1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx95.dtsi" 10 11#define BRD_SM_CTRL_SD3_WAKE 0x8000 12#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 13#define BRD_SM_CTRL_BT_WAKE 0x8002 14#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 15#define BRD_SM_CTRL_BUTTON 0x8004 16 17/ { 18 compatible = "fsl,imx95-15x15-ab2", "fsl,imx95"; 19 model = "NXP i.MX95 CPU on AB2"; 20 21 aliases { 22 ethernet0 = &enetc_port0; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &lpi2c1; 29 i2c1 = &lpi2c2; 30 i2c2 = &lpi2c3; 31 i2c3 = &lpi2c4; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 serial0 = &lpuart1; 35 }; 36 37 chosen { 38 #address-cells = <2>; 39 #size-cells = <2>; 40 stdout-path = &lpuart1; 41 }; 42 43 reg_ab2_ana_pwr: regulator-ab2-ana-pwr { 44 compatible = "regulator-fixed"; 45 regulator-name = "ab2_ana_pwr"; 46 regulator-always-on; 47 regulator-max-microvolt = <3300000>; 48 regulator-min-microvolt = <3300000>; 49 gpio = <&pcal6524 1 GPIO_ACTIVE_HIGH>; 50 enable-active-high; 51 }; 52 53 reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { 54 compatible = "regulator-fixed"; 55 regulator-name = "ab2_vdd_pwr_5v0"; 56 regulator-always-on; 57 regulator-max-microvolt = <3300000>; 58 regulator-min-microvolt = <3300000>; 59 gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>; 60 enable-active-high; 61 }; 62 63 reg_usdhc2_vmmc: regulator-usdhc2 { 64 compatible = "regulator-fixed"; 65 regulator-name = "VDD_SD2_3V3"; 66 off-on-delay-us = <12000>; 67 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 68 pinctrl-names = "default"; 69 regulator-max-microvolt = <3300000>; 70 regulator-min-microvolt = <3300000>; 71 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 72 enable-active-high; 73 }; 74 75 reserved-memory { 76 ranges; 77 #address-cells = <2>; 78 #size-cells = <2>; 79 80 linux_cma: linux,cma { 81 compatible = "shared-dma-pool"; 82 alloc-ranges = <0 0x80000000 0 0x7f000000>; 83 reusable; 84 size = <0 0x3c000000>; 85 linux,cma-default; 86 }; 87 88 vpu_boot: vpu-boot@a0000000 { 89 reg = <0 0xa0000000 0 0x100000>; 90 no-map; 91 }; 92 }; 93 94 sound-ak4458 { 95 compatible = "fsl,imx-audio-card"; 96 model = "ak4458-audio"; 97 98 pri-dai-link { 99 format = "i2s"; 100 link-name = "akcodec"; 101 fsl,mclk-equal-bclk; 102 103 codec { 104 sound-dai = <&ak4458_1>, <&ak4458_2>; 105 }; 106 107 cpu { 108 sound-dai = <&sai2>; 109 }; 110 }; 111 }; 112 113 sound-ak5552 { 114 compatible = "fsl,imx-audio-card"; 115 model = "ak5552-audio"; 116 117 pri-dai-link { 118 format = "i2s"; 119 link-name = "akcodec"; 120 fsl,mclk-equal-bclk; 121 122 codec { 123 sound-dai = <&ak5552>; 124 }; 125 126 cpu { 127 sound-dai = <&sai3>; 128 }; 129 }; 130 }; 131 132 sound-micfil { 133 compatible = "fsl,imx-audio-card"; 134 model = "micfil-audio"; 135 136 pri-dai-link { 137 format = "i2s"; 138 link-name = "micfil hifi"; 139 140 cpu { 141 sound-dai = <&micfil>; 142 }; 143 }; 144 }; 145 146 sound-xcvr { 147 compatible = "fsl,imx-audio-card"; 148 model = "imx-audio-xcvr"; 149 150 pri-dai-link { 151 link-name = "XCVR PCM"; 152 153 cpu { 154 sound-dai = <&xcvr>; 155 }; 156 }; 157 }; 158 159 memory@80000000 { 160 reg = <0x0 0x80000000 0 0x80000000>; 161 device_type = "memory"; 162 }; 163}; 164 165&enetc_port0 { 166 phy-handle = <ðphy0>; 167 phy-mode = "rgmii-id"; 168 pinctrl-0 = <&pinctrl_enetc0>; 169 pinctrl-names = "default"; 170 status = "okay"; 171}; 172 173&lpi2c1 { 174 clock-frequency = <400000>; 175 pinctrl-0 = <&pinctrl_lpi2c1>; 176 pinctrl-names = "default"; 177 status = "disabled"; 178}; 179 180&lpi2c2 { 181 clock-frequency = <400000>; 182 pinctrl-0 = <&pinctrl_lpi2c2>; 183 pinctrl-names = "default"; 184 status = "okay"; 185 186 pcal6524: gpio@22 { 187 compatible = "nxp,pcal6524"; 188 reg = <0x22>; 189 #interrupt-cells = <2>; 190 interrupt-controller; 191 interrupt-parent = <&gpio5>; 192 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 193 #gpio-cells = <2>; 194 gpio-controller; 195 pinctrl-0 = <&pinctrl_pcal6524>; 196 pinctrl-names = "default"; 197 }; 198}; 199 200&lpi2c3 { 201 clock-frequency = <400000>; 202 pinctrl-0 = <&pinctrl_lpi2c3>; 203 pinctrl-names = "default"; 204 status = "okay"; 205 206 ak4458_1: audio-codec@10 { 207 compatible = "asahi-kasei,ak4458"; 208 reg = <0x10>; 209 #sound-dai-cells = <0>; 210 AVDD-supply = <®_ab2_ana_pwr>; 211 DVDD-supply = <®_ab2_ana_pwr>; 212 reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; 213 sound-name-prefix = "0"; 214 }; 215 216 ak4458_3: audio-codec@11 { 217 compatible = "asahi-kasei,ak4458"; 218 reg = <0x11>; 219 #sound-dai-cells = <0>; 220 AVDD-supply = <®_ab2_ana_pwr>; 221 DVDD-supply = <®_ab2_ana_pwr>; 222 reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; 223 status = "disabled"; 224 }; 225 226 ak4458_2: audio-codec@12 { 227 compatible = "asahi-kasei,ak4458"; 228 reg = <0x12>; 229 #sound-dai-cells = <0>; 230 AVDD-supply = <®_ab2_ana_pwr>; 231 DVDD-supply = <®_ab2_ana_pwr>; 232 reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; 233 sound-name-prefix = "1"; 234 }; 235 236 ak5552: audio-codec@13 { 237 compatible = "asahi-kasei,ak5552"; 238 reg = <0x13>; 239 #sound-dai-cells = <0>; 240 AVDD-supply = <®_ab2_ana_pwr>; 241 DVDD-supply = <®_ab2_ana_pwr>; 242 reset-gpios = <&pca6416 3 GPIO_ACTIVE_LOW>; 243 }; 244 245 pca6416: gpio@20 { 246 compatible = "ti,tca6416"; 247 reg = <0x20>; 248 #gpio-cells = <2>; 249 gpio-controller; 250 }; 251}; 252 253&lpi2c4 { 254 clock-frequency = <400000>; 255 pinctrl-0 = <&pinctrl_lpi2c4>; 256 pinctrl-names = "default"; 257 status = "okay"; 258}; 259 260&lpuart1 { 261 /* console */ 262 pinctrl-names = "default"; 263 pinctrl-0 = <&pinctrl_uart1>; 264 status = "okay"; 265}; 266 267&micfil { 268 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 269 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 270 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 271 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 272 <&scmi_clk IMX95_CLK_PDM>; 273 assigned-clock-parents = <0>, <0>, <0>, <0>, 274 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 275 assigned-clock-rates = <3932160000>, 276 <3612672000>, <393216000>, 277 <361267200>, <49152000>; 278 #sound-dai-cells = <0>; 279 pinctrl-0 = <&pinctrl_pdm>; 280 pinctrl-names = "default"; 281 status = "okay"; 282}; 283 284&netc_blk_ctrl { 285 status = "okay"; 286}; 287 288&netc_emdio { 289 pinctrl-0 = <&pinctrl_emdio>; 290 pinctrl-names = "default"; 291 status = "okay"; 292 293 ethphy0: ethernet-phy@1 { 294 reg = <1>; 295 reset-assert-us = <10000>; 296 reset-deassert-us = <80000>; 297 reset-gpios = <&pcal6524 4 GPIO_ACTIVE_LOW>; 298 realtek,clkout-disable; 299 }; 300}; 301 302&netcmix_blk_ctrl { 303 status = "okay"; 304}; 305 306&sai2 { 307 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>, 308 <&scmi_clk IMX95_CLK_SAI2>, <&dummy>, 309 <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>, 310 <&scmi_clk IMX95_CLK_AUDIOPLL2>; 311 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; 312 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 313 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 314 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 315 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 316 <&scmi_clk IMX95_CLK_SAI2>; 317 assigned-clock-parents = <0>, <0>, <0>, <0>, 318 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 319 assigned-clock-rates = <3932160000>, 320 <3612672000>, <393216000>, 321 <361267200>, <12288000>; 322 #sound-dai-cells = <0>; 323 pinctrl-0 = <&pinctrl_sai2>; 324 pinctrl-names = "default"; 325 fsl,sai-asynchronous; 326 fsl,sai-mclk-direction-output; 327 status = "okay"; 328}; 329 330&sai3 { 331 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>, 332 <&scmi_clk IMX95_CLK_SAI3>, <&dummy>, 333 <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>, 334 <&scmi_clk IMX95_CLK_AUDIOPLL2>; 335 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; 336 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 337 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 338 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 339 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 340 <&scmi_clk IMX95_CLK_SAI3>; 341 assigned-clock-parents = <0>, <0>, <0>, <0>, 342 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 343 assigned-clock-rates = <3932160000>, 344 <3612672000>, <393216000>, 345 <361267200>, <12288000>; 346 #sound-dai-cells = <0>; 347 pinctrl-0 = <&pinctrl_sai3>; 348 pinctrl-names = "default"; 349 fsl,sai-asynchronous; 350 fsl,sai-mclk-direction-output; 351 status = "okay"; 352}; 353 354&sai5 { 355 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 356 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 357 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 358 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 359 <&scmi_clk IMX95_CLK_SAI5>; 360 assigned-clock-parents = <0>, <0>, <0>, <0>, 361 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 362 assigned-clock-rates = <3932160000>, 363 <3612672000>, <393216000>, 364 <361267200>, <12288000>; 365 #sound-dai-cells = <0>; 366 pinctrl-0 = <&pinctrl_sai5>; 367 pinctrl-names = "default"; 368 fsl,sai-mclk-direction-output; 369 status = "okay"; 370}; 371 372&scmi_iomuxc { 373 pinctrl_emdio: emdiogrp { 374 fsl,pins = < 375 IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e 376 IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e 377 >; 378 }; 379 380 pinctrl_enetc0: enetc0grp { 381 fsl,pins = < 382 IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e 383 IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e 384 IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e 385 IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e 386 IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e 387 IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e 388 IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e 389 IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e 390 IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e 391 IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e 392 IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e 393 IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e 394 >; 395 }; 396 397 pinctrl_lpi2c1: lpi2c1grp { 398 fsl,pins = < 399 IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e 400 IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e 401 >; 402 }; 403 404 pinctrl_lpi2c2: lpi2c2grp { 405 fsl,pins = < 406 IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e 407 IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e 408 >; 409 }; 410 411 pinctrl_lpi2c3: lpi2c3grp { 412 fsl,pins = < 413 IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 414 IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 415 >; 416 }; 417 418 pinctrl_lpi2c4: lpi2c4grp { 419 fsl,pins = < 420 IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e 421 IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e 422 >; 423 }; 424 425 pinctrl_pcal6524: pcal6524grp { 426 fsl,pins = < 427 IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e 428 >; 429 }; 430 431 pinctrl_pdm: pdmgrp { 432 fsl,pins = < 433 IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e 434 IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e 435 IMX95_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x31e 436 IMX95_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x31e 437 IMX95_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x31e 438 >; 439 }; 440 441 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 442 fsl,pins = < 443 IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e 444 >; 445 }; 446 447 pinctrl_sai2: sai2grp { 448 fsl,pins = < 449 IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e 450 IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e 451 IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e 452 IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e 453 IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e 454 IMX95_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_BIT2 0x31e 455 IMX95_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_BIT3 0x31e 456 IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e 457 IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e 458 IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e 459 IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e 460 IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e 461 IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e 462 IMX95_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_BIT4 0x31e 463 IMX95_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_BIT5 0x31e 464 IMX95_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_BIT6 0x31e 465 IMX95_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_BIT7 0x31e 466 >; 467 }; 468 469 pinctrl_sai3: sai3grp { 470 fsl,pins = < 471 IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e 472 IMX95_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e 473 IMX95_PAD_GPIO_IO19__SAI3_RX_SYNC 0x31e 474 IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e 475 >; 476 }; 477 478 pinctrl_sai5: sai5grp { 479 fsl,pins = < 480 IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x31e 481 IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x31e 482 IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK 0x31e 483 IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC 0x31e 484 485 >; 486 }; 487 488 pinctrl_spdif: spdifgrp { 489 fsl,pins = < 490 IMX95_PAD_GPIO_IO22__SPDIF_IN 0x31e 491 IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x31e 492 >; 493 }; 494 495 pinctrl_uart1: uart1grp { 496 fsl,pins = < 497 IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e 498 IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e 499 >; 500 }; 501 502 pinctrl_usdhc1: usdhc1grp { 503 fsl,pins = < 504 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 505 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 506 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 507 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 508 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 509 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 510 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 511 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 512 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 513 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 514 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 515 >; 516 }; 517 518 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 519 fsl,pins = < 520 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 521 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 522 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 523 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 524 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 525 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 526 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 527 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 528 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 529 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 530 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 531 >; 532 }; 533 534 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 535 fsl,pins = < 536 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe 537 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe 538 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 539 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 540 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 541 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 542 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 543 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 544 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 545 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 546 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 547 >; 548 }; 549 550 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 551 fsl,pins = < 552 IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e 553 >; 554 }; 555 556 pinctrl_usdhc2: usdhc2grp { 557 fsl,pins = < 558 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 559 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 560 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 561 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 562 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 563 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 564 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 565 >; 566 }; 567 568 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 569 fsl,pins = < 570 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 571 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 572 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 573 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 574 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 575 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 576 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 577 >; 578 }; 579 580 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 581 fsl,pins = < 582 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe 583 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe 584 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 585 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 586 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 587 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 588 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 589 >; 590 }; 591}; 592 593&scmi_misc { 594 nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1>, 595 <BRD_SM_CTRL_PCIE1_WAKE 1>, 596 <BRD_SM_CTRL_BT_WAKE 1>, 597 <BRD_SM_CTRL_PCIE2_WAKE 1>, 598 <BRD_SM_CTRL_BUTTON 1>; 599}; 600 601&usb3 { 602 status = "okay"; 603}; 604 605&usb3_dwc3 { 606 adp-disable; 607 dr_mode = "host"; 608 hnp-disable; 609 srp-disable; 610 snps,dis-u1-entry-quirk; 611 snps,dis-u2-entry-quirk; 612 status = "okay"; 613}; 614 615&usb3_phy { 616 status = "okay"; 617}; 618 619&usdhc1 { 620 bus-width = <8>; 621 non-removable; 622 no-sd; 623 no-sdio; 624 pinctrl-0 = <&pinctrl_usdhc1>; 625 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 626 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 627 pinctrl-3 = <&pinctrl_usdhc1>; 628 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 629 fsl,tuning-step = <1>; 630 status = "okay"; 631}; 632 633&usdhc2 { 634 bus-width = <4>; 635 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 636 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 637 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 638 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 639 pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 640 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 641 vmmc-supply = <®_usdhc2_vmmc>; 642 status = "okay"; 643}; 644 645&xcvr { 646 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 647 <&scmi_clk IMX95_CLK_SPDIF>, 648 <&dummy>, 649 <&scmi_clk IMX95_CLK_AUDIOXCVR>, 650 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 651 <&scmi_clk IMX95_CLK_AUDIOPLL2>; 652 clock-names = "ipg", "phy", "spba", "pll_ipg", "pll8k", "pll11k"; 653 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 654 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 655 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 656 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 657 <&scmi_clk IMX95_CLK_SPDIF>, 658 <&scmi_clk IMX95_CLK_AUDIOXCVR>; 659 assigned-clock-parents = <0>, <0>, <0>, <0>, 660 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 661 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 662 assigned-clock-rates = <3932160000>, <3612672000>, 663 <393216000>, <361267200>, 664 <12288000>, <0>; 665 #sound-dai-cells = <0>; 666 pinctrl-0 = <&pinctrl_spdif>; 667 pinctrl-names = "default"; 668 status = "okay"; 669}; 670