1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024-2025 NXP 4 */ 5 6#include <dt-bindings/dma/fsl-edma.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11#include "imx94-clock.h" 12#include "imx94-pinfunc.h" 13#include "imx94-power.h" 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 interrupt-parent = <&gic>; 19 20 osc_24m: clock-24m { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "osc_24m"; 25 }; 26 27 dummy: clock-dummy { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <0>; 31 clock-output-names = "dummy"; 32 }; 33 34 clk_ext1: clock-ext1 { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <133000000>; 38 clock-output-names = "clk_ext1"; 39 }; 40 41 sai1_mclk: clock-sai1-mclk1 { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 clock-output-names = "sai1_mclk"; 46 }; 47 48 sai2_mclk: clock-sai2-mclk1 { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <0>; 52 clock-output-names = "sai2_mclk"; 53 }; 54 55 sai3_mclk: clock-sai3-mclk1 { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 59 clock-output-names = "sai3_mclk"; 60 }; 61 62 sai4_mclk: clock-sai4-mclk1 { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <0>; 66 clock-output-names = "sai4_mclk"; 67 }; 68 69 firmware { 70 scmi { 71 compatible = "arm,scmi"; 72 #address-cells = <1>; 73 #size-cells = <0>; 74 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; 75 shmem = <&scmi_buf0>, <&scmi_buf1>; 76 arm,max-rx-timeout-ms = <5000>; 77 78 scmi_devpd: protocol@11 { 79 reg = <0x11>; 80 #power-domain-cells = <1>; 81 }; 82 83 scmi_sys_power: protocol@12 { 84 reg = <0x12>; 85 }; 86 87 scmi_perf: protocol@13 { 88 reg = <0x13>; 89 #power-domain-cells = <1>; 90 }; 91 92 scmi_clk: protocol@14 { 93 reg = <0x14>; 94 #clock-cells = <1>; 95 }; 96 97 scmi_iomuxc: protocol@19 { 98 reg = <0x19>; 99 }; 100 101 scmi_bbm: protocol@81 { 102 reg = <0x81>; 103 }; 104 105 scmi_misc: protocol@84 { 106 reg = <0x84>; 107 }; 108 }; 109 }; 110 111 pmu { 112 compatible = "arm,cortex-a55-pmu"; 113 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 114 }; 115 116 psci { 117 compatible = "arm,psci-1.0"; 118 method = "smc"; 119 }; 120 121 timer { 122 compatible = "arm,armv8-timer"; 123 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 124 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 125 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 126 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 127 clock-frequency = <24000000>; 128 interrupt-parent = <&gic>; 129 arm,no-tick-in-suspend; 130 }; 131 132 gic: interrupt-controller@48000000 { 133 compatible = "arm,gic-v3"; 134 reg = <0 0x48000000 0 0x10000>, 135 <0 0x48060000 0 0xc0000>; 136 ranges; 137 #interrupt-cells = <3>; 138 interrupt-controller; 139 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 140 #address-cells = <2>; 141 #size-cells = <2>; 142 dma-noncoherent; 143 interrupt-parent = <&gic>; 144 145 its: msi-controller@48040000 { 146 compatible = "arm,gic-v3-its"; 147 reg = <0 0x48040000 0 0x20000>; 148 #msi-cells = <1>; 149 dma-noncoherent; 150 msi-controller; 151 }; 152 }; 153 154 soc { 155 compatible = "simple-bus"; 156 ranges; 157 #address-cells = <2>; 158 #size-cells = <2>; 159 160 aips2: bus@42000000 { 161 compatible = "fsl,aips-bus", "simple-bus"; 162 reg = <0x0 0x42000000 0x0 0x800000>; 163 ranges = <0x42000000 0x0 0x42000000 0x8000000>; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 167 edma2: dma-controller@42000000 { 168 compatible = "fsl,imx94-edma5", "fsl,imx95-edma5"; 169 reg = <0x42000000 0x210000>; 170 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 171 clock-names = "dma"; 172 #dma-cells = <3>; 173 dma-channels = <64>; 174 interrupts-extended = <&a55_irqsteer 0>, <&a55_irqsteer 1>, 175 <&a55_irqsteer 2>, <&a55_irqsteer 3>, 176 <&a55_irqsteer 4>, <&a55_irqsteer 5>, 177 <&a55_irqsteer 6>, <&a55_irqsteer 7>, 178 <&a55_irqsteer 8>, <&a55_irqsteer 9>, 179 <&a55_irqsteer 10>, <&a55_irqsteer 11>, 180 <&a55_irqsteer 12>, <&a55_irqsteer 13>, 181 <&a55_irqsteer 14>, <&a55_irqsteer 15>, 182 <&a55_irqsteer 16>, <&a55_irqsteer 17>, 183 <&a55_irqsteer 18>, <&a55_irqsteer 19>, 184 <&a55_irqsteer 20>, <&a55_irqsteer 21>, 185 <&a55_irqsteer 22>, <&a55_irqsteer 23>, 186 <&a55_irqsteer 24>, <&a55_irqsteer 25>, 187 <&a55_irqsteer 26>, <&a55_irqsteer 27>, 188 <&a55_irqsteer 28>, <&a55_irqsteer 29>, 189 <&a55_irqsteer 30>, <&a55_irqsteer 31>, 190 <&a55_irqsteer 64>, <&a55_irqsteer 65>, 191 <&a55_irqsteer 66>, <&a55_irqsteer 67>, 192 <&a55_irqsteer 68>, <&a55_irqsteer 69>, 193 <&a55_irqsteer 70>, <&a55_irqsteer 71>, 194 <&a55_irqsteer 72>, <&a55_irqsteer 73>, 195 <&a55_irqsteer 74>, <&a55_irqsteer 75>, 196 <&a55_irqsteer 76>, <&a55_irqsteer 77>, 197 <&a55_irqsteer 78>, <&a55_irqsteer 79>, 198 <&a55_irqsteer 80>, <&a55_irqsteer 81>, 199 <&a55_irqsteer 82>, <&a55_irqsteer 83>, 200 <&a55_irqsteer 84>, <&a55_irqsteer 85>, 201 <&a55_irqsteer 86>, <&a55_irqsteer 87>, 202 <&a55_irqsteer 88>, <&a55_irqsteer 89>, 203 <&a55_irqsteer 90>, <&a55_irqsteer 91>, 204 <&a55_irqsteer 92>, <&a55_irqsteer 93>, 205 <&a55_irqsteer 94>, <&a55_irqsteer 95>; 206 }; 207 208 mu10: mailbox@42430000 { 209 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 210 reg = <0x42430000 0x10000>; 211 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 213 #mbox-cells = <2>; 214 status = "disabled"; 215 }; 216 217 i3c2: i3c@42520000 { 218 compatible = "silvaco,i3c-master-v1"; 219 reg = <0x42520000 0x10000>; 220 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 221 #address-cells = <3>; 222 #size-cells = <0>; 223 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 224 <&scmi_clk IMX94_CLK_I3C2SLOW>, 225 <&dummy>; 226 clock-names = "pclk", "fast_clk", "slow_clk"; 227 status = "disabled"; 228 }; 229 230 lpi2c3: i2c@42530000 { 231 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 232 reg = <0x42530000 0x10000>; 233 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 clocks = <&scmi_clk IMX94_CLK_LPI2C3>, 237 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 238 clock-names = "per", "ipg"; 239 dmas = <&edma2 5 0 0>, <&edma2 6 0 FSL_EDMA_RX>; 240 dma-names = "tx", "rx"; 241 status = "disabled"; 242 }; 243 244 lpi2c4: i2c@42540000 { 245 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 246 reg = <0x42540000 0x10000>; 247 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 clocks = <&scmi_clk IMX94_CLK_LPI2C4>, 251 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 252 clock-names = "per", "ipg"; 253 dmas = <&edma4 4 0 0>, <&edma4 5 0 FSL_EDMA_RX>; 254 dma-names = "tx", "rx"; 255 status = "disabled"; 256 }; 257 258 lpspi3: spi@42550000 { 259 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 260 reg = <0x42550000 0x10000>; 261 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 clocks = <&scmi_clk IMX94_CLK_LPSPI3>, 265 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 266 clock-names = "per", "ipg"; 267 dmas = <&edma2 7 0 0>, <&edma2 8 0 FSL_EDMA_RX>; 268 dma-names = "tx", "rx"; 269 status = "disabled"; 270 }; 271 272 lpspi4: spi@42560000 { 273 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 274 reg = <0x42560000 0x10000>; 275 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 clocks = <&scmi_clk IMX94_CLK_LPSPI4>, 279 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 280 clock-names = "per", "ipg"; 281 dmas = <&edma4 6 0 0>, <&edma4 7 0 FSL_EDMA_RX>; 282 dma-names = "tx", "rx"; 283 status = "disabled"; 284 }; 285 286 lpuart3: serial@42570000 { 287 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 288 "fsl,imx7ulp-lpuart"; 289 reg = <0x42570000 0x1000>; 290 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&scmi_clk IMX94_CLK_LPUART3>; 292 clock-names = "ipg"; 293 dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 9 0 0>; 294 dma-names = "rx", "tx"; 295 status = "disabled"; 296 }; 297 298 lpuart4: serial@42580000 { 299 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 300 "fsl,imx7ulp-lpuart"; 301 reg = <0x42580000 0x1000>; 302 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&scmi_clk IMX94_CLK_LPUART4>; 304 clock-names = "ipg"; 305 dmas = <&edma4 10 0 FSL_EDMA_RX>, <&edma4 9 0 0>; 306 dma-names = "rx", "tx"; 307 status = "disabled"; 308 }; 309 310 lpuart5: serial@42590000 { 311 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 312 "fsl,imx7ulp-lpuart"; 313 reg = <0x42590000 0x1000>; 314 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&scmi_clk IMX94_CLK_LPUART5>; 316 clock-names = "ipg"; 317 dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 11 0 0>; 318 dma-names = "rx", "tx"; 319 status = "disabled"; 320 }; 321 322 lpuart6: serial@425a0000 { 323 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 324 "fsl,imx7ulp-lpuart"; 325 reg = <0x425a0000 0x1000>; 326 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&scmi_clk IMX94_CLK_LPUART6>; 328 clock-names = "ipg"; 329 dmas = <&edma4 12 0 FSL_EDMA_RX>, <&edma4 11 0 0>; 330 dma-names = "rx", "tx"; 331 status = "disabled"; 332 }; 333 334 flexcan2: can@425b0000 { 335 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; 336 reg = <0x425b0000 0x10000>; 337 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 339 <&scmi_clk IMX94_CLK_CAN2>; 340 clock-names = "ipg", "per"; 341 assigned-clocks = <&scmi_clk IMX94_CLK_CAN2>; 342 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; 343 assigned-clock-rates = <80000000>; 344 fsl,clk-source = /bits/ 8 <0>; 345 status = "disabled"; 346 }; 347 348 flexcan3: can@425e0000 { 349 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; 350 reg = <0x425e0000 0x10000>; 351 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 353 <&scmi_clk IMX94_CLK_CAN3>; 354 clock-names = "ipg", "per"; 355 assigned-clocks = <&scmi_clk IMX94_CLK_CAN3>; 356 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; 357 assigned-clock-rates = <80000000>; 358 fsl,clk-source = /bits/ 8 <0>; 359 status = "disabled"; 360 }; 361 362 flexcan4: can@425f0000 { 363 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; 364 reg = <0x425f0000 0x10000>; 365 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 367 <&scmi_clk IMX94_CLK_CAN4>; 368 clock-names = "ipg", "per"; 369 assigned-clocks = <&scmi_clk IMX94_CLK_CAN4>; 370 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; 371 assigned-clock-rates = <80000000>; 372 fsl,clk-source = /bits/ 8 <0>; 373 status = "disabled"; 374 }; 375 376 flexcan5: can@42600000 { 377 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; 378 reg = <0x42600000 0x10000>; 379 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 381 <&scmi_clk IMX94_CLK_CAN5>; 382 clock-names = "ipg", "per"; 383 assigned-clocks = <&scmi_clk IMX94_CLK_CAN5>; 384 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; 385 assigned-clock-rates = <80000000>; 386 fsl,clk-source = /bits/ 8 <0>; 387 status = "disabled"; 388 }; 389 390 sai2: sai@42650000 { 391 compatible = "fsl,imx94-sai", "fsl,imx95-sai"; 392 reg = <0x42650000 0x10000>; 393 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, <&dummy>, 395 <&scmi_clk IMX94_CLK_SAI2>, <&dummy>, <&dummy>; 396 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 397 dmas = <&edma2 30 0 FSL_EDMA_RX>, <&edma2 29 0 0>; 398 dma-names = "rx", "tx"; 399 #sound-dai-cells = <0>; 400 status = "disabled"; 401 }; 402 403 sai3: sai@42660000 { 404 compatible = "fsl,imx94-sai", "fsl,imx95-sai"; 405 reg = <0x42660000 0x10000>; 406 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, <&dummy>, 408 <&scmi_clk IMX94_CLK_SAI3>, <&dummy>, <&dummy>; 409 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 410 dmas = <&edma2 32 0 FSL_EDMA_RX>, <&edma2 31 0 0>; 411 dma-names = "rx", "tx"; 412 #sound-dai-cells = <0>; 413 status = "disabled"; 414 }; 415 416 sai4: sai@42670000 { 417 compatible = "fsl,imx94-sai", "fsl,imx95-sai"; 418 reg = <0x42670000 0x10000>; 419 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, <&dummy>, 421 <&scmi_clk IMX94_CLK_SAI4>, <&dummy>, <&dummy>; 422 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 423 dmas = <&edma2 36 0 FSL_EDMA_RX>, <&edma2 35 0 0>; 424 dma-names = "rx", "tx"; 425 #sound-dai-cells = <0>; 426 status = "disabled"; 427 }; 428 429 lpuart7: serial@42690000 { 430 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 431 "fsl,imx7ulp-lpuart"; 432 reg = <0x42690000 0x1000>; 433 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&scmi_clk IMX94_CLK_LPUART7>; 435 clock-names = "ipg"; 436 dmas = <&edma2 46 0 FSL_EDMA_RX>, <&edma2 45 0 0>; 437 dma-names = "rx", "tx"; 438 status = "disabled"; 439 }; 440 441 lpuart8: serial@426a0000 { 442 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 443 "fsl,imx7ulp-lpuart"; 444 reg = <0x426a0000 0x1000>; 445 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&scmi_clk IMX94_CLK_LPUART8>; 447 clock-names = "ipg"; 448 dmas = <&edma4 39 0 FSL_EDMA_RX>, <&edma4 38 0 0>; 449 dma-names = "rx", "tx"; 450 status = "disabled"; 451 }; 452 453 lpi2c5: i2c@426b0000 { 454 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 455 reg = <0x426b0000 0x10000>; 456 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 clocks = <&scmi_clk IMX94_CLK_LPI2C5>, 460 <&scmi_clk IMX94_CLK_BUSAON>; 461 clock-names = "per", "ipg"; 462 dmas = <&edma2 37 0 0>, <&edma2 38 0 FSL_EDMA_RX>; 463 dma-names = "tx", "rx"; 464 status = "disabled"; 465 }; 466 467 lpi2c6: i2c@426c0000 { 468 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 469 reg = <0x426c0000 0x10000>; 470 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 clocks = <&scmi_clk IMX94_CLK_LPI2C6>, 474 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 475 clock-names = "per", "ipg"; 476 dmas = <&edma4 30 0 0>, <&edma4 31 0 FSL_EDMA_RX>; 477 dma-names = "tx", "rx"; 478 status = "disabled"; 479 }; 480 481 lpi2c7: i2c@426d0000 { 482 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 483 reg = <0x426d0000 0x10000>; 484 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 clocks = <&scmi_clk IMX94_CLK_LPI2C7>, 488 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 489 clock-names = "per", "ipg"; 490 dmas = <&edma2 39 0 0>, <&edma2 40 0 FSL_EDMA_RX>; 491 dma-names = "tx", "rx"; 492 status = "disabled"; 493 }; 494 495 lpi2c8: i2c@426e0000 { 496 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 497 reg = <0x426e0000 0x10000>; 498 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 clocks = <&scmi_clk IMX94_CLK_LPI2C8>, 502 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 503 clock-names = "per", "ipg"; 504 dmas = <&edma4 32 0 0>, <&edma4 33 0 FSL_EDMA_RX>; 505 dma-names = "tx", "rx"; 506 status = "disabled"; 507 }; 508 509 lpspi5: spi@426f0000 { 510 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 511 reg = <0x426f0000 0x10000>; 512 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 clocks = <&scmi_clk IMX94_CLK_LPSPI5>, 516 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 517 clock-names = "per", "ipg"; 518 dmas = <&edma2 41 0 0>, <&edma2 42 0 FSL_EDMA_RX>; 519 dma-names = "tx", "rx"; 520 status = "disabled"; 521 }; 522 523 lpspi6: spi@42700000 { 524 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 525 reg = <0x42700000 0x10000>; 526 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 clocks = <&scmi_clk IMX94_CLK_LPSPI6>, 530 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 531 clock-names = "per", "ipg"; 532 dmas = <&edma4 34 0 0>, <&edma4 35 0 FSL_EDMA_RX>; 533 dma-names = "tx", "rx"; 534 status = "disabled"; 535 }; 536 537 lpspi7: spi@42710000 { 538 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 539 reg = <0x42710000 0x10000>; 540 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 clocks = <&scmi_clk IMX94_CLK_LPSPI7>, 544 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 545 clock-names = "per", "ipg"; 546 dmas = <&edma2 43 0 0>, <&edma2 44 0 FSL_EDMA_RX>; 547 dma-names = "tx", "rx"; 548 status = "disabled"; 549 }; 550 551 lpspi8: spi@42720000 { 552 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 553 reg = <0x42720000 0x10000>; 554 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 clocks = <&scmi_clk IMX94_CLK_LPSPI8>, 558 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 559 clock-names = "per", "ipg"; 560 dmas = <&edma4 36 0 0>, <&edma4 37 0 FSL_EDMA_RX>; 561 dma-names = "tx", "rx"; 562 status = "disabled"; 563 }; 564 565 mu11: mailbox@42730000 { 566 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 567 reg = <0x42730000 0x10000>; 568 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 570 #mbox-cells = <2>; 571 status = "disabled"; 572 }; 573 574 edma4: dma-controller@42df0000 { 575 compatible = "fsl,imx94-edma5", "fsl,imx95-edma5"; 576 reg = <0x42df0000 0x210000>; 577 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 578 clock-names = "dma"; 579 #dma-cells = <3>; 580 dma-channels = <64>; 581 interrupts-extended = <&a55_irqsteer 128>, <&a55_irqsteer 129>, 582 <&a55_irqsteer 130>, <&a55_irqsteer 131>, 583 <&a55_irqsteer 132>, <&a55_irqsteer 133>, 584 <&a55_irqsteer 134>, <&a55_irqsteer 135>, 585 <&a55_irqsteer 136>, <&a55_irqsteer 137>, 586 <&a55_irqsteer 138>, <&a55_irqsteer 139>, 587 <&a55_irqsteer 140>, <&a55_irqsteer 141>, 588 <&a55_irqsteer 142>, <&a55_irqsteer 143>, 589 <&a55_irqsteer 144>, <&a55_irqsteer 145>, 590 <&a55_irqsteer 146>, <&a55_irqsteer 147>, 591 <&a55_irqsteer 148>, <&a55_irqsteer 149>, 592 <&a55_irqsteer 150>, <&a55_irqsteer 151>, 593 <&a55_irqsteer 152>, <&a55_irqsteer 153>, 594 <&a55_irqsteer 154>, <&a55_irqsteer 155>, 595 <&a55_irqsteer 156>, <&a55_irqsteer 157>, 596 <&a55_irqsteer 158>, <&a55_irqsteer 159>, 597 <&a55_irqsteer 192>, <&a55_irqsteer 193>, 598 <&a55_irqsteer 194>, <&a55_irqsteer 195>, 599 <&a55_irqsteer 196>, <&a55_irqsteer 197>, 600 <&a55_irqsteer 198>, <&a55_irqsteer 199>, 601 <&a55_irqsteer 200>, <&a55_irqsteer 201>, 602 <&a55_irqsteer 202>, <&a55_irqsteer 203>, 603 <&a55_irqsteer 204>, <&a55_irqsteer 205>, 604 <&a55_irqsteer 206>, <&a55_irqsteer 207>, 605 <&a55_irqsteer 208>, <&a55_irqsteer 209>, 606 <&a55_irqsteer 210>, <&a55_irqsteer 211>, 607 <&a55_irqsteer 212>, <&a55_irqsteer 213>, 608 <&a55_irqsteer 214>, <&a55_irqsteer 215>, 609 <&a55_irqsteer 216>, <&a55_irqsteer 217>, 610 <&a55_irqsteer 218>, <&a55_irqsteer 219>, 611 <&a55_irqsteer 220>, <&a55_irqsteer 221>, 612 <&a55_irqsteer 222>, <&a55_irqsteer 223>; 613 }; 614 }; 615 616 aips3: bus@42800000 { 617 compatible = "fsl,aips-bus", "simple-bus"; 618 reg = <0 0x42800000 0 0x800000>; 619 ranges = <0x42800000 0x0 0x42800000 0x800000>, 620 <0x28000000 0x0 0x28000000 0x1000000>; 621 #address-cells = <1>; 622 #size-cells = <1>; 623 624 usdhc1: mmc@42850000 { 625 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; 626 reg = <0x42850000 0x10000>; 627 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 629 <&scmi_clk IMX94_CLK_WAKEUPAXI>, 630 <&scmi_clk IMX94_CLK_USDHC1>; 631 clock-names = "ipg", "ahb", "per"; 632 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC1>; 633 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>; 634 assigned-clock-rates = <400000000>; 635 bus-width = <8>; 636 fsl,tuning-start-tap = <1>; 637 fsl,tuning-step = <2>; 638 status = "disabled"; 639 }; 640 641 usdhc2: mmc@42860000 { 642 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; 643 reg = <0x42860000 0x10000>; 644 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 646 <&scmi_clk IMX94_CLK_WAKEUPAXI>, 647 <&scmi_clk IMX94_CLK_USDHC2>; 648 clock-names = "ipg", "ahb", "per"; 649 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC2>; 650 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>; 651 assigned-clock-rates = <200000000>; 652 bus-width = <4>; 653 fsl,tuning-start-tap = <1>; 654 fsl,tuning-step = <2>; 655 status = "disabled"; 656 }; 657 658 usdhc3: mmc@42880000 { 659 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; 660 reg = <0x42880000 0x10000>; 661 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 663 <&scmi_clk IMX94_CLK_WAKEUPAXI>, 664 <&scmi_clk IMX94_CLK_USDHC3>; 665 clock-names = "ipg", "ahb", "per"; 666 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC3>; 667 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>; 668 assigned-clock-rates = <200000000>; 669 bus-width = <4>; 670 fsl,tuning-start-tap = <1>; 671 fsl,tuning-step = <2>; 672 status = "disabled"; 673 }; 674 675 lpuart9: serial@42a50000 { 676 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 677 "fsl,imx7ulp-lpuart"; 678 reg = <0x42a50000 0x1000>; 679 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&scmi_clk IMX94_CLK_LPUART10>; 681 clock-names = "ipg"; 682 dmas = <&edma2 51 0 FSL_EDMA_RX>, <&edma2 50 0 0>; 683 dma-names = "rx", "tx"; 684 status = "disabled"; 685 }; 686 687 lpuart10: serial@42a60000 { 688 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 689 "fsl,imx7ulp-lpuart"; 690 reg = <0x42a60000 0x1000>; 691 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&scmi_clk IMX94_CLK_LPUART10>; 693 clock-names = "ipg"; 694 dmas = <&edma4 47 0 FSL_EDMA_RX>, <&edma4 46 0 0>; 695 dma-names = "rx", "tx"; 696 status = "disabled"; 697 }; 698 699 lpuart11: serial@42a70000 { 700 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 701 "fsl,imx7ulp-lpuart"; 702 reg = <0x42a70000 0x1000>; 703 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&scmi_clk IMX94_CLK_LPUART11>; 705 clock-names = "ipg"; 706 dmas = <&edma2 53 0 FSL_EDMA_RX>, <&edma2 52 0 0>; 707 dma-names = "rx", "tx"; 708 status = "disabled"; 709 }; 710 711 lpuart12: serial@42a80000 { 712 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 713 "fsl,imx7ulp-lpuart"; 714 reg = <0x42a80000 0x1000>; 715 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&scmi_clk IMX94_CLK_LPUART12>; 717 clock-names = "ipg"; 718 dmas = <&edma4 49 0 FSL_EDMA_RX>, <&edma4 48 0 0>; 719 dma-names = "rx", "tx"; 720 status = "disabled"; 721 }; 722 723 mu12: mailbox@42ac0000 { 724 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 725 reg = <0x42ac0000 0x10000>; 726 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 728 #mbox-cells = <2>; 729 status = "disabled"; 730 }; 731 732 mu13: mailbox@42ae0000 { 733 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 734 reg = <0x42ae0000 0x10000>; 735 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 737 #mbox-cells = <2>; 738 status = "disabled"; 739 }; 740 741 mu14: mailbox@42b00000 { 742 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 743 reg = <0x42b00000 0x10000>; 744 interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 746 #mbox-cells = <2>; 747 status = "disabled"; 748 }; 749 750 mu15: mailbox@42b20000 { 751 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 752 reg = <0x42b20000 0x10000>; 753 interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 755 #mbox-cells = <2>; 756 status = "disabled"; 757 }; 758 759 mu16: mailbox@42b40000 { 760 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 761 reg = <0x42b40000 0x10000>; 762 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 764 #mbox-cells = <2>; 765 status = "disabled"; 766 }; 767 768 mu17: mailbox@42b60000 { 769 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 770 reg = <0x42b60000 0x10000>; 771 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 773 #mbox-cells = <2>; 774 status = "disabled"; 775 }; 776 }; 777 778 gpio2: gpio@43810000 { 779 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 780 reg = <0x0 0x43810000 0x0 0x1000>; 781 #interrupt-cells = <2>; 782 interrupt-controller; 783 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 785 #gpio-cells = <2>; 786 gpio-controller; 787 gpio-ranges = <&scmi_iomuxc 0 4 32>; 788 }; 789 790 gpio3: gpio@43820000 { 791 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 792 reg = <0x0 0x43820000 0x0 0x1000>; 793 #interrupt-cells = <2>; 794 interrupt-controller; 795 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 797 #gpio-cells = <2>; 798 gpio-controller; 799 gpio-ranges = <&scmi_iomuxc 0 36 26>; 800 }; 801 802 gpio4: gpio@43840000 { 803 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 804 reg = <0x0 0x43840000 0x0 0x1000>; 805 #interrupt-cells = <2>; 806 interrupt-controller; 807 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 809 #gpio-cells = <2>; 810 gpio-controller; 811 gpio-ranges = <&scmi_iomuxc 0 62 4>, <&scmi_iomuxc 4 0 4>, 812 <&scmi_iomuxc 8 140 12>, <&scmi_iomuxc 20 164 12>; 813 }; 814 815 gpio5: gpio@43850000 { 816 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 817 reg = <0x0 0x43850000 0x0 0x1000>; 818 #interrupt-cells = <2>; 819 interrupt-controller; 820 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 822 #gpio-cells = <2>; 823 gpio-controller; 824 gpio-ranges = <&scmi_iomuxc 0 108 32>; 825 }; 826 827 gpio6: gpio@43860000 { 828 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 829 reg = <0x0 0x43860000 0x0 0x1000>; 830 #interrupt-cells = <2>; 831 interrupt-controller; 832 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 834 #gpio-cells = <2>; 835 gpio-controller; 836 gpio-ranges = <&scmi_iomuxc 0 66 32>; 837 }; 838 839 gpio7: gpio@43870000 { 840 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 841 reg = <0x0 0x43870000 0x0 0x1000>; 842 #interrupt-cells = <2>; 843 interrupt-controller; 844 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 846 #gpio-cells = <2>; 847 gpio-controller; 848 gpio-ranges = <&scmi_iomuxc 0 98 10>, <&scmi_iomuxc 16 152 12>; 849 }; 850 851 aips1: bus@44000000 { 852 compatible = "fsl,aips-bus", "simple-bus"; 853 reg = <0x0 0x44000000 0x0 0x800000>; 854 ranges = <0x44000000 0x0 0x44000000 0x800000>; 855 #address-cells = <1>; 856 #size-cells = <1>; 857 858 edma1: dma-controller@44000000 { 859 compatible = "fsl,imx94-edma3", "fsl,imx93-edma3"; 860 reg = <0x44000000 0x210000>; 861 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&scmi_clk IMX94_CLK_BUSAON>; 895 clock-names = "dma"; 896 #dma-cells = <3>; 897 dma-channels = <32>; 898 }; 899 900 mu1: mailbox@44220000 { 901 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 902 reg = <0x44220000 0x10000>; 903 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&scmi_clk IMX94_CLK_BUSAON>; 905 #mbox-cells = <2>; 906 status = "disabled"; 907 }; 908 909 system_counter: timer@44290000 { 910 compatible = "nxp,imx94-sysctr-timer", "nxp,imx95-sysctr-timer"; 911 reg = <0x44290000 0x30000>; 912 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&osc_24m>; 914 clock-names = "per"; 915 nxp,no-divider; 916 }; 917 918 tpm1: pwm@44310000 { 919 compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm"; 920 reg = <0x44310000 0x1000>; 921 clocks = <&scmi_clk IMX94_CLK_BUSAON>; 922 #pwm-cells = <3>; 923 status = "disabled"; 924 }; 925 926 tpm2: pwm@44320000 { 927 compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm"; 928 reg = <0x44320000 0x1000>; 929 clocks = <&scmi_clk IMX94_CLK_TPM2>; 930 #pwm-cells = <3>; 931 status = "disabled"; 932 }; 933 934 i3c1: i3c@44330000 { 935 compatible = "silvaco,i3c-master-v1"; 936 reg = <0x44330000 0x10000>; 937 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 938 #address-cells = <3>; 939 #size-cells = <0>; 940 clocks = <&scmi_clk IMX94_CLK_BUSAON>, 941 <&scmi_clk IMX94_CLK_I3C1SLOW>, 942 <&dummy>; 943 clock-names = "pclk", "fast_clk", "slow_clk"; 944 status = "disabled"; 945 }; 946 947 lpi2c1: i2c@44340000 { 948 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 949 reg = <0x44340000 0x10000>; 950 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 clocks = <&scmi_clk IMX94_CLK_LPI2C1>, 954 <&scmi_clk IMX94_CLK_BUSAON>; 955 clock-names = "per", "ipg"; 956 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX>; 957 dma-names = "tx", "rx"; 958 status = "disabled"; 959 }; 960 961 lpi2c2: i2c@44350000 { 962 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 963 reg = <0x44350000 0x10000>; 964 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 clocks = <&scmi_clk IMX94_CLK_LPI2C2>, 968 <&scmi_clk IMX94_CLK_BUSAON>; 969 clock-names = "per", "ipg"; 970 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX>; 971 dma-names = "tx", "rx"; 972 status = "disabled"; 973 }; 974 975 lpspi1: spi@44360000 { 976 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 977 reg = <0x44360000 0x10000>; 978 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 979 #address-cells = <1>; 980 #size-cells = <0>; 981 clocks = <&scmi_clk IMX94_CLK_LPSPI2>, 982 <&scmi_clk IMX94_CLK_BUSAON>; 983 clock-names = "per", "ipg"; 984 dmas = <&edma1 16 0 0>, <&edma1 17 0 FSL_EDMA_RX>; 985 dma-names = "tx", "rx"; 986 status = "disabled"; 987 }; 988 989 lpspi2: spi@44370000 { 990 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 991 reg = <0x44370000 0x10000>; 992 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 clocks = <&scmi_clk IMX94_CLK_LPSPI2>, 996 <&scmi_clk IMX94_CLK_BUSAON>; 997 clock-names = "per", "ipg"; 998 dmas = <&edma1 18 0 0>, <&edma1 19 0 FSL_EDMA_RX>; 999 dma-names = "tx", "rx"; 1000 status = "disabled"; 1001 }; 1002 1003 lpuart1: serial@44380000 { 1004 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 1005 "fsl,imx7ulp-lpuart"; 1006 reg = <0x44380000 0x1000>; 1007 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&scmi_clk IMX94_CLK_LPUART1>; 1009 clock-names = "ipg"; 1010 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; 1011 dma-names = "rx", "tx"; 1012 status = "disabled"; 1013 }; 1014 1015 lpuart2: serial@44390000 { 1016 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 1017 "fsl,imx7ulp-lpuart"; 1018 reg = <0x44390000 0x1000>; 1019 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&scmi_clk IMX94_CLK_LPUART2>; 1021 clock-names = "ipg"; 1022 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; 1023 dma-names = "rx", "tx"; 1024 status = "disabled"; 1025 }; 1026 1027 flexcan1: can@443a0000 { 1028 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; 1029 reg = <0x443a0000 0x10000>; 1030 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1031 status = "disabled"; 1032 }; 1033 1034 sai1: sai@443b0000 { 1035 compatible = "fsl,imx94-sai", "fsl,imx95-sai"; 1036 reg = <0x443b0000 0x10000>; 1037 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&scmi_clk IMX94_CLK_BUSAON>, <&dummy>, 1039 <&scmi_clk IMX94_CLK_SAI1>, <&dummy>, 1040 <&dummy>, <&dummy>; 1041 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1042 dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; 1043 dma-names = "rx", "tx"; 1044 #sound-dai-cells = <0>; 1045 status = "disabled"; 1046 }; 1047 1048 adc1: adc@44530000 { 1049 compatible = "nxp,imx94-adc", "nxp,imx93-adc"; 1050 reg = <0x44530000 0x10000>; 1051 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&scmi_clk IMX94_CLK_ADC>; 1055 clock-names = "ipg"; 1056 #io-channel-cells = <1>; 1057 status = "disabled"; 1058 }; 1059 1060 mu2: mailbox@445b0000 { 1061 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 1062 reg = <0x445b0000 0x1000>; 1063 ranges; 1064 interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 1065 #address-cells = <1>; 1066 #size-cells = <1>; 1067 #mbox-cells = <2>; 1068 1069 sram0: sram@445b1000 { 1070 compatible = "mmio-sram"; 1071 reg = <0x445b1000 0x400>; 1072 ranges = <0x0 0x445b1000 0x400>; 1073 #address-cells = <1>; 1074 #size-cells = <1>; 1075 1076 scmi_buf0: scmi-sram-section@0 { 1077 compatible = "arm,scmi-shmem"; 1078 reg = <0x0 0x80>; 1079 }; 1080 1081 scmi_buf1: scmi-sram-section@80 { 1082 compatible = "arm,scmi-shmem"; 1083 reg = <0x80 0x80>; 1084 }; 1085 }; 1086 }; 1087 1088 mu3: mailbox@445d0000 { 1089 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 1090 reg = <0x445d0000 0x10000>; 1091 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1092 #mbox-cells = <2>; 1093 status = "disabled"; 1094 }; 1095 1096 mu4: mailbox@445f0000 { 1097 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 1098 reg = <0x445f0000 0x10000>; 1099 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1100 #mbox-cells = <2>; 1101 status = "disabled"; 1102 }; 1103 1104 mu6: mailbox@44630000 { 1105 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 1106 reg = <0x44630000 0x10000>; 1107 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1108 #mbox-cells = <2>; 1109 status = "disabled"; 1110 }; 1111 1112 a55_irqsteer: interrupt-controller@446a0000 { 1113 compatible = "fsl,imx94-irqsteer", "fsl,imx-irqsteer"; 1114 reg = <0x446a0000 0x1000>; 1115 #interrupt-cells = <1>; 1116 interrupt-controller; 1117 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&scmi_clk IMX94_CLK_BUSAON>; 1124 clock-names = "ipg"; 1125 fsl,channel = <0>; 1126 fsl,num-irqs = <960>; 1127 }; 1128 }; 1129 1130 aips4: bus@49000000 { 1131 compatible = "fsl,aips-bus", "simple-bus"; 1132 reg = <0x0 0x49000000 0x0 0x800000>; 1133 ranges = <0x49000000 0x0 0x49000000 0x800000>; 1134 #address-cells = <1>; 1135 #size-cells = <1>; 1136 1137 wdog3: watchdog@49220000 { 1138 compatible = "fsl,imx94-wdt", "fsl,imx93-wdt"; 1139 reg = <0x49220000 0x10000>; 1140 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1141 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 1142 timeout-sec = <40>; 1143 fsl,ext-reset-output; 1144 status = "disabled"; 1145 }; 1146 }; 1147 }; 1148}; 1149