1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Common dtsi for Variscite DART-MX93 4 * 5 * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-93/dart-mx93/ 6 * 7 * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11/dts-v1/; 12 13#include <dt-bindings/usb/pd.h> 14#include "imx93.dtsi" 15 16/ { 17 model = "Variscite DART-MX93 Module"; 18 compatible = "variscite,var-dart-mx93", "fsl,imx93"; 19 20 sound-wm8904 { 21 compatible = "simple-audio-card"; 22 simple-audio-card,bitclock-master = <&codec_dai>; 23 simple-audio-card,format = "i2s"; 24 simple-audio-card,frame-master = <&codec_dai>; 25 simple-audio-card,mclk-fs = <256>; 26 simple-audio-card,name = "wm8904-audio"; 27 simple-audio-card,routing = 28 "Headphone Jack", "HPOUTL", 29 "Headphone Jack", "HPOUTR", 30 "IN2L", "Line In Jack", 31 "IN2R", "Line In Jack", 32 "IN1L", "Microphone Jack", 33 "IN1R", "Microphone Jack"; 34 simple-audio-card,widgets = 35 "Microphone", "Microphone Jack", 36 "Headphone", "Headphone Jack", 37 "Line", "Line In Jack"; 38 39 codec_dai: simple-audio-card,codec { 40 sound-dai = <&wm8904>; 41 }; 42 43 simple-audio-card,cpu { 44 sound-dai = <&sai1>; 45 }; 46 }; 47 48 wifi_pwrseq: wifi-pwrseq { 49 compatible = "mmc-pwrseq-simple"; 50 post-power-on-delay-ms = <100>; 51 power-off-delay-us = <10000>; 52 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ 53 <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ 54 }; 55}; 56 57&cm33 { 58 mbox-names = "tx", "rx", "rxdb"; 59 mboxes = <&mu1 0 1>, 60 <&mu1 1 1>, 61 <&mu1 3 1>; 62 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 63 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 64 status = "okay"; 65}; 66 67&eqos { 68 pinctrl-names = "default", "sleep"; 69 pinctrl-0 = <&pinctrl_eqos>; 70 pinctrl-1 = <&pinctrl_eqos_sleep>; 71 /* 72 * The required RGMII TX and RX 2ns delays are implemented directly 73 * in hardware via passive delay elements on the SOM PCB. 74 * No delay configuration is needed in software via PHY driver. 75 */ 76 phy-mode = "rgmii"; 77 phy-handle = <ðphy0>; 78 snps,clk-csr = <5>; 79 status = "okay"; 80 81 mdio { 82 compatible = "snps,dwmac-mdio"; 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 ethphy0: ethernet-phy@0 { 87 compatible = "ethernet-phy-ieee802.3-c22"; 88 reg = <0>; 89 reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; 90 reset-assert-us = <10000>; 91 reset-deassert-us = <100000>; 92 }; 93 }; 94}; 95 96&lpi2c3 { 97 clock-frequency = <400000>; 98 pinctrl-names = "default", "sleep", "gpio"; 99 pinctrl-0 = <&pinctrl_lpi2c3>; 100 pinctrl-1 = <&pinctrl_lpi2c3_gpio>; 101 pinctrl-2 = <&pinctrl_lpi2c3_gpio>; 102 scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 103 sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 104 status = "okay"; 105 106 wm8904: audio-codec@1a { 107 compatible = "wlf,wm8904"; 108 reg = <0x1a>; 109 #sound-dai-cells = <0>; 110 clocks = <&clk IMX93_CLK_SAI1_GATE>; 111 clock-names = "mclk"; 112 AVDD-supply = <&buck5>; 113 CPVDD-supply = <&buck5>; 114 DBVDD-supply = <&buck4>; 115 DCVDD-supply = <&buck5>; 116 MICVDD-supply = <&buck5>; 117 wlf,drc-cfg-names = "default", "peaklimiter", "tradition", 118 "soft", "music"; 119 /* 120 * Config registers per name, respectively: 121 * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 122 * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 123 * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 124 * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 125 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 126 */ 127 wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, 128 /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, 129 /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, 130 /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, 131 /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; 132 /* GPIO1 = DMIC_CLK, don't touch others */ 133 wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; 134 /* DMIC is connected to IN1L */ 135 wlf,in1l-as-dmicdat1; 136 }; 137 138 pmic@25 { 139 compatible = "nxp,pca9451a"; 140 reg = <0x25>; 141 142 regulators { 143 buck1: BUCK1 { 144 regulator-name = "BUCK1"; 145 regulator-min-microvolt = <650000>; 146 regulator-max-microvolt = <2237500>; 147 regulator-boot-on; 148 regulator-always-on; 149 regulator-ramp-delay = <3125>; 150 }; 151 152 buck2: BUCK2 { 153 regulator-name = "BUCK2"; 154 regulator-min-microvolt = <600000>; 155 regulator-max-microvolt = <2187500>; 156 regulator-boot-on; 157 regulator-always-on; 158 regulator-ramp-delay = <3125>; 159 }; 160 161 buck4: BUCK4 { 162 regulator-name = "BUCK4"; 163 regulator-min-microvolt = <600000>; 164 regulator-max-microvolt = <3400000>; 165 regulator-boot-on; 166 regulator-always-on; 167 }; 168 169 buck5: BUCK5 { 170 regulator-name = "BUCK5"; 171 regulator-min-microvolt = <600000>; 172 regulator-max-microvolt = <3400000>; 173 regulator-boot-on; 174 regulator-always-on; 175 }; 176 177 buck6: BUCK6 { 178 regulator-name = "BUCK6"; 179 regulator-min-microvolt = <600000>; 180 regulator-max-microvolt = <3400000>; 181 regulator-boot-on; 182 regulator-always-on; 183 }; 184 185 ldo1: LDO1 { 186 regulator-name = "LDO1"; 187 regulator-min-microvolt = <1600000>; 188 regulator-max-microvolt = <3300000>; 189 regulator-boot-on; 190 regulator-always-on; 191 }; 192 193 ldo4: LDO4 { 194 regulator-name = "LDO4"; 195 regulator-min-microvolt = <800000>; 196 regulator-max-microvolt = <3300000>; 197 regulator-boot-on; 198 regulator-always-on; 199 }; 200 201 ldo5: LDO5 { 202 regulator-name = "LDO5"; 203 regulator-min-microvolt = <1800000>; 204 regulator-max-microvolt = <3300000>; 205 regulator-boot-on; 206 regulator-always-on; 207 }; 208 }; 209 }; 210}; 211 212/* BT module */ 213&lpuart5 { 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>; 216 uart-has-rtscts; 217 status = "okay"; 218 219 bluetooth { 220 compatible = "nxp,88w8987-bt"; 221 }; 222}; 223 224&mu1 { 225 status = "okay"; 226}; 227 228&mu2 { 229 status = "okay"; 230}; 231 232&sai1 { 233 pinctrl-names = "default", "sleep"; 234 pinctrl-0 = <&pinctrl_sai1>; 235 pinctrl-1 = <&pinctrl_sai1_sleep>; 236 assigned-clocks = <&clk IMX93_CLK_SAI1>; 237 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 238 assigned-clock-rates = <12288000>; 239 #sound-dai-cells = <0>; 240 fsl,sai-mclk-direction-output; 241 status = "okay"; 242}; 243 244/* eMMC */ 245&usdhc1 { 246 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 247 pinctrl-0 = <&pinctrl_usdhc1>; 248 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 249 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 250 bus-width = <8>; 251 non-removable; 252 status = "okay"; 253}; 254 255/* WiFi */ 256&usdhc3 { 257 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 258 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; 259 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; 260 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; 261 pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; 262 mmc-pwrseq = <&wifi_pwrseq>; 263 keep-power-in-suspend; 264 bus-width = <4>; 265 non-removable; 266 wakeup-source; 267 status = "okay"; 268}; 269 270&iomuxc { 271 pinctrl_bt: btgrp { 272 fsl,pins = < 273 MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e 274 >; 275 }; 276 277 pinctrl_eqos: eqosgrp { 278 fsl,pins = < 279 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 280 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 281 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 282 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 283 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 284 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 285 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e 286 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 287 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 288 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 289 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 290 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 291 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 292 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 293 MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e 294 >; 295 }; 296 297 pinctrl_eqos_sleep: eqos-sleepgrp { 298 fsl,pins = < 299 MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e 300 MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e 301 MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e 302 MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e 303 MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e 304 MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e 305 MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e 306 MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e 307 MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e 308 MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e 309 MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e 310 MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e 311 MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e 312 MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e 313 >; 314 }; 315 316 pinctrl_lpi2c3: lpi2c3grp { 317 fsl,pins = < 318 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 319 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 320 >; 321 }; 322 323 pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { 324 fsl,pins = < 325 MX93_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e 326 MX93_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e 327 >; 328 }; 329 330 pinctrl_sai1: sai1grp { 331 fsl,pins = < 332 MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e 333 MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e 334 MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e 335 MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e 336 MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e 337 MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e 338 MX93_PAD_UART2_RXD__SAI1_MCLK 0x31e 339 >; 340 }; 341 342 pinctrl_sai1_sleep: sai1-sleepgrp { 343 fsl,pins = < 344 MX93_PAD_SAI1_TXC__GPIO1_IO12 0x31e 345 MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x31e 346 MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x31e 347 MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x31e 348 MX93_PAD_UART2_RXD__GPIO1_IO06 0x31e 349 MX93_PAD_I2C2_SDA__GPIO1_IO03 0x31e 350 MX93_PAD_I2C2_SCL__GPIO1_IO02 0x31e 351 >; 352 }; 353 354 pinctrl_uart5: uart5grp { 355 fsl,pins = < 356 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 357 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 358 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 359 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 360 >; 361 }; 362 363 pinctrl_usdhc1: usdhc1grp { 364 fsl,pins = < 365 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 366 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 367 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 368 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 369 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 370 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 371 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 372 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 373 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 374 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 375 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 376 >; 377 }; 378 379 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 380 fsl,pins = < 381 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 382 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 383 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 384 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 385 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 386 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 387 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 388 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 389 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 390 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 391 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 392 >; 393 }; 394 395 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 396 fsl,pins = < 397 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 398 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 399 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 400 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 401 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 402 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 403 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 404 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 405 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 406 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 407 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 408 >; 409 }; 410 411 pinctrl_usdhc3: usdhc3grp { 412 fsl,pins = < 413 MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 414 MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 415 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 416 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 417 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 418 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 419 >; 420 }; 421 422 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 423 fsl,pins = < 424 MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e 425 MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e 426 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e 427 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e 428 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e 429 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e 430 >; 431 }; 432 433 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 434 fsl,pins = < 435 MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe 436 MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe 437 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe 438 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe 439 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe 440 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe 441 >; 442 }; 443 444 pinctrl_usdhc3_sleep: usdhc3-sleepgrp { 445 fsl,pins = < 446 MX93_PAD_SD3_CLK__GPIO3_IO20 0x400 447 MX93_PAD_SD3_CMD__GPIO3_IO21 0x400 448 MX93_PAD_SD3_DATA0__GPIO3_IO22 0x400 449 MX93_PAD_SD3_DATA1__GPIO3_IO23 0x400 450 MX93_PAD_SD3_DATA2__GPIO3_IO24 0x400 451 MX93_PAD_SD3_DATA3__GPIO3_IO25 0x400 452 >; 453 }; 454 455 pinctrl_usdhc3_wlan: usdhc3wlangrp { 456 fsl,pins = < 457 MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e 458 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x51e 459 >; 460 }; 461}; 462