1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Variscite Sonata carrier board for DART-MX93 4 * 5 * Link: https://variscite.com/carrier-boards/sonata-board/ 6 * 7 * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11/dts-v1/; 12 13#include <dt-bindings/leds/common.h> 14#include "imx93-var-dart.dtsi" 15 16/ { 17 model = "Variscite DART-MX93 on Sonata-Board"; 18 compatible = "variscite,var-dart-mx93-sonata", 19 "variscite,var-dart-mx93", 20 "fsl,imx93"; 21 22 aliases { 23 ethernet0 = &eqos; 24 ethernet1 = &fec; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 i2c0 = &lpi2c1; 29 i2c1 = &lpi2c2; 30 i2c2 = &lpi2c3; 31 i2c3 = &lpi2c4; 32 i2c4 = &lpi2c5; 33 mmc0 = &usdhc1; 34 mmc1 = &usdhc2; 35 serial0 = &lpuart1; 36 serial1 = &lpuart2; 37 serial2 = &lpuart3; 38 serial3 = &lpuart4; 39 serial4 = &lpuart5; 40 serial5 = &lpuart6; 41 serial6 = &lpuart7; 42 }; 43 44 chosen { 45 stdout-path = &lpuart1; 46 }; 47 48 gpio-keys { 49 compatible = "gpio-keys"; 50 51 button-home { 52 label = "Home"; 53 linux,code = <KEY_HOME>; 54 gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; 55 wakeup-source; 56 }; 57 58 button-up { 59 label = "Up"; 60 linux,code = <KEY_UP>; 61 gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; 62 wakeup-source; 63 }; 64 65 button-down { 66 label = "Down"; 67 linux,code = <KEY_DOWN>; 68 gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; 69 wakeup-source; 70 }; 71 72 button-back { 73 label = "Back"; 74 linux,code = <KEY_BACK>; 75 gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; 76 wakeup-source; 77 }; 78 }; 79 80 gpio-leds { 81 compatible = "gpio-leds"; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_leds_gpio>; 84 85 led-emmc { 86 gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; 87 label = "eMMC"; 88 linux,default-trigger = "mmc0"; 89 }; 90 }; 91 92 clk40m: oscillator { 93 compatible = "fixed-clock"; 94 #clock-cells = <0>; 95 clock-frequency = <40000000>; 96 clock-output-names = "can_osc"; 97 }; 98 99 reg_vref_1v8: regulator-adc-vref { 100 compatible = "regulator-fixed"; 101 regulator-name = "vref_1v8"; 102 regulator-max-microvolt = <1800000>; 103 regulator-min-microvolt = <1800000>; 104 }; 105 106 reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { 107 compatible = "regulator-fixed"; 108 regulator-name = "VDD_SD2_3V3"; 109 off-on-delay-us = <20000>; 110 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 111 pinctrl-names = "default"; 112 regulator-max-microvolt = <3300000>; 113 regulator-min-microvolt = <3300000>; 114 gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; 115 enable-active-high; 116 }; 117 118 reserved-memory { 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges; 122 123 ethosu_mem: ethosu-region@88000000 { 124 compatible = "shared-dma-pool"; 125 reusable; 126 reg = <0x0 0x88000000 0x0 0x8000000>; 127 }; 128 129 vdev0vring0: vdev0vring0@87ee0000 { 130 reg = <0 0x87ee0000 0 0x8000>; 131 no-map; 132 }; 133 134 vdev0vring1: vdev0vring1@87ee8000 { 135 reg = <0 0x87ee8000 0 0x8000>; 136 no-map; 137 }; 138 139 vdev1vring0: vdev1vring0@87ef0000 { 140 reg = <0 0x87ef0000 0 0x8000>; 141 no-map; 142 }; 143 144 vdev1vring1: vdev1vring1@87ef8000 { 145 reg = <0 0x87ef8000 0 0x8000>; 146 no-map; 147 }; 148 149 rsc_table: rsc-table@2021e000 { 150 reg = <0 0x2021e000 0 0x1000>; 151 no-map; 152 }; 153 154 vdevbuffer: vdevbuffer@87f00000 { 155 compatible = "shared-dma-pool"; 156 reg = <0 0x87f00000 0 0x100000>; 157 no-map; 158 }; 159 160 ele_reserved: ele-reserved@87de0000 { 161 compatible = "shared-dma-pool"; 162 reg = <0 0x87de0000 0 0x100000>; 163 no-map; 164 }; 165 }; 166}; 167 168&adc1 { 169 vref-supply = <®_vref_1v8>; 170 status = "okay"; 171}; 172 173/* Use external instead of internal RTC */ 174&bbnsm_rtc { 175 status = "disabled"; 176}; 177 178&eqos { 179 mdio { 180 ethphy1: ethernet-phy@1 { 181 compatible = "ethernet-phy-ieee802.3-c22"; 182 reg = <1>; 183 reset-assert-us = <15000>; 184 reset-deassert-us = <100000>; 185 reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; 186 187 leds { 188 #address-cells = <1>; 189 #size-cells = <0>; 190 191 led@0 { 192 reg = <0>; 193 color = <LED_COLOR_ID_YELLOW>; 194 function = LED_FUNCTION_LAN; 195 linux,default-trigger = "netdev"; 196 }; 197 198 led@1 { 199 reg = <1>; 200 color = <LED_COLOR_ID_GREEN>; 201 function = LED_FUNCTION_LAN; 202 linux,default-trigger = "netdev"; 203 }; 204 }; 205 }; 206 }; 207}; 208 209ðphy0 { 210 leds { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 214 led@0 { 215 reg = <0>; 216 color = <LED_COLOR_ID_YELLOW>; 217 function = LED_FUNCTION_LAN; 218 linux,default-trigger = "netdev"; 219 }; 220 221 led@1 { 222 reg = <1>; 223 color = <LED_COLOR_ID_GREEN>; 224 function = LED_FUNCTION_LAN; 225 linux,default-trigger = "netdev"; 226 }; 227 }; 228}; 229 230&fec { 231 pinctrl-names = "default", "sleep"; 232 pinctrl-0 = <&pinctrl_fec>; 233 pinctrl-1 = <&pinctrl_fec_sleep>; 234 /* 235 * The required RGMII TX and RX 2ns delays are implemented directly 236 * in hardware via passive delay elements on the SOM PCB. 237 * No delay configuration is needed in software via PHY driver. 238 */ 239 phy-mode = "rgmii"; 240 phy-handle = <ðphy1>; 241 status = "okay"; 242}; 243 244&flexcan1 { 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_flexcan1>; 247 status = "okay"; 248}; 249 250&lpi2c1 { 251 clock-frequency = <400000>; 252 pinctrl-0 = <&pinctrl_lpi2c1>; 253 pinctrl-1 = <&pinctrl_lpi2c1_gpio>; 254 pinctrl-2 = <&pinctrl_lpi2c1_gpio>; 255 pinctrl-names = "default", "sleep", "gpio"; 256 scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 257 sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 258 status = "okay"; 259 260 pca9534: gpio@22 { 261 compatible = "nxp,pca9534"; 262 reg = <0x22>; 263 gpio-controller; 264 #gpio-cells = <2>; 265 interrupt-parent = <&gpio1>; 266 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 267 }; 268 269 /* Capacitive touch controller */ 270 ft5x06_ts: touchscreen@38 { 271 compatible = "edt,edt-ft5206"; 272 reg = <0x38>; 273 interrupt-parent = <&gpio3>; 274 interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 275 pinctrl-0 = <&pinctrl_captouch>; 276 pinctrl-names = "default"; 277 reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; 278 touchscreen-inverted-x; 279 touchscreen-inverted-y; 280 touchscreen-size-x = <800>; 281 touchscreen-size-y = <480>; 282 wakeup-source; 283 }; 284 285 /* USB Type-C Controller */ 286 typec@3d { 287 compatible = "nxp,ptn5150"; 288 reg = <0x3d>; 289 interrupt-parent = <&gpio4>; 290 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; 291 pinctrl-0 = <&pinctrl_extcon>; 292 pinctrl-names = "default"; 293 294 port { 295 typec1_dr_sw: endpoint { 296 remote-endpoint = <&usb1_drd_sw>; 297 }; 298 }; 299 }; 300 301 rtc@68 { 302 compatible = "dallas,ds1337"; 303 reg = <0x68>; 304 interrupt-parent = <&gpio2>; 305 interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&pinctrl_rtc>; 308 wakeup-source; 309 }; 310}; 311 312&lpi2c5 { 313 clock-frequency = <400000>; 314 pinctrl-names = "default", "sleep", "gpio"; 315 pinctrl-0 = <&pinctrl_lpi2c5>; 316 pinctrl-1 = <&pinctrl_lpi2c5_gpio>; 317 pinctrl-2 = <&pinctrl_lpi2c5_gpio>; 318 scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 319 sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 320 status = "okay"; 321}; 322 323&lpi2c7 { 324 clock-frequency = <400000>; 325 pinctrl-names = "default", "sleep", "gpio"; 326 pinctrl-0 = <&pinctrl_lpi2c7>; 327 pinctrl-1 = <&pinctrl_lpi2c7_gpio>; 328 pinctrl-2 = <&pinctrl_lpi2c7_gpio>; 329 scl-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 330 sda-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 331 status = "okay"; 332 333 pca6408_1: gpio@20 { 334 compatible = "nxp,pcal6408"; 335 reg = <0x20>; 336 gpio-controller; 337 #gpio-cells = <2>; 338 interrupt-parent = <&gpio1>; 339 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 340 }; 341 342 pca6408_2: gpio@21 { 343 compatible = "nxp,pcal6408"; 344 reg = <0x21>; 345 gpio-controller; 346 #gpio-cells = <2>; 347 interrupt-parent = <&gpio1>; 348 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 349 }; 350 351 st33ktpm2xi2c: tpm@2e { 352 compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; 353 reg = <0x2e>; 354 }; 355}; 356 357&lpspi8 { 358 pinctrl-names = "default"; 359 pinctrl-0 = <&pinctrl_lpspi8>; 360 cs-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 361 status = "okay"; 362 363 /* CAN controller */ 364 can0: can@0 { 365 compatible = "microchip,mcp251xfd"; 366 reg = <0>; 367 clocks = <&clk40m>; 368 interrupt-parent = <&gpio2>; 369 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 370 pinctrl-names = "default"; 371 pinctrl-0 = <&pinctrl_can>; 372 spi-max-frequency = <1000000>; 373 }; 374}; 375 376/* Console (J10) */ 377&lpuart1 { 378 pinctrl-names = "default"; 379 pinctrl-0 = <&pinctrl_uart1>; 380 status = "okay"; 381}; 382 383/* Header (J12.4, J12.6) */ 384&lpuart6 { 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_uart6>; 387 status = "okay"; 388}; 389 390/* Header (J12.11, J12.13) */ 391&lpuart7 { 392 pinctrl-names = "default"; 393 pinctrl-0 = <&pinctrl_uart7>; 394 status = "okay"; 395}; 396 397&tpm3 { 398 pinctrl-0 = <&pinctrl_tpm3>; 399 pinctrl-names = "default"; 400 status = "okay"; 401}; 402 403&usbotg1 { 404 dr_mode = "otg"; 405 hnp-disable; 406 srp-disable; 407 adp-disable; 408 usb-role-switch; 409 disable-over-current; 410 samsung,picophy-pre-emp-curr-control = <3>; 411 samsung,picophy-dc-vol-level-adjust = <7>; 412 status = "okay"; 413 414 port { 415 usb1_drd_sw: endpoint { 416 remote-endpoint = <&typec1_dr_sw>; 417 }; 418 }; 419}; 420 421&usbotg2 { 422 disable-over-current; 423 dr_mode = "host"; 424 status = "okay"; 425}; 426 427/* SD */ 428&usdhc2 { 429 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 430 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 431 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 432 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 433 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 434 vmmc-supply = <®_usdhc2_vmmc>; 435 bus-width = <4>; 436 no-sdio; 437 no-mmc; 438 status = "okay"; 439}; 440 441&wdog3 { 442 status = "okay"; 443}; 444 445&iomuxc { 446 pinctrl-names = "default"; 447 pinctrl-0 = <&pinctrl_hog>; 448 449 pinctrl_can: cangrp { 450 fsl,pins = < 451 MX93_PAD_GPIO_IO03__GPIO2_IO03 0x31e 452 >; 453 }; 454 455 pinctrl_captouch: captouchgrp { 456 fsl,pins = < 457 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e 458 >; 459 }; 460 461 pinctrl_extcon: extcongrp { 462 fsl,pins = < 463 MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x31e 464 >; 465 }; 466 467 pinctrl_fec: fecgrp { 468 fsl,pins = < 469 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 470 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 471 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 472 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x37e 473 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e 474 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 475 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 476 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 477 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 478 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 479 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e 480 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 481 >; 482 }; 483 484 pinctrl_fec_sleep: fecsleepgrp { 485 fsl,pins = < 486 MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e 487 MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e 488 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e 489 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e 490 MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e 491 MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e 492 MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e 493 MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e 494 MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e 495 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e 496 MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e 497 MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e 498 >; 499 }; 500 501 pinctrl_flexcan1: flexcan1grp { 502 fsl,pins = < 503 MX93_PAD_PDM_CLK__CAN1_TX 0x139e 504 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 505 >; 506 }; 507 508 pinctrl_hog: hoggrp { 509 fsl,pins = < 510 /* GPIO Expanders shared IRQ */ 511 MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e 512 >; 513 }; 514 515 pinctrl_leds_gpio: ledgrp { 516 fsl,pins = < 517 MX93_PAD_GPIO_IO11__GPIO2_IO11 0x31e 518 >; 519 }; 520 521 pinctrl_lpi2c1: lpi2c1grp { 522 fsl,pins = < 523 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 524 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 525 >; 526 }; 527 528 pinctrl_lpi2c1_gpio: lpi2c1-gpiogrp { 529 fsl,pins = < 530 MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e 531 MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e 532 >; 533 }; 534 535 pinctrl_lpi2c5: lpi2c5grp { 536 fsl,pins = < 537 MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e 538 MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e 539 >; 540 }; 541 542 pinctrl_lpi2c5_gpio: lpi2c5-gpiogrp { 543 fsl,pins = < 544 MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e 545 MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e 546 >; 547 }; 548 549 pinctrl_lpi2c7: lpi2c7grp { 550 fsl,pins = < 551 MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x40000b9e 552 MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x40000b9e 553 >; 554 }; 555 556 pinctrl_lpi2c7_gpio: lpi2c7-gpiogrp { 557 fsl,pins = < 558 MX93_PAD_GPIO_IO07__GPIO2_IO07 0x31e 559 MX93_PAD_GPIO_IO06__GPIO2_IO06 0x31e 560 >; 561 }; 562 563 pinctrl_lpspi8: lpspi8grp { 564 fsl,pins = < 565 MX93_PAD_GPIO_IO00__GPIO2_IO00 0x31e 566 MX93_PAD_GPIO_IO01__GPIO2_IO01 0x31e 567 MX93_PAD_GPIO_IO12__GPIO2_IO12 0x31e 568 MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x31e 569 MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x31e 570 MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x31e 571 >; 572 }; 573 574 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 575 fsl,pins = < 576 MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x31e 577 >; 578 }; 579 580 pinctrl_rtc: rtcgrp { 581 fsl,pins = < 582 MX93_PAD_GPIO_IO02__GPIO2_IO02 0x31e 583 >; 584 }; 585 586 pinctrl_tpm3: tpm3grp { 587 fsl,pins = < 588 MX93_PAD_GPIO_IO24__TPM3_CH3 0x51e 589 >; 590 }; 591 592 pinctrl_uart1: uart1grp { 593 fsl,pins = < 594 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 595 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 596 >; 597 }; 598 599 pinctrl_uart6: uart6grp { 600 fsl,pins = < 601 MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e 602 MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e 603 >; 604 }; 605 606 pinctrl_uart7: uart7grp { 607 fsl,pins = < 608 MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e 609 MX93_PAD_GPIO_IO08__LPUART7_TX 0x31e 610 >; 611 }; 612 613 pinctrl_usdhc2: usdhc2grp { 614 fsl,pins = < 615 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 616 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 617 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 618 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 619 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 620 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 621 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 622 >; 623 }; 624 625 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 626 fsl,pins = < 627 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 628 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 629 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 630 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 631 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 632 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 633 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 634 >; 635 }; 636 637 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 638 fsl,pins = < 639 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 640 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 641 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 642 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 643 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 644 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 645 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 646 >; 647 }; 648 649 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 650 fsl,pins = < 651 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 652 >; 653 }; 654}; 655