1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2025 PHYTEC Messtechnik GmbH 4 * Author: Andrej Picej <andrej.picej@norik.com> 5 */ 6 7/dts-v1/; 8/plugin/; 9 10#include <dt-bindings/gpio/gpio.h> 11#include "imx93-pinfunc.h" 12 13&{/} { 14 usdhc3_pwrseq: usdhc3-pwrseq { 15 compatible = "mmc-pwrseq-simple"; 16 post-power-on-delay-ms = <100>; 17 power-off-delay-us = <60>; 18 reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; 19 }; 20}; 21 22&lpuart5 { 23 pinctrl-names = "default"; 24 pinctrl-0 = <&pinctrl_uart5>; 25 status = "okay"; 26 27 bluetooth { 28 compatible = "brcm,bcm43438-bt"; 29 shutdown-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; 30 host-wakeup-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; 31 max-speed = <2000000>; 32 }; 33}; 34 35&usdhc3 { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 pinctrl-names = "default", "sleep"; 39 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wlbt>; 40 pinctrl-1 = <&pinctrl_usdhc3_sleep>, <&pinctrl_wlbt>; 41 mmc-pwrseq = <&usdhc3_pwrseq>; 42 bus-width = <4>; 43 non-removable; 44 no-1-8-v; 45 status = "okay"; 46 47 brmcf: wifi@1 { 48 compatible = "brcm,bcm4329-fmac"; 49 reg = <1>; 50 }; 51}; 52 53&iomuxc { 54 pinctrl_uart5: uart5grp { 55 fsl,pins = < 56 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 57 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 58 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 59 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 60 >; 61 }; 62 63 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 64 pinctrl_usdhc3: usdhc3grp { 65 fsl,pins = < 66 MX93_PAD_GPIO_IO22__USDHC3_CLK 0x179e 67 MX93_PAD_GPIO_IO23__USDHC3_CMD 0x4000139e 68 MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x4000139e 69 MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x4000139e 70 MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x4000139e 71 MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x4000139e 72 >; 73 }; 74 75 pinctrl_usdhc3_sleep: usdhc3sleepgrp { 76 fsl,pins = < 77 MX93_PAD_GPIO_IO22__USDHC3_CLK 0x31e 78 MX93_PAD_GPIO_IO23__USDHC3_CMD 0x31e 79 MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x31e 80 MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x31e 81 MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x31e 82 MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x31e 83 >; 84 }; 85 86 pinctrl_wlbt: wlbtgrp { 87 fsl,pins = < 88 MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e /* BT ENABLE */ 89 MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e /* WLAN ENABLE */ 90 MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e /* HOST WAKEUP */ 91 >; 92 }; 93}; 94