1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2025 PHYTEC Messtechnik GmbH 4 * Author: Primoz Fiser <primoz.fiser@norik.com> 5 */ 6 7/dts-v1/; 8/plugin/; 9 10#include <dt-bindings/gpio/gpio.h> 11#include "imx93-pinfunc.h" 12 13&{/} { 14 usdhc3_pwrseq: usdhc3-pwrseq { 15 compatible = "mmc-pwrseq-simple"; 16 reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; 17 }; 18}; 19 20&lpuart5 { 21 pinctrl-names = "default"; 22 pinctrl-0 = <&pinctrl_uart5>; 23 status = "okay"; 24 25 bluetooth { 26 compatible = "nxp,88w8987-bt"; 27 }; 28}; 29 30/* 31 * NOTE: When uSDHC3 port is multiplexed on GPIO_IO[27:22] pads, it only 32 * supports 50 MHz mode, due to introduction of potential variations in 33 * trace impedance, drive strength, and timing skew. Refer to i.MX 93 34 * Application Processors Data Sheet, Rev. 3, page 60 for more details. 35 */ 36&usdhc3 { 37 pinctrl-names = "default", "sleep"; 38 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wlbt>; 39 pinctrl-1 = <&pinctrl_usdhc3_sleep>, <&pinctrl_wlbt>; 40 mmc-pwrseq = <&usdhc3_pwrseq>; 41 bus-width = <4>; 42 keep-power-in-suspend; 43 non-removable; 44 wakeup-source; 45 status = "okay"; 46}; 47 48&iomuxc { 49 pinctrl_uart5: uart5grp { 50 fsl,pins = < 51 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 52 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 53 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 54 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 55 >; 56 }; 57 58 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 59 pinctrl_usdhc3: usdhc3grp { 60 fsl,pins = < 61 MX93_PAD_GPIO_IO22__USDHC3_CLK 0x179e 62 MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000178e 63 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e 64 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e 65 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e 66 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e 67 >; 68 }; 69 70 pinctrl_usdhc3_sleep: usdhc3sleepgrp { 71 fsl,pins = < 72 MX93_PAD_GPIO_IO22__USDHC3_CLK 0x31e 73 MX93_PAD_SD3_CMD__USDHC3_CMD 0x31e 74 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x31e 75 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x31e 76 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x31e 77 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x31e 78 >; 79 }; 80 81 pinctrl_wlbt: wlbtgrp { 82 fsl,pins = < 83 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e /* WAKE_DEV */ 84 MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x31e /* WAKE_HOST */ 85 MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x31e /* PDn */ 86 >; 87 }; 88}; 89