1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022,2026 NXP 4 */ 5 6#include <dt-bindings/usb/pd.h> 7 8/ { 9 aliases { 10 ethernet0 = &fec; 11 ethernet1 = &eqos; 12 gpio0 = &gpio1; 13 gpio1 = &gpio2; 14 gpio2 = &gpio3; 15 i2c0 = &lpi2c1; 16 i2c1 = &lpi2c2; 17 i2c2 = &lpi2c3; 18 mmc0 = &usdhc1; 19 mmc1 = &usdhc2; 20 rtc0 = &bbnsm_rtc; 21 serial0 = &lpuart1; 22 serial1 = &lpuart2; 23 serial2 = &lpuart3; 24 serial3 = &lpuart4; 25 serial4 = &lpuart5; 26 }; 27 28 chosen { 29 stdout-path = &lpuart1; 30 }; 31 32 reserved-memory { 33 #address-cells = <2>; 34 #size-cells = <2>; 35 ranges; 36 37 linux,cma { 38 compatible = "shared-dma-pool"; 39 reusable; 40 alloc-ranges = <0 0x80000000 0 0x40000000>; 41 size = <0 0x10000000>; 42 linux,cma-default; 43 }; 44 45 vdev0vring0: vdev0vring0@a4000000 { 46 reg = <0 0xa4000000 0 0x8000>; 47 no-map; 48 }; 49 50 vdev0vring1: vdev0vring1@a4008000 { 51 reg = <0 0xa4008000 0 0x8000>; 52 no-map; 53 }; 54 55 vdev1vring0: vdev1vring0@a4010000 { 56 reg = <0 0xa4010000 0 0x8000>; 57 no-map; 58 }; 59 60 vdev1vring1: vdev1vring1@a4018000 { 61 reg = <0 0xa4018000 0 0x8000>; 62 no-map; 63 }; 64 65 rsc_table: rsc-table@2021e000 { 66 reg = <0 0x2021e000 0 0x1000>; 67 no-map; 68 }; 69 70 vdevbuffer: vdevbuffer@a4020000 { 71 compatible = "shared-dma-pool"; 72 reg = <0 0xa4020000 0 0x100000>; 73 no-map; 74 }; 75 76 }; 77 78 flexcan_phy: can-phy { 79 compatible = "nxp,tja1057"; 80 #phy-cells = <0>; 81 max-bitrate = <5000000>; 82 silent-gpios = <&adp5585 6 GPIO_ACTIVE_HIGH>; 83 }; 84 85 reg_vdd_12v: regulator-vdd-12v { 86 compatible = "regulator-fixed"; 87 regulator-name = "VDD_12V"; 88 regulator-min-microvolt = <12000000>; 89 regulator-max-microvolt = <12000000>; 90 gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; 91 enable-active-high; 92 }; 93 94 reg_vref_1v8: regulator-adc-vref { 95 compatible = "regulator-fixed"; 96 regulator-name = "vref_1v8"; 97 regulator-min-microvolt = <1800000>; 98 regulator-max-microvolt = <1800000>; 99 }; 100 101 reg_audio_pwr: regulator-audio-pwr { 102 compatible = "regulator-fixed"; 103 regulator-name = "audio-pwr"; 104 regulator-min-microvolt = <3300000>; 105 regulator-max-microvolt = <3300000>; 106 gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; 107 enable-active-high; 108 }; 109 110 reg_usdhc2_vmmc: regulator-usdhc2 { 111 compatible = "regulator-fixed"; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 114 regulator-name = "VSD_3V3"; 115 regulator-min-microvolt = <3300000>; 116 regulator-max-microvolt = <3300000>; 117 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 118 off-on-delay-us = <12000>; 119 enable-active-high; 120 }; 121 122 backlight_lvds: backlight-lvds { 123 compatible = "pwm-backlight"; 124 pwms = <&adp5585 0 100000 0>; 125 brightness-levels = <0 100>; 126 num-interpolated-steps = <100>; 127 default-brightness-level = <100>; 128 power-supply = <®_vdd_12v>; 129 enable-gpios = <&adp5585 9 GPIO_ACTIVE_HIGH>; 130 status = "disabled"; 131 }; 132 133 sound-wm8962 { 134 compatible = "fsl,imx-audio-wm8962"; 135 model = "wm8962-audio"; 136 audio-cpu = <&sai3>; 137 audio-codec = <&wm8962>; 138 hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; 139 audio-routing = 140 "Headphone Jack", "HPOUTL", 141 "Headphone Jack", "HPOUTR", 142 "Ext Spk", "SPKOUTL", 143 "Ext Spk", "SPKOUTR", 144 "AMIC", "MICBIAS", 145 "IN3R", "AMIC", 146 "IN1R", "AMIC"; 147 }; 148 149 sound-xcvr { 150 compatible = "fsl,imx-audio-card"; 151 model = "imx-audio-xcvr"; 152 153 pri-dai-link { 154 link-name = "XCVR PCM"; 155 156 cpu { 157 sound-dai = <&xcvr>; 158 }; 159 }; 160 }; 161}; 162 163&adc1 { 164 vref-supply = <®_vref_1v8>; 165 status = "okay"; 166}; 167 168&cm33 { 169 mbox-names = "tx", "rx", "rxdb"; 170 mboxes = <&mu1 0 1>, 171 <&mu1 1 1>, 172 <&mu1 3 1>; 173 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 174 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 175 status = "okay"; 176}; 177 178&eqos { 179 pinctrl-names = "default", "sleep"; 180 pinctrl-0 = <&pinctrl_eqos>; 181 pinctrl-1 = <&pinctrl_eqos_sleep>; 182 phy-mode = "rgmii-id"; 183 phy-handle = <ðphy1>; 184 status = "okay"; 185 186 mdio { 187 compatible = "snps,dwmac-mdio"; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 clock-frequency = <5000000>; 191 192 ethphy1: ethernet-phy@1 { 193 reg = <1>; 194 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; 195 reset-assert-us = <10000>; 196 reset-deassert-us = <80000>; 197 realtek,clkout-disable; 198 }; 199 }; 200}; 201 202&fec { 203 pinctrl-names = "default", "sleep"; 204 pinctrl-0 = <&pinctrl_fec>; 205 pinctrl-1 = <&pinctrl_fec_sleep>; 206 phy-mode = "rgmii-id"; 207 phy-handle = <ðphy2>; 208 fsl,magic-packet; 209 status = "okay"; 210 211 mdio { 212 #address-cells = <1>; 213 #size-cells = <0>; 214 clock-frequency = <5000000>; 215 216 ethphy2: ethernet-phy@2 { 217 reg = <2>; 218 reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; 219 reset-assert-us = <10000>; 220 reset-deassert-us = <80000>; 221 realtek,clkout-disable; 222 }; 223 }; 224}; 225 226&flexcan2 { 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_flexcan2>; 229 phys = <&flexcan_phy>; 230 status = "okay"; 231}; 232 233&lpi2c1 { 234 clock-frequency = <400000>; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_lpi2c1>; 237 status = "okay"; 238 239 wm8962: codec@1a { 240 compatible = "wlf,wm8962"; 241 reg = <0x1a>; 242 clocks = <&clk IMX93_CLK_SAI3_GATE>; 243 DCVDD-supply = <®_audio_pwr>; 244 DBVDD-supply = <®_audio_pwr>; 245 AVDD-supply = <®_audio_pwr>; 246 CPVDD-supply = <®_audio_pwr>; 247 MICVDD-supply = <®_audio_pwr>; 248 PLLVDD-supply = <®_audio_pwr>; 249 SPKVDD1-supply = <®_audio_pwr>; 250 SPKVDD2-supply = <®_audio_pwr>; 251 gpio-cfg = < 252 0x0000 /* 0:Default */ 253 0x0000 /* 1:Default */ 254 0x0000 /* 2:FN_DMICCLK */ 255 0x0000 /* 3:Default */ 256 0x0000 /* 4:FN_DMICCDAT */ 257 0x0000 /* 5:Default */ 258 >; 259 }; 260 261 inertial-meter@6a { 262 compatible = "st,lsm6dso"; 263 reg = <0x6a>; 264 }; 265}; 266 267&lpi2c2 { 268 clock-frequency = <400000>; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&pinctrl_lpi2c2>; 271 status = "okay"; 272 273 pcal6524: gpio@22 { 274 compatible = "nxp,pcal6524"; 275 reg = <0x22>; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_pcal6524>; 278 gpio-controller; 279 #gpio-cells = <2>; 280 interrupt-controller; 281 #interrupt-cells = <2>; 282 interrupt-parent = <&gpio3>; 283 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 284 }; 285 286 pmic@25 { 287 compatible = "nxp,pca9451a"; 288 reg = <0x25>; 289 interrupt-parent = <&pcal6524>; 290 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 291 292 regulators { 293 buck1: BUCK1 { 294 regulator-name = "BUCK1"; 295 regulator-min-microvolt = <610000>; 296 regulator-max-microvolt = <950000>; 297 regulator-boot-on; 298 regulator-always-on; 299 regulator-ramp-delay = <3125>; 300 }; 301 302 buck2: BUCK2 { 303 regulator-name = "BUCK2"; 304 regulator-min-microvolt = <600000>; 305 regulator-max-microvolt = <670000>; 306 regulator-boot-on; 307 regulator-always-on; 308 regulator-ramp-delay = <3125>; 309 }; 310 311 buck4: BUCK4 { 312 regulator-name = "BUCK4"; 313 regulator-min-microvolt = <1620000>; 314 regulator-max-microvolt = <3400000>; 315 regulator-boot-on; 316 regulator-always-on; 317 }; 318 319 buck5: BUCK5 { 320 regulator-name = "BUCK5"; 321 regulator-min-microvolt = <1620000>; 322 regulator-max-microvolt = <3400000>; 323 regulator-boot-on; 324 regulator-always-on; 325 }; 326 327 buck6: BUCK6 { 328 regulator-name = "BUCK6"; 329 regulator-min-microvolt = <1060000>; 330 regulator-max-microvolt = <1140000>; 331 regulator-boot-on; 332 regulator-always-on; 333 }; 334 335 ldo1: LDO1 { 336 regulator-name = "LDO1"; 337 regulator-min-microvolt = <1620000>; 338 regulator-max-microvolt = <1980000>; 339 regulator-boot-on; 340 regulator-always-on; 341 }; 342 343 ldo4: LDO4 { 344 regulator-name = "LDO4"; 345 regulator-min-microvolt = <800000>; 346 regulator-max-microvolt = <840000>; 347 regulator-boot-on; 348 regulator-always-on; 349 }; 350 351 ldo5: LDO5 { 352 regulator-name = "LDO5"; 353 regulator-min-microvolt = <1800000>; 354 regulator-max-microvolt = <3300000>; 355 regulator-boot-on; 356 regulator-always-on; 357 }; 358 }; 359 }; 360 361 adp5585: io-expander@34 { 362 compatible = "adi,adp5585-00", "adi,adp5585"; 363 reg = <0x34>; 364 vdd-supply = <&buck4>; 365 gpio-controller; 366 #gpio-cells = <2>; 367 gpio-reserved-ranges = <5 1>; 368 #pwm-cells = <3>; 369 }; 370}; 371 372&lpi2c3 { 373 clock-frequency = <400000>; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&pinctrl_lpi2c3>; 376 status = "okay"; 377 378 adp5585_isp: io-expander@34 { 379 compatible = "adi,adp5585-01", "adi,adp5585"; 380 reg = <0x34>; 381 gpio-controller; 382 #gpio-cells = <2>; 383 #pwm-cells = <3>; 384 }; 385 386 ptn5110: tcpc@50 { 387 compatible = "nxp,ptn5110", "tcpci"; 388 reg = <0x50>; 389 interrupt-parent = <&gpio3>; 390 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 391 392 typec1_con: connector { 393 compatible = "usb-c-connector"; 394 label = "USB-C"; 395 power-role = "dual"; 396 data-role = "dual"; 397 try-power-role = "sink"; 398 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 399 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 400 PDO_VAR(5000, 20000, 3000)>; 401 op-sink-microwatt = <15000000>; 402 self-powered; 403 404 ports { 405 #address-cells = <1>; 406 #size-cells = <0>; 407 408 port@0 { 409 reg = <0>; 410 411 typec1_dr_sw: endpoint { 412 remote-endpoint = <&usb1_drd_sw>; 413 }; 414 }; 415 }; 416 }; 417 }; 418 419 ptn5110_2: tcpc@51 { 420 compatible = "nxp,ptn5110", "tcpci"; 421 reg = <0x51>; 422 interrupt-parent = <&gpio3>; 423 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 424 425 typec2_con: connector { 426 compatible = "usb-c-connector"; 427 label = "USB-C"; 428 power-role = "dual"; 429 data-role = "dual"; 430 try-power-role = "sink"; 431 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 432 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 433 PDO_VAR(5000, 20000, 3000)>; 434 op-sink-microwatt = <15000000>; 435 self-powered; 436 437 ports { 438 #address-cells = <1>; 439 #size-cells = <0>; 440 441 port@0 { 442 reg = <0>; 443 444 typec2_dr_sw: endpoint { 445 remote-endpoint = <&usb2_drd_sw>; 446 }; 447 }; 448 }; 449 }; 450 }; 451 452 pcf2131: rtc@53 { 453 compatible = "nxp,pcf2131"; 454 reg = <0x53>; 455 interrupt-parent = <&pcal6524>; 456 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 457 }; 458}; 459 460&lpuart1 { /* console */ 461 pinctrl-names = "default"; 462 pinctrl-0 = <&pinctrl_uart1>; 463 status = "okay"; 464}; 465 466&lpuart5 { 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pinctrl_uart5>; 469 status = "okay"; 470 471 bluetooth { 472 compatible = "nxp,88w8987-bt"; 473 }; 474}; 475 476&mu1 { 477 status = "okay"; 478}; 479 480&mu2 { 481 status = "okay"; 482}; 483 484&sai3 { 485 pinctrl-names = "default", "sleep"; 486 pinctrl-0 = <&pinctrl_sai3>; 487 pinctrl-1 = <&pinctrl_sai3_sleep>; 488 assigned-clocks = <&clk IMX93_CLK_SAI3>; 489 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 490 assigned-clock-rates = <12288000>; 491 fsl,sai-mclk-direction-output; 492 status = "okay"; 493}; 494 495&usbotg1 { 496 dr_mode = "otg"; 497 hnp-disable; 498 srp-disable; 499 adp-disable; 500 usb-role-switch; 501 disable-over-current; 502 samsung,picophy-pre-emp-curr-control = <3>; 503 samsung,picophy-dc-vol-level-adjust = <7>; 504 status = "okay"; 505 506 port { 507 usb1_drd_sw: endpoint { 508 remote-endpoint = <&typec1_dr_sw>; 509 }; 510 }; 511}; 512 513&usbotg2 { 514 dr_mode = "otg"; 515 hnp-disable; 516 srp-disable; 517 adp-disable; 518 usb-role-switch; 519 disable-over-current; 520 samsung,picophy-pre-emp-curr-control = <3>; 521 samsung,picophy-dc-vol-level-adjust = <7>; 522 status = "okay"; 523 524 port { 525 usb2_drd_sw: endpoint { 526 remote-endpoint = <&typec2_dr_sw>; 527 }; 528 }; 529}; 530 531&usdhc1 { 532 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 533 pinctrl-0 = <&pinctrl_usdhc1>; 534 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 535 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 536 bus-width = <8>; 537 non-removable; 538 fsl,tuning-step = <1>; 539 status = "okay"; 540}; 541 542&usdhc2 { 543 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 544 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 545 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 546 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 547 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 548 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 549 vmmc-supply = <®_usdhc2_vmmc>; 550 bus-width = <4>; 551 fsl,tuning-step = <1>; 552 status = "okay"; 553 no-mmc; 554}; 555 556&wdog3 { 557 pinctrl-names = "default"; 558 pinctrl-0 = <&pinctrl_wdog>; 559 fsl,ext-reset-output; 560 status = "okay"; 561}; 562 563&xcvr { 564 pinctrl-names = "default", "sleep"; 565 pinctrl-0 = <&pinctrl_spdif>; 566 pinctrl-1 = <&pinctrl_spdif_sleep>; 567 assigned-clocks = <&clk IMX93_CLK_SPDIF>, 568 <&clk IMX93_CLK_AUDIO_XCVR>; 569 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, 570 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 571 assigned-clock-rates = <12288000>, <200000000>; 572 status = "okay"; 573}; 574 575&iomuxc { 576 pinctrl_eqos: eqosgrp { 577 fsl,pins = < 578 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 579 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 580 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 581 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 582 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 583 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 584 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e 585 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 586 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 587 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 588 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 589 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 590 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 591 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 592 >; 593 }; 594 595 pinctrl_eqos_sleep: eqossleepgrp { 596 fsl,pins = < 597 MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e 598 MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e 599 MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e 600 MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e 601 MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e 602 MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e 603 MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e 604 MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e 605 MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e 606 MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e 607 MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e 608 MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e 609 MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e 610 MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e 611 >; 612 }; 613 614 pinctrl_fec: fecgrp { 615 fsl,pins = < 616 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e 617 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e 618 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 619 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 620 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 621 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 622 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e 623 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 624 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 625 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 626 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 627 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 628 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e 629 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 630 >; 631 }; 632 633 pinctrl_fec_sleep: fecsleepgrp { 634 fsl,pins = < 635 MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e 636 MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e 637 MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e 638 MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e 639 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e 640 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e 641 MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e 642 MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e 643 MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e 644 MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e 645 MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e 646 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e 647 MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e 648 MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e 649 >; 650 }; 651 652 pinctrl_flexcan2: flexcan2grp { 653 fsl,pins = < 654 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e 655 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e 656 >; 657 }; 658 659 pinctrl_uart1: uart1grp { 660 fsl,pins = < 661 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 662 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 663 >; 664 }; 665 666 pinctrl_uart5: uart5grp { 667 fsl,pins = < 668 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 669 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 670 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 671 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 672 >; 673 }; 674 675 pinctrl_lpi2c1: lpi2c1grp { 676 fsl,pins = < 677 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 678 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 679 >; 680 }; 681 682 pinctrl_lpi2c2: lpi2c2grp { 683 fsl,pins = < 684 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 685 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 686 >; 687 }; 688 689 pinctrl_lpi2c3: lpi2c3grp { 690 fsl,pins = < 691 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 692 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 693 >; 694 }; 695 696 pinctrl_pcal6524: pcal6524grp { 697 fsl,pins = < 698 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e 699 >; 700 }; 701 702 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 703 pinctrl_usdhc1: usdhc1grp { 704 fsl,pins = < 705 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 706 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 707 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 708 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 709 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 710 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 711 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 712 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 713 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 714 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 715 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 716 >; 717 }; 718 719 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 720 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 721 fsl,pins = < 722 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 723 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 724 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 725 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 726 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 727 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 728 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 729 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 730 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 731 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 732 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 733 >; 734 }; 735 736 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 737 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 738 fsl,pins = < 739 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 740 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 741 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 742 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 743 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 744 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 745 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 746 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 747 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 748 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 749 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 750 >; 751 }; 752 753 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 754 fsl,pins = < 755 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 756 >; 757 }; 758 759 pinctrl_sai3: sai3grp { 760 fsl,pins = < 761 MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e 762 MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e 763 MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e 764 MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e 765 MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e 766 >; 767 }; 768 769 pinctrl_sai3_sleep: sai3sleepgrp { 770 fsl,pins = < 771 MX93_PAD_GPIO_IO26__GPIO2_IO26 0x51e 772 MX93_PAD_GPIO_IO16__GPIO2_IO16 0x51e 773 MX93_PAD_GPIO_IO17__GPIO2_IO17 0x51e 774 MX93_PAD_GPIO_IO19__GPIO2_IO19 0x51e 775 MX93_PAD_GPIO_IO20__GPIO2_IO20 0x51e 776 >; 777 }; 778 779 pinctrl_spdif: spdifgrp { 780 fsl,pins = < 781 MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e 782 MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e 783 >; 784 }; 785 786 pinctrl_spdif_sleep: spdifsleepgrp { 787 fsl,pins = < 788 MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e 789 MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e 790 >; 791 }; 792 793 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 794 fsl,pins = < 795 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 796 >; 797 }; 798 799 pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { 800 fsl,pins = < 801 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e 802 >; 803 }; 804 805 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 806 pinctrl_usdhc2: usdhc2grp { 807 fsl,pins = < 808 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 809 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 810 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 811 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 812 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 813 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 814 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 815 >; 816 }; 817 818 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 819 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 820 fsl,pins = < 821 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 822 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 823 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 824 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 825 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 826 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 827 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 828 >; 829 }; 830 831 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 832 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 833 fsl,pins = < 834 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 835 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 836 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 837 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 838 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 839 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 840 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 841 >; 842 }; 843 844 pinctrl_usdhc2_sleep: usdhc2sleepgrp { 845 fsl,pins = < 846 MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e 847 MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e 848 MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e 849 MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e 850 MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e 851 MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e 852 MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e 853 >; 854 }; 855 856 pinctrl_wdog: wdoggrp { 857 fsl,pins = < 858 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 859 >; 860 }; 861}; 862