1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Common dtsi for Variscite VAR-SOM-MX91 4 * 5 * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/var-som-mx91/ 6 * 7 * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11/dts-v1/; 12 13#include "imx91.dtsi" 14 15/{ 16 model = "Variscite VAR-SOM-MX91 module"; 17 compatible = "variscite,var-som-mx91", "fsl,imx91"; 18 19 usdhc3_pwrseq: mmc-pwrseq { 20 compatible = "mmc-pwrseq-simple"; 21 post-power-on-delay-ms = <100>; 22 power-off-delay-us = <10000>; 23 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ 24 <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ 25 }; 26 27 sound { 28 compatible = "simple-audio-card"; 29 simple-audio-card,bitclock-master = <&codec_dai>; 30 simple-audio-card,format = "i2s"; 31 simple-audio-card,frame-master = <&codec_dai>; 32 simple-audio-card,name = "wm8904-audio"; 33 simple-audio-card,routing = 34 "Headphone Jack", "HPOUTL", 35 "Headphone Jack", "HPOUTR", 36 "IN2L", "Line In Jack", 37 "IN2R", "Line In Jack", 38 "IN1L", "Microphone Jack", 39 "IN1R", "Microphone Jack"; 40 simple-audio-card,widgets = 41 "Microphone", "Microphone Jack", 42 "Headphone", "Headphone Jack", 43 "Line", "Line In Jack"; 44 simple-audio-card,mclk-fs = <256>; 45 46 codec_dai: simple-audio-card,codec { 47 sound-dai = <&wm8904>; 48 }; 49 50 simple-audio-card,cpu { 51 sound-dai = <&sai1>; 52 }; 53 }; 54}; 55 56&eqos { 57 pinctrl-names = "default", "sleep"; 58 pinctrl-0 = <&pinctrl_eqos>; 59 pinctrl-1 = <&pinctrl_eqos_sleep>; 60 /* 61 * The required RGMII TX and RX 2ns delays are implemented directly 62 * in hardware via passive delay elements on the SOM PCB. 63 * No delay configuration is needed in software via PHY driver. 64 */ 65 phy-mode = "rgmii"; 66 phy-handle = <ðphy0>; 67 snps,clk-csr = <5>; 68 status = "okay"; 69 70 mdio { 71 compatible = "snps,dwmac-mdio"; 72 #address-cells = <1>; 73 #size-cells = <0>; 74 75 ethphy0: ethernet-phy@0 { 76 compatible = "ethernet-phy-ieee802.3-c22"; 77 reg = <0>; 78 eee-broken-1000t; 79 reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; 80 reset-assert-us = <15000>; 81 reset-deassert-us = <100000>; 82 }; 83 }; 84}; 85 86&lpi2c3 { 87 clock-frequency = <400000>; 88 pinctrl-names = "default", "sleep", "gpio"; 89 pinctrl-0 = <&pinctrl_lpi2c3>; 90 pinctrl-1 = <&pinctrl_lpi2c3_gpio>; 91 pinctrl-2 = <&pinctrl_lpi2c3_gpio>; 92 scl-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; 93 sda-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; 94 status = "okay"; 95 96 pmic@25 { 97 compatible = "nxp,pca9451a"; 98 reg = <0x25>; 99 100 regulators { 101 buck1: BUCK1 { 102 regulator-name = "BUCK1"; 103 regulator-min-microvolt = <650000>; 104 regulator-max-microvolt = <2237500>; 105 regulator-boot-on; 106 regulator-always-on; 107 regulator-ramp-delay = <3125>; 108 }; 109 110 buck2: BUCK2 { 111 regulator-name = "BUCK2"; 112 regulator-min-microvolt = <600000>; 113 regulator-max-microvolt = <2187500>; 114 regulator-boot-on; 115 regulator-always-on; 116 regulator-ramp-delay = <3125>; 117 }; 118 119 buck4: BUCK4 { 120 regulator-name = "BUCK4"; 121 regulator-min-microvolt = <600000>; 122 regulator-max-microvolt = <3400000>; 123 regulator-boot-on; 124 regulator-always-on; 125 }; 126 127 buck5: BUCK5 { 128 regulator-name = "BUCK5"; 129 regulator-min-microvolt = <600000>; 130 regulator-max-microvolt = <3400000>; 131 regulator-boot-on; 132 regulator-always-on; 133 }; 134 135 buck6: BUCK6 { 136 regulator-name = "BUCK6"; 137 regulator-min-microvolt = <600000>; 138 regulator-max-microvolt = <3400000>; 139 regulator-boot-on; 140 regulator-always-on; 141 }; 142 143 ldo1: LDO1 { 144 regulator-name = "LDO1"; 145 regulator-min-microvolt = <1600000>; 146 regulator-max-microvolt = <3300000>; 147 regulator-boot-on; 148 regulator-always-on; 149 }; 150 151 ldo4: LDO4 { 152 regulator-name = "LDO4"; 153 regulator-min-microvolt = <800000>; 154 regulator-max-microvolt = <3300000>; 155 regulator-boot-on; 156 regulator-always-on; 157 }; 158 159 ldo5: LDO5 { 160 regulator-name = "LDO5"; 161 regulator-min-microvolt = <1800000>; 162 regulator-max-microvolt = <3300000>; 163 regulator-boot-on; 164 regulator-always-on; 165 }; 166 }; 167 }; 168 169 wm8904: audio-codec@1a { 170 compatible = "wlf,wm8904"; 171 reg = <0x1a>; 172 #sound-dai-cells = <0>; 173 clocks = <&clk IMX93_CLK_SAI1_GATE>; 174 clock-names = "mclk"; 175 AVDD-supply = <&buck5>; 176 CPVDD-supply = <&buck5>; 177 DBVDD-supply = <&buck4>; 178 DCVDD-supply = <&buck5>; 179 MICVDD-supply = <&buck5>; 180 wlf,drc-cfg-names = "default", "peaklimiter", "tradition", 181 "soft", "music"; 182 /* 183 * Config registers per name, respectively: 184 * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 185 * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 186 * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 187 * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 188 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 189 */ 190 wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, 191 /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, 192 /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, 193 /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, 194 /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; 195 /* GPIO1 = DMIC_CLK, don't touch others */ 196 wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; 197 }; 198}; 199 200&lpspi8 { 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_lpspi8>; 203 cs-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 204 status = "okay"; 205}; 206 207/* BT module */ 208&lpuart5 { 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_lpuart5>, <&pinctrl_bluetooth>; 211 uart-has-rtscts; 212 status = "okay"; 213 214 bluetooth { 215 compatible = "nxp,88w8987-bt"; 216 }; 217}; 218 219&sai1 { 220 pinctrl-names = "default", "sleep"; 221 pinctrl-0 = <&pinctrl_sai1>; 222 pinctrl-1 = <&pinctrl_sai1_sleep>; 223 assigned-clocks = <&clk IMX93_CLK_SAI1>; 224 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 225 assigned-clock-rates = <12288000>; 226 fsl,sai-mclk-direction-output; 227 status = "okay"; 228}; 229 230/* eMMC */ 231&usdhc1 { 232 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 233 pinctrl-0 = <&pinctrl_usdhc1>; 234 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 235 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 236 bus-width = <8>; 237 non-removable; 238 status = "okay"; 239}; 240 241/* WiFi */ 242&usdhc3 { 243 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 244 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; 245 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; 246 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; 247 pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; 248 bus-width = <4>; 249 keep-power-in-suspend; 250 mmc-pwrseq = <&usdhc3_pwrseq>; 251 non-removable; 252 wakeup-source; 253 status = "okay"; 254}; 255 256&iomuxc { 257 pinctrl_bluetooth: bluetoothgrp { 258 fsl,pins = < 259 MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e 260 >; 261 }; 262 263 pinctrl_eqos: eqosgrp { 264 fsl,pins = < 265 MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e 266 MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 267 MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 268 MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 269 MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 270 MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 271 MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe 272 MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 273 MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 274 MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e 275 MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 276 MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 277 MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe 278 MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 279 MX91_PAD_UART2_TXD__GPIO1_IO7 0x51e 280 >; 281 }; 282 283 pinctrl_eqos_sleep: eqos-sleepgrp { 284 fsl,pins = < 285 MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e 286 MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e 287 MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e 288 MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e 289 MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e 290 MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e 291 MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e 292 MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e 293 MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e 294 MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e 295 MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e 296 MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e 297 MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e 298 MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e 299 >; 300 }; 301 302 pinctrl_lpi2c3: lpi2c3grp { 303 fsl,pins = < 304 MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 305 MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 306 >; 307 }; 308 309 pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp { 310 fsl,pins = < 311 MX91_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e 312 MX91_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e 313 >; 314 }; 315 316 pinctrl_lpspi8: lpspi8grp { 317 fsl,pins = < 318 MX91_PAD_GPIO_IO12__GPIO2_IO12 0x31e 319 MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x31e 320 MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x31e 321 MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x31e 322 >; 323 }; 324 325 pinctrl_lpuart5: lpuart5grp { 326 fsl,pins = < 327 MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 328 MX91_PAD_DAP_TDI__LPUART5_RX 0x31e 329 MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 330 MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 331 >; 332 }; 333 334 pinctrl_sai1: sai1grp { 335 fsl,pins = < 336 MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e 337 MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e 338 MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e 339 MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e 340 MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e 341 MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e 342 MX91_PAD_UART2_RXD__SAI1_MCLK 0x31e 343 >; 344 }; 345 346 pinctrl_sai1_sleep: sai1-sleepgrp { 347 fsl,pins = < 348 MX91_PAD_SAI1_TXC__GPIO1_IO12 0x31e 349 MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x31e 350 MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x31e 351 MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x31e 352 MX91_PAD_UART2_RXD__GPIO1_IO6 0x31e 353 MX91_PAD_I2C2_SDA__GPIO1_IO3 0x31e 354 MX91_PAD_I2C2_SCL__GPIO1_IO2 0x31e 355 >; 356 }; 357 358 pinctrl_usdhc1: usdhc1grp { 359 fsl,pins = < 360 MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 361 MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 362 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 363 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 364 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 365 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 366 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 367 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 368 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 369 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 370 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 371 >; 372 }; 373 374 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 375 fsl,pins = < 376 MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e 377 MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e 378 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 379 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 380 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 381 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 382 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 383 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 384 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 385 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 386 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 387 >; 388 }; 389 390 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 391 fsl,pins = < 392 MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe 393 MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe 394 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 395 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 396 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 397 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 398 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 399 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 400 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 401 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 402 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 403 >; 404 }; 405 406 pinctrl_usdhc3: usdhc3grp { 407 fsl,pins = < 408 MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 409 MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 410 MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 411 MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 412 MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 413 MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 414 >; 415 }; 416 417 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 418 fsl,pins = < 419 MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e 420 MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e 421 MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e 422 MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e 423 MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e 424 MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e 425 >; 426 }; 427 428 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 429 fsl,pins = < 430 MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe 431 MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe 432 MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe 433 MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe 434 MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe 435 MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe 436 >; 437 }; 438 439 pinctrl_usdhc3_sleep: usdhc3-sleepgrp { 440 fsl,pins = < 441 MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e 442 MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e 443 MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e 444 MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e 445 MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e 446 MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e 447 >; 448 }; 449 450 pinctrl_usdhc3_wlan: usdhc3-wlangrp { 451 fsl,pins = < 452 MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e 453 MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x51e 454 >; 455 }; 456}; 457