1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Variscite Symphony carrier board for VAR-SOM-MX91 4 * 5 * Link: https://variscite.com/carrier-boards/symphony-board/ 6 * 7 * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11/dts-v1/; 12 13#include <dt-bindings/leds/common.h> 14#include "imx91-var-som.dtsi" 15 16/{ 17 model = "Variscite VAR-SOM-MX91 on Symphony evaluation board"; 18 compatible = "variscite,var-som-mx91-symphony", 19 "variscite,var-som-mx91", "fsl,imx91"; 20 21 aliases { 22 ethernet0 = &eqos; 23 ethernet1 = &fec; 24 gpio0 = &gpio1; 25 gpio1 = &gpio2; 26 gpio2 = &gpio3; 27 gpio3 = &gpio4; 28 gpio4 = &pca9534; 29 gpio5 = &pca6408; 30 i2c0 = &lpi2c1; 31 i2c1 = &lpi2c2; 32 i2c2 = &lpi2c3; 33 mmc0 = &usdhc1; 34 mmc1 = &usdhc2; 35 serial0 = &lpuart1; 36 serial1 = &lpuart2; 37 serial2 = &lpuart3; 38 serial3 = &lpuart4; 39 serial4 = &lpuart5; 40 }; 41 42 chosen { 43 stdout-path = &lpuart1; 44 }; 45 46 gpio-keys { 47 compatible = "gpio-keys"; 48 49 key-back { 50 label = "Back"; 51 gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; 52 linux,code = <KEY_BACK>; 53 }; 54 55 key-home { 56 label = "Home"; 57 gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; 58 linux,code = <KEY_HOME>; 59 }; 60 61 key-menu { 62 label = "Menu"; 63 gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; 64 linux,code = <KEY_MENU>; 65 }; 66 }; 67 68 gpio-leds { 69 compatible = "gpio-leds"; 70 71 led-hearthbeat { 72 function = LED_FUNCTION_STATUS; 73 color = <LED_COLOR_ID_GREEN>; 74 gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; 75 linux,default-trigger = "heartbeat"; 76 }; 77 }; 78 79 reg_vref_1v8: regulator-adc-vref { 80 compatible = "regulator-fixed"; 81 regulator-name = "vref_1v8"; 82 regulator-min-microvolt = <1800000>; 83 regulator-max-microvolt = <1800000>; 84 }; 85 86 /* 87 * Needed only for Symphony <= v1.5 88 */ 89 reg_fec_phy: regulator-fec-phy { 90 compatible = "regulator-fixed"; 91 regulator-name = "fec-phy"; 92 regulator-min-microvolt = <1800000>; 93 regulator-max-microvolt = <1800000>; 94 regulator-enable-ramp-delay = <20000>; 95 gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; 96 enable-active-high; 97 regulator-always-on; 98 }; 99 100 reg_usdhc2_vmmc: regulator-usdhc2 { 101 compatible = "regulator-fixed"; 102 regulator-name = "VSD_3V3"; 103 regulator-min-microvolt = <3300000>; 104 regulator-max-microvolt = <3300000>; 105 gpio = <&pca6408 6 GPIO_ACTIVE_HIGH>; 106 off-on-delay-us = <20000>; 107 enable-active-high; 108 }; 109 110 reserved-memory { 111 ranges; 112 #address-cells = <2>; 113 #size-cells = <2>; 114 115 ele_reserved: ele-reserved@87de0000 { 116 compatible = "shared-dma-pool"; 117 reg = <0 0x87de0000 0 0x100000>; 118 no-map; 119 }; 120 121 linux,cma { 122 compatible = "shared-dma-pool"; 123 alloc-ranges = <0 0x80000000 0 0x40000000>; 124 reusable; 125 size = <0 0x10000000>; 126 linux,cma-default; 127 }; 128 }; 129}; 130 131&adc1 { 132 vref-supply = <®_vref_1v8>; 133 status = "okay"; 134}; 135 136/* Use external instead of internal RTC*/ 137&bbnsm_rtc { 138 status = "disabled"; 139}; 140 141&eqos { 142 mdio { 143 ethphy1: ethernet-phy@5 { 144 compatible = "ethernet-phy-ieee802.3-c22"; 145 reg = <5>; 146 eee-broken-1000t; 147 reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; 148 reset-assert-us = <10000>; 149 reset-deassert-us = <20000>; 150 vddio-supply = <&vddio1>; 151 152 leds { 153 #address-cells = <1>; 154 #size-cells = <0>; 155 156 led@0 { 157 reg = <0>; 158 color = <LED_COLOR_ID_YELLOW>; 159 function = LED_FUNCTION_LAN; 160 linux,default-trigger = "netdev"; 161 }; 162 163 led@1 { 164 reg = <1>; 165 color = <LED_COLOR_ID_GREEN>; 166 function = LED_FUNCTION_LAN; 167 linux,default-trigger = "netdev"; 168 }; 169 }; 170 171 vddio1: vddio-regulator { 172 regulator-min-microvolt = <1800000>; 173 regulator-max-microvolt = <1800000>; 174 }; 175 }; 176 }; 177}; 178 179ðphy0 { 180 leds { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 184 led@0 { 185 reg = <0>; 186 color = <LED_COLOR_ID_YELLOW>; 187 function = LED_FUNCTION_LAN; 188 linux,default-trigger = "netdev"; 189 }; 190 191 led@1 { 192 reg = <1>; 193 color = <LED_COLOR_ID_GREEN>; 194 function = LED_FUNCTION_LAN; 195 linux,default-trigger = "netdev"; 196 }; 197 }; 198}; 199 200&fec { 201 pinctrl-names = "default", "sleep"; 202 pinctrl-0 = <&pinctrl_fec>; 203 pinctrl-1 = <&pinctrl_fec_sleep>; 204 /* 205 * The required RGMII TX and RX 2ns delays are implemented directly 206 * in hardware via passive delay elements on the SOM PCB. 207 * No delay configuration is needed in software via PHY driver. 208 */ 209 phy-mode = "rgmii"; 210 phy-handle = <ðphy1>; 211 phy-supply = <®_fec_phy>; 212 status = "okay"; 213}; 214 215&flexcan1 { 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_flexcan1>; 218 status = "okay"; 219}; 220 221&lpi2c1 { 222 clock-frequency = <400000>; 223 pinctrl-names = "default", "sleep", "gpio"; 224 pinctrl-0 = <&pinctrl_lpi2c1>; 225 pinctrl-1 = <&pinctrl_lpi2c1_gpio>; 226 pinctrl-2 = <&pinctrl_lpi2c1_gpio>; 227 scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; 228 sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 229 status = "okay"; 230 231 pca9534: gpio@20 { 232 compatible = "nxp,pca9534"; 233 reg = <0x20>; 234 gpio-controller; 235 #gpio-cells = <2>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_pca9534>; 238 interrupt-parent = <&gpio3>; 239 interrupts = <26 IRQ_TYPE_EDGE_FALLING>; 240 wakeup-source; 241 }; 242 243 pca6408: gpio@21 { 244 compatible = "nxp,pcal6408"; 245 reg = <0x21>; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_pca6408>; 248 gpio-controller; 249 #gpio-cells = <2>; 250 interrupt-controller; 251 #interrupt-cells = <2>; 252 interrupt-parent = <&gpio2>; 253 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; 254 wakeup-source; 255 256 tpm-enable-hog { 257 gpio-hog; 258 gpios = <4 GPIO_ACTIVE_HIGH>; 259 output-high; 260 line-name = "tpm_en"; 261 }; 262 263 /* RGB_SEL */ 264 lvds-brg-enable-hog { 265 gpio-hog; 266 gpios = <7 GPIO_ACTIVE_HIGH>; 267 output-high; 268 line-name = "lvds_brg_en"; 269 }; 270 }; 271 272 /* USB Type-C Controller */ 273 ptn5150: typec@3d { 274 compatible = "nxp,ptn5150"; 275 reg = <0x3d>; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_ptn5150>; 278 interrupt-parent = <&gpio1>; 279 interrupts = <10 IRQ_TYPE_NONE>; 280 281 port { 282 typec1_dr_sw: endpoint { 283 remote-endpoint = <&usb1_drd_sw>; 284 }; 285 }; 286 }; 287 288 st33ktpm2xi2c: tpm@2e { 289 compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; 290 reg = <0x2e>; 291 }; 292 293 /* Capacitive touch controller */ 294 ft5x06_ts: touchscreen@38 { 295 compatible = "edt,edt-ft5206"; 296 reg = <0x38>; 297 interrupt-parent = <&pca6408>; 298 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 299 touchscreen-size-x = <800>; 300 touchscreen-size-y = <480>; 301 touchscreen-inverted-x; 302 touchscreen-inverted-y; 303 wakeup-source; 304 }; 305 306 /* DS1337 RTC module */ 307 rtc@68 { 308 compatible = "dallas,ds1337"; 309 reg = <0x68>; 310 }; 311}; 312 313/* pins conflict */ 314&lpspi8 { 315 status = "disabled"; 316}; 317 318/* Console */ 319&lpuart1 { 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_uart1>; 322 status = "okay"; 323}; 324 325&tpm4 { 326 pinctrl-names = "default", "sleep"; 327 pinctrl-0 = <&pinctrl_tpm4>; 328 pinctrl-1 = <&pinctrl_tpm4_sleep>; 329 status = "okay"; 330}; 331 332&usbotg1 { 333 dr_mode = "otg"; 334 hnp-disable; 335 srp-disable; 336 adp-disable; 337 usb-role-switch; 338 samsung,picophy-pre-emp-curr-control = <3>; 339 samsung,picophy-dc-vol-level-adjust = <7>; 340 status = "okay"; 341 342 port { 343 usb1_drd_sw: endpoint { 344 remote-endpoint = <&typec1_dr_sw>; 345 }; 346 }; 347}; 348 349&usbotg2 { 350 dr_mode = "host"; 351 disable-over-current; 352 status = "okay"; 353}; 354 355/* SD */ 356&usdhc2 { 357 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 358 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 359 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 360 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 361 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 362 bus-width = <4>; 363 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 364 no-mmc; 365 no-sdio; 366 vmmc-supply = <®_usdhc2_vmmc>; 367 status = "okay"; 368}; 369 370/* Watchdog */ 371&wdog3 { 372 status = "okay"; 373}; 374 375&iomuxc { 376 pinctrl_fec: fecgrp { 377 fsl,pins = < 378 MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e 379 MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e 380 MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e 381 MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e 382 MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe 383 MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e 384 MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e 385 MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e 386 MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e 387 MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e 388 MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe 389 MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e 390 >; 391 }; 392 393 pinctrl_fec_sleep: fecsleepgrp { 394 fsl,pins = < 395 MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e 396 MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e 397 MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e 398 MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e 399 MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e 400 MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e 401 MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e 402 MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e 403 MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e 404 MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e 405 MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e 406 MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e 407 >; 408 }; 409 410 pinctrl_flexcan1: flexcan1grp { 411 fsl,pins = < 412 MX91_PAD_PDM_CLK__CAN1_TX 0x139e 413 MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 414 >; 415 }; 416 417 pinctrl_lpi2c1: lpi2c1grp { 418 fsl,pins = < 419 MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 420 MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 421 >; 422 }; 423 424 pinctrl_lpi2c1_gpio: lpi2c1gpiogrp { 425 fsl,pins = < 426 MX91_PAD_I2C1_SCL__GPIO1_IO0 0x31e 427 MX91_PAD_I2C1_SDA__GPIO1_IO1 0x31e 428 >; 429 }; 430 431 pinctrl_pca6408: pca6408grp { 432 fsl,pins = < 433 MX91_PAD_GPIO_IO04__GPIO2_IO4 0x31e 434 >; 435 }; 436 437 pinctrl_pca9534: pca9534grp { 438 fsl,pins = < 439 MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e 440 >; 441 }; 442 443 pinctrl_ptn5150: ptn5150grp { 444 fsl,pins = < 445 MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e 446 >; 447 }; 448 449 pinctrl_uart1: uart1grp { 450 fsl,pins = < 451 MX91_PAD_UART1_RXD__LPUART1_RX 0x31e 452 MX91_PAD_UART1_TXD__LPUART1_TX 0x31e 453 >; 454 }; 455 456 pinctrl_tpm4: tpm4grp { 457 fsl,pins = < 458 MX91_PAD_GPIO_IO05__TPM4_CH0 0x51e 459 >; 460 }; 461 462 pinctrl_tpm4_sleep: tpm4sleepgrp { 463 fsl,pins = < 464 MX91_PAD_GPIO_IO05__GPIO2_IO5 0x51e 465 >; 466 }; 467 468 pinctrl_usdhc2: usdhc2grp { 469 fsl,pins = < 470 MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 471 MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 472 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 473 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 474 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 475 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 476 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 477 >; 478 }; 479 480 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 481 fsl,pins = < 482 MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e 483 MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e 484 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 485 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 486 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 487 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 488 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 489 >; 490 }; 491 492 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 493 fsl,pins = < 494 MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe 495 MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe 496 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 497 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 498 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 499 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 500 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 501 >; 502 }; 503 504 pinctrl_usdhc2_sleep: usdhc2sleep-grp { 505 fsl,pins = < 506 MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e 507 MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e 508 MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e 509 MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e 510 MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e 511 MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e 512 MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e 513 >; 514 }; 515 516 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 517 fsl,pins = < 518 MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e 519 >; 520 }; 521 522 pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleep-grp { 523 fsl,pins = < 524 MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e 525 >; 526 }; 527}; 528