1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 5 * Author: Markus Niebel 6 * Author: Alexander Stein 7 */ 8 9#include "imx91.dtsi" 10 11/{ 12 model = "TQ-Systems i.MX91 TQMa91xxCA / TQMa91xxLA SOM"; 13 compatible = "tq,imx91-tqma9131", "fsl,imx91"; 14 15 memory@80000000 { 16 device_type = "memory"; 17 /* our minimum RAM config will be 1024 MiB */ 18 reg = <0x00000000 0x80000000 0 0x40000000>; 19 }; 20 21 reserved-memory { 22 #address-cells = <2>; 23 #size-cells = <2>; 24 ranges; 25 26 /* default CMA, must not exceed assembled memory */ 27 linux,cma { 28 compatible = "shared-dma-pool"; 29 reusable; 30 alloc-ranges = <0 0x80000000 0 0x40000000>; 31 size = <0 0x10000000>; 32 linux,cma-default; 33 }; 34 35 /* EdgeLock secure enclave */ 36 ele_reserved: ele-reserved@a4120000 { 37 compatible = "shared-dma-pool"; 38 reg = <0 0xa4120000 0 0x100000>; 39 no-map; 40 }; 41 }; 42 43 /* SD2 RST# via PMIC SW_EN */ 44 reg_usdhc2_vmmc: regulator-usdhc2 { 45 compatible = "regulator-fixed"; 46 pinctrl-names = "default"; 47 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 48 regulator-name = "VSD_3V3"; 49 regulator-min-microvolt = <3300000>; 50 regulator-max-microvolt = <3300000>; 51 vin-supply = <&buck4>; 52 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 53 enable-active-high; 54 }; 55}; 56 57&adc1 { 58 vref-supply = <&buck5>; 59}; 60 61&flexspi1 { 62 pinctrl-names = "default"; 63 pinctrl-0 = <&pinctrl_flexspi1>; 64 status = "okay"; 65 66 flash0: flash@0 { 67 compatible = "jedec,spi-nor"; 68 reg = <0>; 69 /* 70 * no DQS, RXCLKSRC internal loop back, max 66 MHz 71 * clk framework uses CLK_DIVIDER_ROUND_CLOSEST 72 * selected value together with root from 73 * IMX91_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to 74 * respect the maximum value. 75 */ 76 spi-max-frequency = <62000000>; 77 spi-tx-bus-width = <4>; 78 spi-rx-bus-width = <4>; 79 vcc-supply = <&buck5>; 80 81 partitions { 82 compatible = "fixed-partitions"; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 }; 86 }; 87}; 88 89&lpi2c1 { 90 clock-frequency = <400000>; 91 pinctrl-names = "default", "sleep"; 92 pinctrl-0 = <&pinctrl_lpi2c1>; 93 pinctrl-1 = <&pinctrl_lpi2c1>; 94 status = "okay"; 95 96 se97_som: temperature-sensor@1b { 97 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 98 reg = <0x1b>; 99 }; 100 101 pca9451a: pmic@25 { 102 compatible = "nxp,pca9451a"; 103 reg = <0x25>; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_pca9451>; 106 interrupt-parent = <&gpio1>; 107 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 108 109 regulators { 110 /* V_0V8_SOC - hw developer guide: 0.75 .. 0.9 */ 111 buck1: BUCK1 { 112 regulator-name = "BUCK1"; 113 regulator-min-microvolt = <750000>; 114 regulator-max-microvolt = <900000>; 115 regulator-boot-on; 116 regulator-always-on; 117 regulator-ramp-delay = <3125>; 118 }; 119 120 /* V_DDRQ - 1.1 V for LPDDR4 */ 121 buck2: BUCK2 { 122 regulator-name = "BUCK2"; 123 regulator-min-microvolt = <1100000>; 124 regulator-max-microvolt = <1100000>; 125 regulator-boot-on; 126 regulator-always-on; 127 regulator-ramp-delay = <3125>; 128 }; 129 130 /* V_3V3 - EEPROM, RTC, ... */ 131 buck4: BUCK4 { 132 regulator-name = "BUCK4"; 133 regulator-min-microvolt = <3300000>; 134 regulator-max-microvolt = <3300000>; 135 regulator-boot-on; 136 regulator-always-on; 137 }; 138 139 /* V_1V8 - SPI NOR, eMMC, RAM VDD1... */ 140 buck5: BUCK5 { 141 regulator-name = "BUCK5"; 142 regulator-min-microvolt = <1800000>; 143 regulator-max-microvolt = <1800000>; 144 regulator-boot-on; 145 regulator-always-on; 146 }; 147 148 /* V_1V1 - RAM VDD2*/ 149 buck6: BUCK6 { 150 regulator-name = "BUCK6"; 151 regulator-min-microvolt = <1100000>; 152 regulator-max-microvolt = <1100000>; 153 regulator-boot-on; 154 regulator-always-on; 155 }; 156 157 /* V_1V8_BBSM, fix 1.8 */ 158 ldo1: LDO1 { 159 regulator-name = "LDO1"; 160 regulator-min-microvolt = <1800000>; 161 regulator-max-microvolt = <1800000>; 162 regulator-boot-on; 163 regulator-always-on; 164 }; 165 166 /* V_0V8_ANA */ 167 ldo4: LDO4 { 168 regulator-name = "LDO4"; 169 regulator-min-microvolt = <800000>; 170 regulator-max-microvolt = <800000>; 171 regulator-boot-on; 172 regulator-always-on; 173 }; 174 175 /* V_SD2 - 3.3/1.8V USDHC2 io Voltage */ 176 ldo5: LDO5 { 177 regulator-name = "LDO5"; 178 regulator-min-microvolt = <1800000>; 179 regulator-max-microvolt = <3300000>; 180 regulator-boot-on; 181 regulator-always-on; 182 }; 183 }; 184 }; 185 186 pcf85063: rtc@51 { 187 compatible = "nxp,pcf85063a"; 188 reg = <0x51>; 189 quartz-load-femtofarads = <7000>; 190 }; 191 192 eeprom0: eeprom@53 { 193 compatible = "nxp,se97b", "atmel,24c02"; 194 reg = <0x53>; 195 pagesize = <16>; 196 read-only; 197 vcc-supply = <&buck4>; 198 }; 199 200 eeprom1: eeprom@57 { 201 compatible = "atmel,24c64"; 202 reg = <0x57>; 203 pagesize = <32>; 204 vcc-supply = <&buck4>; 205 }; 206 207 /* protectable identification memory (part of M24C64-D @57) */ 208 eeprom@5f { 209 compatible = "atmel,24c64d-wl"; 210 reg = <0x5f>; 211 vcc-supply = <&buck4>; 212 }; 213 214 accelerometer@6a { 215 compatible = "st,ism330dhcx"; 216 reg = <0x6a>; 217 vdd-supply = <&buck4>; 218 vddio-supply = <&buck4>; 219 }; 220}; 221 222&usdhc1 { 223 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 224 pinctrl-0 = <&pinctrl_usdhc1>; 225 pinctrl-1 = <&pinctrl_usdhc1>; 226 pinctrl-2 = <&pinctrl_usdhc1>; 227 vmmc-supply = <&buck4>; 228 vqmmc-supply = <&buck5>; 229 bus-width = <8>; 230 non-removable; 231 no-sdio; 232 no-sd; 233 status = "okay"; 234}; 235 236&wdog3 { 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinctrl_wdog>; 239 fsl,ext-reset-output; 240 status = "okay"; 241}; 242 243&iomuxc { 244 pinctrl_flexspi1: flexspi1grp { 245 fsl,pins = /* FSEL 3 | DSE X6 */ 246 <MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x01fe>, 247 <MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x01fe>, 248 /* HYS | PU | FSEL 3 | DSE X6 */ 249 <MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x13fe>, 250 <MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x13fe>, 251 /* HYS | FSEL 3 | DSE X6 (external PU) */ 252 <MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x11fe>, 253 <MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x11fe>; 254 }; 255 256 pinctrl_lpi2c1: lpi2c1grp { 257 fsl,pins = /* SION | OD | FSEL 3 | DSE X4 */ 258 <MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x4000199e>, 259 <MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x4000199e>; 260 }; 261 262 pinctrl_pca9451: pca9451grp { 263 fsl,pins = /* HYS | PU */ 264 <MX91_PAD_I2C2_SDA__GPIO1_IO3 0x1200>; 265 }; 266 267 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 268 fsl,pins = /* FSEL 2 | DSE X2 */ 269 <MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x106>; 270 }; 271 272 /* enable SION for data and cmd pad due to ERR052021 */ 273 pinctrl_usdhc1: usdhc1grp { 274 fsl,pins = /* PD | FSEL 3 | DSE X5 */ 275 <MX91_PAD_SD1_CLK__USDHC1_CLK 0x5be>, 276 /* HYS | FSEL 0 | no drive */ 277 <MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1000>, 278 /* HYS | FSEL 3 | X5 */ 279 <MX91_PAD_SD1_CMD__USDHC1_CMD 0x400011be>, 280 /* HYS | FSEL 3 | X4 */ 281 <MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e>, 282 <MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e>, 283 <MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e>, 284 <MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e>, 285 <MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e>, 286 <MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e>, 287 <MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e>, 288 <MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e>; 289 }; 290 291 pinctrl_wdog: wdoggrp { 292 fsl,pins = /* PU | FSEL 1 | DSE X4 */ 293 <MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e>; 294 }; 295}; 296