1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 5 * Author: Markus Niebel 6 * Author: Alexander Stein 7 */ 8/dts-v1/; 9 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/leds/common.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include <dt-bindings/pwm/pwm.h> 14#include <dt-bindings/usb/pd.h> 15#include "imx91-tqma9131.dtsi" 16 17/{ 18 model = "TQ-Systems i.MX91 TQMa91xxLA/TQMa91xxCA on MBa91xxCA starter kit"; 19 compatible = "tq,imx91-tqma9131-mba91xxca", "tq,imx91-tqma9131", "fsl,imx91"; 20 chassis-type = "embedded"; 21 22 chosen { 23 stdout-path = &lpuart1; 24 }; 25 26 aliases { 27 eeprom0 = &eeprom0; 28 ethernet0 = &eqos; 29 ethernet1 = &fec; 30 gpio0 = &gpio1; 31 gpio1 = &gpio2; 32 gpio2 = &gpio3; 33 gpio3 = &gpio4; 34 i2c0 = &lpi2c1; 35 i2c1 = &lpi2c2; 36 i2c2 = &lpi2c3; 37 mmc0 = &usdhc1; 38 mmc1 = &usdhc2; 39 serial0 = &lpuart1; 40 serial1 = &lpuart2; 41 rtc0 = &pcf85063; 42 rtc1 = &bbnsm_rtc; 43 }; 44 45 backlight: backlight { 46 compatible = "pwm-backlight"; 47 pwms = <&tpm2 2 5000000 0>; 48 brightness-levels = <0 4 8 16 32 64 128 255>; 49 default-brightness-level = <7>; 50 power-supply = <®_12v0>; 51 enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>; 52 status = "disabled"; 53 }; 54 55 display: display { 56 /* 57 * Display is not fixed, so compatible has to be added from 58 * DT overlay 59 */ 60 power-supply = <®_3v3>; 61 enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>; 62 backlight = <&backlight>; 63 status = "disabled"; 64 65 port { 66 panel_in: endpoint { 67 }; 68 }; 69 }; 70 71 fan0: gpio-fan { 72 compatible = "gpio-fan"; 73 gpios = <&expander2 4 GPIO_ACTIVE_HIGH>; 74 gpio-fan,speed-map = <0 0>, <10000 1>; 75 fan-supply = <®_12v0>; 76 #cooling-cells = <2>; 77 }; 78 79 gpio-keys { 80 compatible = "gpio-keys"; 81 autorepeat; 82 83 switch-a { 84 label = "switcha"; 85 linux,code = <BTN_0>; 86 gpios = <&expander0 6 GPIO_ACTIVE_LOW>; 87 wakeup-source; 88 }; 89 90 switch-b { 91 label = "switchb"; 92 linux,code = <BTN_1>; 93 gpios = <&expander0 7 GPIO_ACTIVE_LOW>; 94 wakeup-source; 95 }; 96 }; 97 98 gpio-leds { 99 compatible = "gpio-leds"; 100 101 led-1 { 102 color = <LED_COLOR_ID_GREEN>; 103 function = LED_FUNCTION_STATUS; 104 gpios = <&expander2 6 GPIO_ACTIVE_HIGH>; 105 linux,default-trigger = "default-on"; 106 }; 107 108 led-2 { 109 color = <LED_COLOR_ID_AMBER>; 110 function = LED_FUNCTION_HEARTBEAT; 111 gpios = <&expander2 7 GPIO_ACTIVE_HIGH>; 112 linux,default-trigger = "heartbeat"; 113 }; 114 }; 115 116 iio-hwmon { 117 compatible = "iio-hwmon"; 118 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; 119 }; 120 121 lvds_encoder: lvds-encoder { 122 compatible = "ti,sn75lvds83", "lvds-encoder"; 123 powerdown-gpios = <&expander2 3 GPIO_ACTIVE_LOW>; 124 power-supply = <®_3v3>; 125 status = "disabled"; 126 127 ports { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 131 port@0 { 132 reg = <0>; 133 134 lvds_encoder_input: endpoint { 135 }; 136 }; 137 138 port@1 { 139 reg = <1>; 140 141 lvds_encoder_output: endpoint { 142 }; 143 }; 144 }; 145 }; 146 147 reg_3v3: regulator-3v3 { 148 compatible = "regulator-fixed"; 149 regulator-name = "V_3V3_MB"; 150 regulator-min-microvolt = <3300000>; 151 regulator-max-microvolt = <3300000>; 152 }; 153 154 reg_5v0: regulator-5v0 { 155 compatible = "regulator-fixed"; 156 regulator-name = "V_5V0_MB"; 157 regulator-min-microvolt = <5000000>; 158 regulator-max-microvolt = <5000000>; 159 }; 160 161 reg_12v0: regulator-12v0 { 162 compatible = "regulator-fixed"; 163 regulator-name = "V_12V"; 164 regulator-min-microvolt = <12000000>; 165 regulator-max-microvolt = <12000000>; 166 gpio = <&expander1 7 GPIO_ACTIVE_HIGH>; 167 enable-active-high; 168 }; 169 170 reg_mpcie_1v5: regulator-mpcie-1v5 { 171 compatible = "regulator-fixed"; 172 regulator-name = "V_1V5_MPCIE"; 173 regulator-min-microvolt = <1500000>; 174 regulator-max-microvolt = <1500000>; 175 gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; 176 enable-active-high; 177 regulator-always-on; 178 }; 179 180 reg_mpcie_3v3: regulator-mpcie-3v3 { 181 compatible = "regulator-fixed"; 182 regulator-name = "V_3V3_MPCIE"; 183 regulator-min-microvolt = <3300000>; 184 regulator-max-microvolt = <3300000>; 185 gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; 186 enable-active-high; 187 regulator-always-on; 188 }; 189}; 190 191&adc1 { 192 status = "okay"; 193}; 194 195&eqos { 196 pinctrl-names = "default"; 197 pinctrl-0 = <&pinctrl_eqos>; 198 phy-mode = "rgmii-id"; 199 phy-handle = <ðphy_eqos>; 200 status = "okay"; 201 202 mdio { 203 compatible = "snps,dwmac-mdio"; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 207 ethphy_eqos: ethernet-phy@0 { 208 compatible = "ethernet-phy-ieee802.3-c22"; 209 reg = <0>; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_eqos_phy>; 212 reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>; 213 reset-assert-us = <500000>; 214 reset-deassert-us = <50000>; 215 interrupt-parent = <&gpio3>; 216 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 217 enet-phy-lane-no-swap; 218 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 219 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 220 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 221 ti,dp83867-rxctrl-strap-quirk; 222 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 223 }; 224 }; 225}; 226 227&fec { 228 pinctrl-names = "default"; 229 pinctrl-0 = <&pinctrl_fec>; 230 phy-mode = "rgmii-id"; 231 phy-handle = <ðphy_fec>; 232 fsl,magic-packet; 233 status = "okay"; 234 235 mdio { 236 #address-cells = <1>; 237 #size-cells = <0>; 238 clock-frequency = <5000000>; 239 240 ethphy_fec: ethernet-phy@0 { 241 compatible = "ethernet-phy-ieee802.3-c22"; 242 reg = <0>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_fec_phy>; 245 reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>; 246 reset-assert-us = <500000>; 247 reset-deassert-us = <50000>; 248 interrupt-parent = <&gpio3>; 249 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 250 enet-phy-lane-no-swap; 251 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 252 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 253 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 254 ti,dp83867-rxctrl-strap-quirk; 255 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 256 }; 257 }; 258}; 259 260&flexcan1 { 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_flexcan1>; 263 xceiver-supply = <®_3v3>; 264 status = "okay"; 265}; 266 267&gpio1 { 268 gpio-line-names = 269 /* 00 */ "", "", "", "PMIC_IRQ#", 270 /* 04 */ "", "", "", "", 271 /* 08 */ "", "", "USB_C_ALERT#", "BM2_LCD_INT#", 272 /* 12 */ "PEX_INT#", "", "RTC_EVENT#", "", 273 /* 16 */ "", "", "", "", 274 /* 20 */ "", "", "", "", 275 /* 24 */ "", "", "", "", 276 /* 28 */ "", "", "", ""; 277}; 278 279&gpio2 { 280 gpio-line-names = 281 /* 00 */ "", "", "", "", 282 /* 04 */ "", "", "", "", 283 /* 08 */ "", "", "", "", 284 /* 12 */ "", "", "", "", 285 /* 16 */ "", "", "", "", 286 /* 20 */ "", "", "", "", 287 /* 24 */ "", "", "", "", 288 /* 28 */ "", "", "", ""; 289}; 290 291&gpio3 { 292 pinctrl-names = "default"; 293 pinctrl-0 = <&pinctrl_jtag>; 294 gpio-line-names = 295 /* 00 */ "SD2_CD#", "", "", "", 296 /* 04 */ "", "", "", "SD2_RST#", 297 /* 08 */ "", "", "", "", 298 /* 12 */ "", "", "", "", 299 /* 16 */ "", "", "", "", 300 /* 20 */ "", "", "", "", 301 /* 24 */ "", "", "ENET1_INT#", "ENET2_INT#", 302 /* 28 */ "", "", "", ""; 303}; 304 305&gpio4 { 306 gpio-line-names = 307 /* 00 */ "", "", "", "", 308 /* 04 */ "", "", "", "", 309 /* 08 */ "", "", "", "", 310 /* 12 */ "", "", "", "", 311 /* 16 */ "", "", "", "", 312 /* 20 */ "", "", "", "", 313 /* 24 */ "", "", "", "", 314 /* 28 */ "", "", "", ""; 315}; 316 317&lpi2c3 { 318 #address-cells = <1>; 319 #size-cells = <0>; 320 clock-frequency = <400000>; 321 pinctrl-names = "default", "sleep"; 322 pinctrl-0 = <&pinctrl_lpi2c3>; 323 pinctrl-1 = <&pinctrl_lpi2c3>; 324 status = "okay"; 325 326 temperature-sensor@1c { 327 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 328 reg = <0x1c>; 329 }; 330 331 ptn5110: usb-typec@50 { 332 compatible = "nxp,ptn5110", "tcpci"; 333 reg = <0x50>; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&pinctrl_typec>; 336 interrupt-parent = <&gpio1>; 337 interrupts = <10 IRQ_TYPE_EDGE_FALLING>; 338 339 connector { 340 compatible = "usb-c-connector"; 341 label = "X17"; 342 power-role = "dual"; 343 data-role = "dual"; 344 try-power-role = "sink"; 345 typec-power-opmode = "default"; 346 pd-disable; 347 self-powered; 348 349 port { 350 typec_con_hs: endpoint { 351 remote-endpoint = <&typec_hs>; 352 }; 353 }; 354 }; 355 }; 356 357 eeprom2: eeprom@54 { 358 compatible = "nxp,se97b", "atmel,24c02"; 359 reg = <0x54>; 360 pagesize = <16>; 361 vcc-supply = <®_3v3>; 362 }; 363 364 expander0: gpio@70 { 365 compatible = "nxp,pca9538"; 366 reg = <0x70>; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&pinctrl_pexp_irq>; 369 gpio-controller; 370 #gpio-cells = <2>; 371 interrupt-controller; 372 #interrupt-cells = <2>; 373 interrupt-parent = <&gpio1>; 374 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 375 vcc-supply = <®_3v3>; 376 gpio-line-names = "TEMP_EVENT_MOD#", "MPCIE_WAKE#", 377 "MPCIE_1V5_EN", "MPCIE_3V3_EN", 378 "MPCIE_PERST#", "MPCIE_WDISABLE#", 379 "BUTTON_A#", "BUTTON_B#"; 380 381 temp-event-mod-hog { 382 gpio-hog; 383 gpios = <0 GPIO_ACTIVE_LOW>; 384 input; 385 line-name = "TEMP_EVENT_MOD#"; 386 }; 387 388 mpcie-wake-hog { 389 gpio-hog; 390 gpios = <1 GPIO_ACTIVE_LOW>; 391 input; 392 line-name = "MPCIE_WAKE#"; 393 }; 394 395 /* 396 * Controls the mPCIE slot reset which is low active as 397 * reset signal. The output-low states, the signal is 398 * inactive, e.g. not in reset 399 */ 400 mpcie_rst_hog: mpcie-rst-hog { 401 gpio-hog; 402 gpios = <4 GPIO_ACTIVE_LOW>; 403 output-low; 404 line-name = "MPCIE_PERST#"; 405 }; 406 407 /* 408 * Controls the mPCIE slot WDISABLE pin which is low active 409 * as disable signal. The output-low states, the signal is 410 * inactive, e.g. not disabled 411 */ 412 mpcie_wdisable_hog: mpcie-wdisable-hog { 413 gpio-hog; 414 gpios = <5 GPIO_ACTIVE_LOW>; 415 output-low; 416 line-name = "MPCIE_WDISABLE#"; 417 }; 418 }; 419 420 expander1: gpio@71 { 421 compatible = "nxp,pca9538"; 422 reg = <0x71>; 423 gpio-controller; 424 #gpio-cells = <2>; 425 vcc-supply = <®_3v3>; 426 gpio-line-names = "ENET1_RESET#", "ENET2_RESET#", 427 "USB_RESET#", "", 428 "WLAN_PD#", "WLAN_W_DISABLE#", 429 "WLAN_PERST#", "12V_EN"; 430 431 /* 432 * Controls the WiFi card PD pin which is low active 433 * as power down signal. The output-low states, the signal 434 * is inactive, e.g. not power down 435 */ 436 wlan-pd-hog { 437 gpio-hog; 438 gpios = <4 GPIO_ACTIVE_LOW>; 439 output-low; 440 line-name = "WLAN_PD#"; 441 }; 442 443 /* 444 * Controls the WiFi card disable pin which is low active 445 * as disable signal. The output-low states, the signal 446 * is inactive, e.g. not disabled 447 */ 448 wlan-wdisable-hog { 449 gpio-hog; 450 gpios = <5 GPIO_ACTIVE_LOW>; 451 output-low; 452 line-name = "WLAN_W_DISABLE#"; 453 }; 454 455 /* 456 * Controls the WiFi card reset pin which is low active 457 * as reset signal. The output-low states, the signal 458 * is inactive, e.g. not in reset 459 */ 460 wlan-perst-hog { 461 gpio-hog; 462 gpios = <6 GPIO_ACTIVE_LOW>; 463 output-low; 464 line-name = "WLAN_PERST#"; 465 }; 466 }; 467 468 expander2: gpio@72 { 469 compatible = "nxp,pca9538"; 470 reg = <0x72>; 471 gpio-controller; 472 #gpio-cells = <2>; 473 vcc-supply = <®_3v3>; 474 gpio-line-names = "LCD_RESET#", "LCD_PWR_EN", 475 "LCD_BLT_EN", "LVDS_SHDN#", 476 "FAN_PWR_EN", "", 477 "USER_LED1", "USER_LED2"; 478 }; 479}; 480 481&lpuart1 { 482 pinctrl-names = "default"; 483 pinctrl-0 = <&pinctrl_uart1>; 484 status = "okay"; 485}; 486 487&lpuart2 { 488 pinctrl-names = "default"; 489 pinctrl-0 = <&pinctrl_uart2>; 490 linux,rs485-enabled-at-boot-time; 491 status = "okay"; 492}; 493 494&pcf85063 { 495 /* RTC_EVENT# from SoM is connected on mainboard */ 496 pinctrl-names = "default"; 497 pinctrl-0 = <&pinctrl_pcf85063>; 498 interrupt-parent = <&gpio1>; 499 interrupts = <14 IRQ_TYPE_EDGE_FALLING>; 500}; 501 502&se97_som { 503 /* TEMP_EVENT# from SoM is connected on mainboard */ 504 interrupt-parent = <&expander0>; 505 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 506}; 507 508&tpm2 { 509 pinctrl-names = "default"; 510 pinctrl-0 = <&pinctrl_tpm2>; 511 status = "okay"; 512}; 513 514&usbotg1 { 515 dr_mode = "otg"; 516 hnp-disable; 517 srp-disable; 518 adp-disable; 519 usb-role-switch; 520 disable-over-current; 521 status = "okay"; 522 523 port { 524 typec_hs: endpoint { 525 remote-endpoint = <&typec_con_hs>; 526 }; 527 }; 528}; 529 530&usbotg2 { 531 dr_mode = "host"; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 disable-over-current; 535 status = "okay"; 536 537 hub_2_0: hub@1 { 538 compatible = "usb424,2517"; 539 reg = <1>; 540 reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>; 541 vdd-supply = <®_3v3>; 542 }; 543}; 544 545&usdhc2 { 546 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 547 pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; 548 pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; 549 pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; 550 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 551 vmmc-supply = <®_usdhc2_vmmc>; 552 bus-width = <4>; 553 no-sdio; 554 no-mmc; 555 disable-wp; 556 status = "okay"; 557}; 558 559&iomuxc { 560 pinctrl_eqos: eqosgrp { 561 fsl,pins = /* PD | FSEL_2 | DSE X4 */ 562 <MX91_PAD_ENET1_MDC__ENET1_MDC 0x51e>, 563 /* SION | HYS | FSEL_2 | DSE X4 */ 564 <MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e>, 565 /* HYS | FSEL_0 | DSE no drive */ 566 <MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000>, 567 <MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000>, 568 <MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1000>, 569 <MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1000>, 570 <MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1000>, 571 /* HYS | PD | FSEL_0 | DSE no drive */ 572 <MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x1400>, 573 /* PD | FSEL_2 | DSE X4 */ 574 <MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e>, 575 <MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x51e>, 576 <MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e>, 577 <MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e>, 578 <MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e>, 579 /* PD | FSEL_3 | DSE X3 */ 580 <MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e>; 581 }; 582 583 pinctrl_eqos_phy: eqosphygrp { 584 fsl,pins = /* HYS | FSEL_0 | DSE no drive */ 585 <MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x1000>; 586 }; 587 588 pinctrl_fec: fecgrp { 589 fsl,pins = /* PD | FSEL_2 | DSE X4 */ 590 <MX91_PAD_ENET2_MDC__ENET2_MDC 0x51e>, 591 /* SION | HYS | FSEL_2 | DSE X4 */ 592 <MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x4000111e>, 593 /* HYS | FSEL_0 | DSE no drive */ 594 <MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x1000>, 595 <MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x1000>, 596 <MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x1000>, 597 <MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x1000>, 598 <MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x1000>, 599 /* HYS | PD | FSEL_0 | DSE no drive */ 600 <MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x1400>, 601 /* PD | FSEL_2 | DSE X4 */ 602 <MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x51e>, 603 <MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x51e>, 604 <MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x51e>, 605 <MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x51e>, 606 <MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x51e>, 607 /* PD | FSEL_3 | DSE X3 */ 608 <MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x58e>; 609 }; 610 611 pinctrl_fec_phy: fecphygrp { 612 fsl,pins = /* HYS | FSEL_0 | DSE no drive */ 613 <MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x1000>; 614 }; 615 616 pinctrl_flexcan1: flexcan1grp { 617 fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */ 618 <MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x1200>, 619 /* PU | FSEL_3 | DSE X4 */ 620 <MX91_PAD_PDM_CLK__CAN1_TX 0x039e>; 621 }; 622 623 pinctrl_jtag: jtaggrp { 624 fsl,pins = <MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x051e>, 625 <MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x1200>, 626 <MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x031e>, 627 <MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x1200>; 628 }; 629 630 pinctrl_lpi2c3: lpi2c3grp { 631 fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */ 632 <MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x4000199e>, 633 <MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x4000199e>; 634 }; 635 636 pinctrl_pcf85063: pcf85063grp { 637 fsl,pins = <MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x1000>; 638 }; 639 640 pinctrl_pexp_irq: pexpirqgrp { 641 fsl,pins = /* HYS | FSEL_0 | No DSE */ 642 <MX91_PAD_SAI1_TXC__GPIO1_IO12 0x1000>; 643 }; 644 645 pinctrl_rgbdisp: rgbdispgrp { 646 fsl,pins = <MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e>, 647 <MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e>, 648 <MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e>, 649 <MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e>, 650 <MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x31e>, 651 <MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x31e>, 652 <MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x31e>, 653 <MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x31e>, 654 <MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x31e>, 655 <MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x31e>, 656 <MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x31e>, 657 <MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x31e>, 658 <MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x31e>, 659 <MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x31e>, 660 <MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e>, 661 <MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e>, 662 <MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e>, 663 <MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e>, 664 <MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e>, 665 <MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e>, 666 <MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e>, 667 <MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e>, 668 <MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x31e>, 669 <MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x31e>, 670 <MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x31e>, 671 <MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x31e>, 672 <MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x31e>, 673 <MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x31e>; 674 }; 675 676 pinctrl_touch: touchgrp { 677 fsl,pins = /* HYS | FSEL_0 | No DSE */ 678 <MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x1000>; 679 }; 680 681 pinctrl_tpm2: tpm2grp { 682 fsl,pins = <MX91_PAD_I2C2_SCL__TPM2_CH2 0x57e>; 683 }; 684 685 pinctrl_typec: typecgrp { 686 fsl,pins = /* HYS | FSEL_0 | No DSE */ 687 <MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x1000>; 688 }; 689 690 pinctrl_uart1: uart1grp { 691 fsl,pins = /* HYS | FSEL_0 | No DSE */ 692 <MX91_PAD_UART1_RXD__LPUART1_RX 0x1000>, 693 /* FSEL_2 | DSE X4 */ 694 <MX91_PAD_UART1_TXD__LPUART1_TX 0x011e>; 695 }; 696 697 pinctrl_uart2: uart2grp { 698 fsl,pins = /* HYS | FSEL_0 | No DSE */ 699 <MX91_PAD_UART2_RXD__LPUART2_RX 0x1000>, 700 /* FSEL_2 | DSE X4 */ 701 <MX91_PAD_UART2_TXD__LPUART2_TX 0x011e>, 702 /* FSEL_2 | DSE X4 */ 703 <MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x011e>; 704 }; 705 706 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 707 fsl,pins = /* HYS | FSEL_0 | No DSE */ 708 <MX91_PAD_SD2_CD_B__GPIO3_IO0 0x1000>; 709 }; 710 711 /* enable SION for data and cmd pad due to ERR052021 */ 712 pinctrl_usdhc2_hs: usdhc2hsgrp { 713 fsl,pins = /* PD | FSEL_3 | DSE X5 */ 714 <MX91_PAD_SD2_CLK__USDHC2_CLK 0x05be>, 715 /* HYS | PU | FSEL_3 | DSE X4 */ 716 <MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e>, 717 /* HYS | PU | FSEL_3 | DSE X3 */ 718 <MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e>, 719 <MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e>, 720 <MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e>, 721 <MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e>, 722 /* FSEL_2 | DSE X3 */ 723 <MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e>; 724 }; 725 726 /* enable SION for data and cmd pad due to ERR052021 */ 727 pinctrl_usdhc2_uhs: usdhc2uhsgrp { 728 fsl,pins = /* PD | FSEL_3 | DSE X6 */ 729 <MX91_PAD_SD2_CLK__USDHC2_CLK 0x05fe>, 730 /* HYS | PU | FSEL_3 | DSE X4 */ 731 <MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e>, 732 <MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e>, 733 <MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e>, 734 <MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e>, 735 <MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e>, 736 /* FSEL_2 | DSE X3 */ 737 <MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e>; 738 }; 739}; 740