1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2026 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx91.dtsi" 10 11/ { 12 compatible = "fsl,imx91-9x9-qsb", "fsl,imx91"; 13 model = "NXP i.MX91 9x9 Quick Start Board"; 14 15 aliases { 16 ethernet0 = &fec; 17 ethernet1 = &eqos; 18 gpio0 = &gpio1; 19 gpio1 = &gpio2; 20 gpio2 = &gpio3; 21 i2c0 = &lpi2c1; 22 i2c1 = &lpi2c2; 23 mmc0 = &usdhc1; 24 mmc1 = &usdhc2; 25 rtc0 = &bbnsm_rtc; 26 serial0 = &lpuart1; 27 }; 28 29 chosen { 30 stdout-path = &lpuart1; 31 }; 32 33 wm8524: audio-codec { 34 compatible = "wlf,wm8524"; 35 #sound-dai-cells = <0>; 36 wlf,mute-gpios = <&pcal6524 2 GPIO_ACTIVE_LOW>; 37 38 port { 39 codec_ep: endpoint { 40 remote-endpoint = <&sai1_ep1>; 41 }; 42 }; 43 }; 44 45 dmic: dmic { 46 compatible = "dmic-codec"; 47 #sound-dai-cells = <0>; 48 num-channels = <4>; 49 50 port { 51 dmic_ep: endpoint { 52 remote-endpoint = <&micfil_ep>; 53 }; 54 }; 55 }; 56 57 can_mux: mux-controller-0 { 58 compatible = "gpio-mux"; 59 #mux-control-cells = <0>; 60 #mux-state-cells = <1>; 61 mux-gpios = <&pcal6524 17 GPIO_ACTIVE_HIGH>; 62 }; 63 64 sai1_mux: mux-controller-1 { 65 compatible = "gpio-mux"; 66 #mux-control-cells = <0>; 67 #mux-state-cells = <1>; 68 mux-gpios = <&pcal6524 18 GPIO_ACTIVE_HIGH>; 69 }; 70 71 sai1_en_mux: mux-controller-2 { 72 compatible = "gpio-mux"; 73 #mux-control-cells = <0>; 74 #mux-state-cells = <1>; 75 mux-gpios = <&pcal6524 9 GPIO_ACTIVE_HIGH>; 76 }; 77 78 pinctrl-gpiomux { 79 compatible = "pinctrl-multiplexer"; 80 81 can_fun: can-grp { 82 mux-states = <&can_mux 1>; 83 }; 84 85 m2_fun: m2-grp { 86 mux-states = <&sai1_mux 1>; 87 }; 88 89 pdm_fun: pdm-grp { 90 mux-states = <&can_mux 0>; 91 }; 92 93 sai1_disable: sai1-disable-grp { 94 mux-states = <&sai1_en_mux 1>; 95 }; 96 97 sai1_enable: sai1-enable-grp { 98 mux-states = <&sai1_en_mux 0>; 99 }; 100 101 sai1_fun: sai1-grp { 102 mux-states = <&sai1_mux 0>; 103 }; 104 }; 105 106 reg_vref_1v8: regulator-adc-vref { 107 compatible = "regulator-fixed"; 108 regulator-name = "vref_1v8"; 109 regulator-max-microvolt = <1800000>; 110 regulator-min-microvolt = <1800000>; 111 }; 112 113 reg_usdhc2_vmmc: regulator-usdhc2 { 114 compatible = "regulator-fixed"; 115 regulator-name = "VSD_3V3"; 116 off-on-delay-us = <12000>; 117 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 118 pinctrl-names = "default"; 119 regulator-max-microvolt = <3300000>; 120 regulator-min-microvolt = <3300000>; 121 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 122 enable-active-high; 123 }; 124 125 reserved-memory { 126 ranges; 127 #address-cells = <2>; 128 #size-cells = <2>; 129 130 linux,cma { 131 compatible = "shared-dma-pool"; 132 reusable; 133 size = <0 0x10000000>; 134 linux,cma-default; 135 }; 136 }; 137 138 sound-micfil { 139 compatible = "audio-graph-card2"; 140 label = "micfil-audio"; 141 links = <&micfil_port>; 142 }; 143 144 sound-wm8524 { 145 compatible = "audio-graph-card2"; 146 label = "wm8524-audio"; 147 links = <&sai1_port1>; 148 widgets = "Line", "Line Out Jack"; 149 routing = 150 "Line Out Jack", "LINEVOUTL", 151 "Line Out Jack", "LINEVOUTR"; 152 }; 153}; 154 155&adc1 { 156 vref-supply = <®_vref_1v8>; 157 status = "okay"; 158}; 159 160&eqos { 161 phy-handle = <ðphy1>; 162 phy-mode = "rgmii-id"; 163 pinctrl-0 = <&pinctrl_eqos>; 164 pinctrl-names = "default"; 165 status = "okay"; 166 167 mdio { 168 compatible = "snps,dwmac-mdio"; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 172 ethphy1: ethernet-phy@1 { 173 compatible = "ethernet-phy-ieee802.3-c22"; 174 reg = <1>; 175 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; 176 reset-assert-us = <10000>; 177 reset-deassert-us = <80000>; 178 realtek,clkout-disable; 179 }; 180 }; 181}; 182 183&iomuxc { 184 pinctrl_eqos: eqosgrp { 185 fsl,pins = < 186 MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e 187 MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 188 MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 189 MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 190 MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 191 MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 192 MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe 193 MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 194 MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 195 MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e 196 MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 197 MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 198 MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe 199 MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 200 >; 201 }; 202 203 pinctrl_lpi2c1: lpi2c1grp { 204 fsl,pins = < 205 MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 206 MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 207 >; 208 }; 209 210 pinctrl_lpi2c2: lpi2c2grp { 211 fsl,pins = < 212 MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 213 MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 214 >; 215 }; 216 217 pinctrl_pcal6524: pcal6524grp { 218 fsl,pins = < 219 MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e 220 >; 221 }; 222 223 pinctrl_pdm: pdmgrp { 224 fsl,pins = < 225 MX91_PAD_PDM_CLK__PDM_CLK 0x31e 226 MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e 227 MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e 228 >; 229 }; 230 231 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 232 fsl,pins = < 233 MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e 234 >; 235 }; 236 237 pinctrl_sai1: sai1grp { 238 fsl,pins = < 239 MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e 240 MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e 241 MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e 242 MX91_PAD_SAI1_RXD0__SAI1_MCLK 0x31e 243 >; 244 }; 245 246 pinctrl_uart1: uart1grp { 247 fsl,pins = < 248 MX91_PAD_UART1_RXD__LPUART1_RX 0x31e 249 MX91_PAD_UART1_TXD__LPUART1_TX 0x31e 250 >; 251 }; 252 253 pinctrl_usdhc1: usdhc1grp { 254 fsl,pins = < 255 MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 256 MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 257 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 258 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 259 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 260 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 261 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 262 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 263 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 264 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 265 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 266 >; 267 }; 268 269 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 270 fsl,pins = < 271 MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e 272 MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e 273 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 274 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 275 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 276 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 277 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 278 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 279 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 280 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 281 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 282 >; 283 }; 284 285 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 286 fsl,pins = < 287 MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe 288 MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe 289 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 290 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 291 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 292 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 293 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 294 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 295 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 296 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 297 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 298 >; 299 }; 300 301 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 302 fsl,pins = < 303 MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e 304 >; 305 }; 306 307 pinctrl_usdhc2: usdhc2grp { 308 fsl,pins = < 309 MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 310 MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 311 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 312 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 313 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 314 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 315 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 316 >; 317 }; 318 319 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 320 fsl,pins = < 321 MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e 322 MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e 323 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 324 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 325 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 326 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 327 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 328 >; 329 }; 330 331 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 332 fsl,pins = < 333 MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe 334 MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe 335 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 336 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 337 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 338 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 339 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 340 >; 341 }; 342 343 pinctrl_wdog: wdoggrp { 344 fsl,pins = < 345 MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 346 >; 347 }; 348}; 349 350&lpi2c1 { 351 clock-frequency = <400000>; 352 pinctrl-0 = <&pinctrl_lpi2c1>; 353 pinctrl-names = "default"; 354 status = "okay"; 355 356 p3t1085: temperature-sensor@48 { 357 compatible = "nxp,p3t1085"; 358 reg = <0x48>; 359 }; 360 361 ptn5110: tcpc@50 { 362 compatible = "nxp,ptn5110", "tcpci"; 363 reg = <0x50>; 364 interrupt-parent = <&gpio3>; 365 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 366 367 typec1_con: connector { 368 compatible = "usb-c-connector"; 369 data-role = "dual"; 370 label = "USB-C"; 371 op-sink-microwatt = <15000000>; 372 power-role = "dual"; 373 self-powered; 374 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 375 PDO_VAR(5000, 20000, 3000)>; 376 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 377 try-power-role = "sink"; 378 379 ports { 380 #address-cells = <1>; 381 #size-cells = <0>; 382 383 port@0 { 384 reg = <0>; 385 typec1_dr_sw: endpoint { 386 remote-endpoint = <&usb1_drd_sw>; 387 }; 388 }; 389 }; 390 }; 391 }; 392 393 pcf2131: rtc@53 { 394 compatible = "nxp,pcf2131"; 395 reg = <0x53>; 396 interrupt-parent = <&pcal6524>; 397 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 398 }; 399}; 400 401&lpi2c2 { 402 clock-frequency = <400000>; 403 pinctrl-0 = <&pinctrl_lpi2c2>; 404 pinctrl-names = "default"; 405 status = "okay"; 406 407 pcal6524: gpio@22 { 408 compatible = "nxp,pcal6524"; 409 reg = <0x22>; 410 #interrupt-cells = <2>; 411 interrupt-controller; 412 interrupt-parent = <&gpio3>; 413 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 414 #gpio-cells = <2>; 415 gpio-controller; 416 pinctrl-0 = <&pinctrl_pcal6524>; 417 pinctrl-names = "default"; 418 }; 419 420 pmic@32 { 421 compatible = "nxp,pf9453"; 422 reg = <0x32>; 423 interrupt-parent = <&pcal6524>; 424 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 425 426 regulators { 427 buck1: BUCK1 { 428 regulator-name = "BUCK1"; 429 regulator-always-on; 430 regulator-boot-on; 431 regulator-max-microvolt = <1140000>; 432 regulator-min-microvolt = <1060000>; 433 }; 434 435 buck2: BUCK2 { 436 regulator-name = "BUCK2"; 437 regulator-always-on; 438 regulator-boot-on; 439 regulator-max-microvolt = <900000>; 440 regulator-min-microvolt = <610000>; 441 regulator-ramp-delay = <12500>; 442 }; 443 444 buck3: BUCK3 { 445 regulator-name = "BUCK3"; 446 regulator-always-on; 447 regulator-boot-on; 448 regulator-max-microvolt = <3450000>; 449 regulator-min-microvolt = <1650000>; 450 }; 451 452 buck4: BUCK4 { 453 regulator-name = "BUCK4"; 454 regulator-always-on; 455 regulator-boot-on; 456 regulator-max-microvolt = <3450000>; 457 regulator-min-microvolt = <1650000>; 458 }; 459 460 ldo1: LDO1 { 461 regulator-name = "LDO1"; 462 regulator-always-on; 463 regulator-boot-on; 464 regulator-max-microvolt = <3300000>; 465 regulator-min-microvolt = <1650000>; 466 }; 467 468 ldo2: LDO2 { 469 regulator-name = "LDO2"; 470 regulator-always-on; 471 regulator-boot-on; 472 regulator-max-microvolt = <1890000>; 473 regulator-min-microvolt = <760000>; 474 }; 475 476 ldo_snvs: LDO-SNVS { 477 regulator-name = "LDO-SNVS"; 478 regulator-always-on; 479 regulator-boot-on; 480 regulator-max-microvolt = <1950000>; 481 regulator-min-microvolt = <1650000>; 482 }; 483 }; 484 }; 485}; 486 487&lpuart1 { 488 pinctrl-0 = <&pinctrl_uart1>; 489 pinctrl-names = "default"; 490 status = "okay"; 491}; 492 493&micfil { 494 #sound-dai-cells = <0>; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&pinctrl_pdm>, <&pdm_fun>; 497 assigned-clocks = <&clk IMX93_CLK_PDM>; 498 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 499 assigned-clock-rates = <49152000>; 500 status = "okay"; 501 502 micfil_port: port { 503 capture-only; 504 505 micfil_ep: endpoint { 506 remote-endpoint = <&dmic_ep>; 507 }; 508 }; 509}; 510 511&sai1 { 512 #sound-dai-cells = <0>; 513 pinctrl-names = "default"; 514 pinctrl-0 = <&pinctrl_sai1>, <&sai1_fun>, <&sai1_enable>; 515 assigned-clocks = <&clk IMX93_CLK_SAI1>; 516 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 517 assigned-clock-rates = <24576000>; 518 clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, 519 <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, 520 <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; 521 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; 522 fsl,sai-mclk-direction-output; 523 status = "okay"; 524 525 ports { 526 #address-cells = <1>; 527 #size-cells = <0>; 528 529 sai1_port1: port@1 { 530 reg = <1>; 531 playback-only; 532 533 sai1_ep1: endpoint { 534 dai-format = "i2s"; 535 dai-tdm-slot-num = <2>; 536 dai-tdm-slot-width = <32>; 537 bitclock-master; 538 frame-master; 539 mclk-fs = <256>; 540 system-clock-direction-out; 541 remote-endpoint = <&codec_ep>; 542 }; 543 }; 544 }; 545}; 546 547&usbotg1 { 548 adp-disable; 549 disable-over-current; 550 dr_mode = "otg"; 551 hnp-disable; 552 srp-disable; 553 usb-role-switch; 554 samsung,picophy-dc-vol-level-adjust = <7>; 555 samsung,picophy-pre-emp-curr-control = <3>; 556 status = "okay"; 557 558 port { 559 usb1_drd_sw: endpoint { 560 remote-endpoint = <&typec1_dr_sw>; 561 }; 562 }; 563}; 564 565&usdhc1 { 566 bus-width = <8>; 567 non-removable; 568 pinctrl-0 = <&pinctrl_usdhc1>; 569 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 570 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 571 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 572 fsl,tuning-step = <1>; 573 status = "okay"; 574}; 575 576&usdhc2 { 577 bus-width = <4>; 578 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 579 no-mmc; 580 no-sdio; 581 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 582 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 583 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 584 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 585 vmmc-supply = <®_usdhc2_vmmc>; 586 fsl,tuning-step = <1>; 587 status = "okay"; 588}; 589 590&wdog3 { 591 pinctrl-names = "default"; 592 pinctrl-0 = <&pinctrl_wdog>; 593 fsl,ext-reset-output; 594 status = "okay"; 595}; 596