1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Common dtsi for Variscite VAR-SOM-MX8 4 * 5 * Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8-quadmax-quadplus/var-som-mx8/ 6 * 7 * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11/dts-v1/; 12 13#include "imx8qm.dtsi" 14 15/ { 16 model = "Variscite i.MX8QM VAR-SOM-MX8 Module"; 17 compatible = "variscite,var-som-imx8qm", "fsl,imx8qm"; 18 19 memory@80000000 { 20 device_type = "memory"; 21 reg = <0x00000000 0x80000000 0 0x40000000>; 22 }; 23 24 reg_audio_supply: regulator-1p8v { 25 compatible = "regulator-fixed"; 26 regulator-name = "wm8904-supply"; 27 regulator-min-microvolt = <1800000>; 28 regulator-max-microvolt = <1800000>; 29 regulator-always-on; 30 }; 31 32 reg_phy_vddio: regulator-phy-vddio { 33 compatible = "regulator-fixed"; 34 regulator-name = "vddio-1v8"; 35 regulator-min-microvolt = <1800000>; 36 regulator-max-microvolt = <1800000>; 37 }; 38 39 reserved-memory { 40 #address-cells = <2>; 41 #size-cells = <2>; 42 ranges; 43 44 vdev0vring0: memory@90000000 { 45 reg = <0 0x90000000 0 0x8000>; 46 no-map; 47 }; 48 49 vdev0vring1: memory@90008000 { 50 reg = <0 0x90008000 0 0x8000>; 51 no-map; 52 }; 53 54 vdev1vring0: memory@90010000 { 55 reg = <0 0x90010000 0 0x8000>; 56 no-map; 57 }; 58 59 vdev1vring1: memory@90018000 { 60 reg = <0 0x90018000 0 0x8000>; 61 no-map; 62 }; 63 64 rsc_table0: memory@900ff000 { 65 reg = <0 0x900ff000 0 0x1000>; 66 no-map; 67 }; 68 69 vdev2vring0: memory@90100000 { 70 reg = <0 0x90100000 0 0x8000>; 71 no-map; 72 }; 73 74 vdev2vring1: memory@90108000 { 75 reg = <0 0x90108000 0 0x8000>; 76 no-map; 77 }; 78 79 vdev3vring0: memory@90110000 { 80 reg = <0 0x90110000 0 0x8000>; 81 no-map; 82 }; 83 84 vdev3vring1: memory@90118000 { 85 reg = <0 0x90118000 0 0x8000>; 86 no-map; 87 }; 88 89 rsc_table1: memory@901ff000 { 90 reg = <0 0x901ff000 0 0x1000>; 91 no-map; 92 }; 93 94 vdevbuffer: memory@90400000 { 95 compatible = "shared-dma-pool"; 96 reg = <0 0x90400000 0 0x100000>; 97 no-map; 98 }; 99 100 dsp_reserved: memory@92400000 { 101 reg = <0 0x92400000 0 0x1000000>; 102 no-map; 103 }; 104 105 dsp_vdev0vring0: memory@942f0000 { 106 reg = <0 0x942f0000 0 0x8000>; 107 no-map; 108 }; 109 110 dsp_vdev0vring1: memory@942f8000 { 111 reg = <0 0x942f8000 0 0x8000>; 112 no-map; 113 }; 114 115 dsp_vdev0buffer: memory@94300000 { 116 compatible = "shared-dma-pool"; 117 reg = <0 0x94300000 0 0x100000>; 118 no-map; 119 }; 120 121 /* global autoconfigured region for contiguous allocations */ 122 linux,cma { 123 compatible = "shared-dma-pool"; 124 /* VAR-SOM-MX8QM doesn't have 1GB variant */ 125 alloc-ranges = <0 0xc0000000 0 0x3c000000>; 126 size = <0 0x3c000000>; 127 linux,cma-default; 128 reusable; 129 }; 130 }; 131 132 sound-wm8904 { 133 compatible = "simple-audio-card"; 134 simple-audio-card,bitclock-master = <&codec_dai>; 135 simple-audio-card,format = "i2s"; 136 simple-audio-card,frame-master = <&codec_dai>; 137 simple-audio-card,mclk-fs = <256>; 138 simple-audio-card,name = "wm8904-audio"; 139 simple-audio-card,routing = 140 "Headphone Jack", "HPOUTL", 141 "Headphone Jack", "HPOUTR", 142 "IN2L", "Line In Jack", 143 "IN2R", "Line In Jack", 144 "IN1L", "Microphone Jack", 145 "IN1R", "Microphone Jack"; 146 simple-audio-card,widgets = 147 "Microphone", "Microphone Jack", 148 "Headphone", "Headphone Jack", 149 "Line", "Line In Jack"; 150 151 codec_dai: simple-audio-card,codec { 152 sound-dai = <&wm8904>; 153 }; 154 155 simple-audio-card,cpu { 156 sound-dai = <&esai0>; 157 }; 158 }; 159}; 160 161&acm { 162 status = "okay"; 163}; 164 165&asrc0 { 166 fsl,asrc-rate = <48000>; 167 status = "okay"; 168}; 169 170&asrc1 { 171 fsl,asrc-rate = <48000>; 172 status = "okay"; 173}; 174 175&cm41_intmux { 176 status = "okay"; 177}; 178 179&esai0 { 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_esai0>; 182 assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, 183 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 184 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 185 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 186 <&esai0_lpcg IMX_LPCG_CLK_4>; 187 assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>; 188 assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; 189 #sound-dai-cells = <0>; 190 status = "okay"; 191}; 192 193&fec1 { 194 pinctrl-names = "default"; 195 pinctrl-0 = <&pinctrl_fec1>; 196 /* 197 * The required RGMII TX and RX 2ns delays are implemented directly 198 * in hardware via passive delay elements on the SOM PCB. 199 * No delay configuration is needed in software via PHY driver. 200 */ 201 phy-mode = "rgmii"; 202 phy-handle = <ðphy0>; 203 status = "okay"; 204 205 mdio { 206 #address-cells = <1>; 207 #size-cells = <0>; 208 209 ethphy0: ethernet-phy@4 { 210 compatible = "ethernet-phy-ieee802.3-c22"; 211 reg = <4>; 212 reset-gpios = <&lsio_gpio2 28 GPIO_ACTIVE_LOW>; 213 reset-assert-us = <10000>; 214 reset-deassert-us = <20000>; 215 vddio-supply = <®_phy_vddio>; 216 }; 217 }; 218}; 219 220&gpio0_mipi_csi0 { 221 status = "disabled"; 222}; 223 224&gpio0_mipi_csi1 { 225 status = "disabled"; 226}; 227 228&i2c0 { 229 clock-frequency = <100000>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_i2c0>; 232 status = "okay"; 233 234 wm8904: codec@1a { 235 compatible = "wlf,wm8904"; 236 reg = <0x1a>; 237 #sound-dai-cells = <0>; 238 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 239 clock-names = "mclk"; 240 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 241 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 242 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 243 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 244 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; 245 AVDD-supply = <®_audio_supply>; 246 CPVDD-supply = <®_audio_supply>; 247 DBVDD-supply = <®_audio_supply>; 248 DCVDD-supply = <®_audio_supply>; 249 MICVDD-supply = <®_audio_supply>; 250 wlf,drc-cfg-names = "default", "peaklimiter", "tradition", 251 "soft", "music"; 252 /* 253 * Config registers per name, respectively: 254 * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 255 * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 256 * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 257 * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 258 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 259 */ 260 wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, 261 /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, 262 /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, 263 /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, 264 /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; 265 /* GPIO1 = DMIC_CLK, don't touch others */ 266 wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; 267 }; 268}; 269 270/* Bluetooth */ 271&lpuart1 { 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pinctrl_lpuart1>; 274 uart-has-rtscts; 275 status = "okay"; 276}; 277 278&mu_m0{ 279 status = "okay"; 280}; 281 282&mu1_m0{ 283 status = "okay"; 284}; 285 286&mu2_m0{ 287 status = "okay"; 288}; 289 290&rtc { 291 status = "disabled"; 292}; 293 294&sai6 { 295 assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, 296 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 297 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 298 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 299 <&sai6_lpcg IMX_LPCG_CLK_4>; 300 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 301 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 302 fsl,sai-asynchronous; 303 status = "okay"; 304}; 305 306&sai7 { 307 assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, 308 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 309 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 310 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 311 <&sai7_lpcg IMX_LPCG_CLK_4>; 312 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 313 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 314 fsl,sai-asynchronous; 315 status = "okay"; 316}; 317 318&thermal_zones { 319 pmic-thermal { 320 polling-delay-passive = <250>; 321 polling-delay = <2000>; 322 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; 323 trips { 324 pmic_alert0: trip0 { 325 temperature = <110000>; 326 hysteresis = <2000>; 327 type = "passive"; 328 }; 329 pmic_crit0: trip1 { 330 temperature = <125000>; 331 hysteresis = <2000>; 332 type = "critical"; 333 }; 334 }; 335 cooling-maps { 336 map0 { 337 trip = <&pmic_alert0>; 338 cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 339 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 340 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 341 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 342 }; 343 }; 344 }; 345}; 346 347/* eMMC */ 348&usdhc1 { 349 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 350 pinctrl-0 = <&pinctrl_usdhc1>; 351 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 352 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 353 bus-width = <8>; 354 non-removable; 355 status = "okay"; 356}; 357 358/* WIFI */ 359&usdhc3 { 360 #address-cells = <1>; 361 #size-cells = <0>; 362 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 363 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi>; 364 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi>; 365 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi>; 366 bus-width = <4>; 367 non-removable; 368 status = "okay"; 369 370 brcmf: wifi@1 { 371 compatible = "brcm,bcm4329-fmac"; 372 reg = <1>; 373 }; 374}; 375 376&iomuxc { 377 pinctrl-names = "default"; 378 pinctrl-0 = <&pinctrl_hog>; 379 380 pinctrl_esai0: esai0grp { 381 fsl,pins = < 382 IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 383 IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 384 IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 385 IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 386 IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 387 IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 388 IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc600004c 389 >; 390 }; 391 392 pinctrl_fec1: fec1grp { 393 fsl,pins = < 394 IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000048 395 IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 396 IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 397 IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 398 IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 399 IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 400 IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 401 IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 402 IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 403 IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 404 IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 405 IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 406 IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 407 IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 408 IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x06000028 409 >; 410 }; 411 412 pinctrl_hog: hoggrp { 413 fsl,pins = < 414 IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000041 415 IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 0x00000041 416 IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06 0x00000041 417 IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000041 418 IMX8QM_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 0x00000041 419 >; 420 }; 421 422 pinctrl_i2c0: i2c0grp { 423 fsl,pins = < 424 IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc6000020 425 IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc6000020 426 >; 427 }; 428 429 pinctrl_lpuart1: lpuart1grp { 430 fsl,pins = < 431 IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 432 IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 433 IMX8QM_UART1_CTS_B_DMA_UART1_RTS_B 0x06000020 434 IMX8QM_UART1_RTS_B_DMA_UART1_CTS_B 0x06000020 435 >; 436 }; 437 438 pinctrl_usdhc1: usdhc1grp { 439 fsl,pins = < 440 IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 441 IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 442 IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 443 IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 444 IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 445 IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 446 IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 447 IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 448 IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 449 IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 450 IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 451 IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 452 >; 453 }; 454 455 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 456 fsl,pins = < 457 IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 458 IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 459 IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 460 IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 461 IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 462 IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 463 IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 464 IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 465 IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 466 IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 467 IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 468 IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 469 >; 470 }; 471 472 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 473 fsl,pins = < 474 IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 475 IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 476 IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 477 IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 478 IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 479 IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 480 IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 481 IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 482 IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 483 IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 484 IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 485 IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 486 >; 487 }; 488 489 pinctrl_usdhc3: usdhc3grp { 490 fsl,pins = < 491 IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 492 IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 493 IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 494 IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 495 IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 496 IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 497 >; 498 }; 499 500 pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { 501 fsl,pins = < 502 IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 503 IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 504 IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 505 IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 506 IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 507 IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 508 >; 509 }; 510 511 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 512 fsl,pins = < 513 IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 514 IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 515 IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 516 IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 517 IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 518 IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 519 >; 520 }; 521 522 pinctrl_wifi: wifigrp { 523 fsl,pins = < 524 /* GPIOs used by user space WiFi init */ 525 IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0xc600004c 526 IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x06000021 527 IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 0x00000021 528 IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 529 >; 530 }; 531}; 532