1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Variscite Symphony carrier board for VAR-SOM-MX8 QuadMax 4 * 5 * Link: https://variscite.com/carrier-boards/symphony-board/ 6 * 7 * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11/dts-v1/; 12 13#include <dt-bindings/input/input.h> 14#include <dt-bindings/leds/common.h> 15#include "imx8qm-var-som.dtsi" 16 17/ { 18 model = "Variscite VAR-SOM-MX8 on Symphony evaluation board"; 19 compatible = "variscite,var-som-imx8qm-symphony", 20 "variscite,var-som-imx8qm", "fsl,imx8qm"; 21 chosen { 22 stdout-path = &lpuart0; 23 }; 24 25 gpio-keys { 26 compatible = "gpio-keys"; 27 28 button-back { 29 label = "Back"; 30 gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; 31 linux,code = <KEY_BACK>; 32 }; 33 34 button-home { 35 label = "Home"; 36 gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; 37 linux,code = <KEY_HOME>; 38 }; 39 40 button-menu { 41 label = "Menu"; 42 gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; 43 linux,code = <KEY_MENU>; 44 }; 45 }; 46 47 gpio-leds { 48 compatible = "gpio-leds"; 49 50 led-heartbeat { 51 function = LED_FUNCTION_STATUS; 52 color = <LED_COLOR_ID_GREEN>; 53 gpios = <&pca9534 0 GPIO_ACTIVE_LOW>; 54 linux,default-trigger = "heartbeat"; 55 }; 56 }; 57 58 reg_fec_phy: regulator-fec-phy { 59 compatible = "regulator-fixed"; 60 regulator-name = "fec-phy"; 61 regulator-min-microvolt = <1800000>; 62 regulator-max-microvolt = <1800000>; 63 regulator-enable-ramp-delay = <20000>; 64 vin-supply = <®_vselect>; 65 gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; 66 enable-active-high; 67 }; 68 69 reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 70 compatible = "regulator-fixed"; 71 regulator-name = "usb_otg1_vbus"; 72 regulator-min-microvolt = <5000000>; 73 regulator-max-microvolt = <5000000>; 74 gpio = <&lsio_gpio0 18 GPIO_ACTIVE_HIGH>; 75 enable-active-high; 76 }; 77 78 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 79 compatible = "regulator-fixed"; 80 regulator-name = "sw-3p3-sd1"; 81 regulator-min-microvolt = <3300000>; 82 regulator-max-microvolt = <3300000>; 83 regulator-always-on; 84 }; 85 86 reg_vselect: regulator-vselect { 87 compatible = "regulator-fixed"; 88 regulator-name = "reg_vselect"; 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 regulator-always-on; 92 gpio = <&pca9534 6 GPIO_ACTIVE_HIGH>; 93 enable-active-high; 94 }; 95}; 96 97ðphy0 { 98 leds { 99 #address-cells = <1>; 100 #size-cells = <0>; 101 102 led@0 { 103 reg = <0>; 104 color = <LED_COLOR_ID_YELLOW>; 105 function = LED_FUNCTION_LAN; 106 linux,default-trigger = "netdev"; 107 }; 108 109 led@1 { 110 reg = <1>; 111 color = <LED_COLOR_ID_GREEN>; 112 function = LED_FUNCTION_LAN; 113 linux,default-trigger = "netdev"; 114 }; 115 }; 116}; 117 118&fec1 { 119 mdio { 120 ethphy1: ethernet-phy@5 { 121 compatible = "ethernet-phy-ieee802.3-c22"; 122 reg = <5>; 123 vddio-supply = <®_phy_vddio>; 124 reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; 125 reset-assert-us = <10000>; 126 reset-deassert-us = <100000>; 127 128 leds { 129 #address-cells = <1>; 130 #size-cells = <0>; 131 132 led@0 { 133 reg = <0>; 134 color = <LED_COLOR_ID_YELLOW>; 135 function = LED_FUNCTION_LAN; 136 linux,default-trigger = "netdev"; 137 }; 138 139 led@1 { 140 reg = <1>; 141 color = <LED_COLOR_ID_GREEN>; 142 function = LED_FUNCTION_LAN; 143 linux,default-trigger = "netdev"; 144 }; 145 }; 146 }; 147 }; 148}; 149 150&fec2 { 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_fec2>; 153 /* 154 * The required RGMII TX and RX 2ns delays are implemented directly 155 * in hardware via passive delay elements on the SOM PCB. 156 * No delay configuration is needed in software via PHY driver. 157 */ 158 phy-mode = "rgmii"; 159 phy-handle = <ðphy1>; 160 phy-supply = <®_fec_phy>; 161 status = "okay"; 162}; 163 164&flexcan1 { 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_flexcan1>; 167 status = "okay"; 168}; 169 170&flexcan2 { 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pinctrl_flexcan2>; 173 status = "okay"; 174}; 175 176&hsio_phy { 177 fsl,hsio-cfg = "pciea-pcieb-sata"; 178 fsl,refclk-pad-mode = "input"; 179 status = "okay"; 180}; 181 182&i2c1 { 183 clock-frequency = <100000>; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_i2c1>; 186 status = "okay"; 187 188 pca9534: gpio@20 { 189 compatible = "nxp,pca9534"; 190 reg = <0x20>; 191 gpio-controller; 192 #gpio-cells = <2>; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&pinctrl_pca9534>; 195 interrupt-parent = <&lsio_gpio1>; 196 interrupts = <24 IRQ_TYPE_LEVEL_LOW>; 197 }; 198 199 /* USB Type-C Controller */ 200 typec_ptn5150: typec@3d { 201 compatible = "nxp,ptn5150"; 202 reg = <0x3d>; 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_ptn5150>; 205 interrupt-parent = <&lsio_gpio3>; 206 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 207 208 port { 209 typec_dr_sw: endpoint { 210 remote-endpoint = <&usb3_drd_sw>; 211 }; 212 }; 213 }; 214}; 215 216&i2c4 { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 clock-frequency = <100000>; 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pinctrl_i2c4>; 222 status = "okay"; 223 224 pca6408: gpio@21 { 225 compatible = "nxp,pcal6408"; 226 reg = <0x21>; 227 gpio-controller; 228 #gpio-cells = <2>; 229 230 /* RGB_SEL */ 231 lvds-brg-enable-hog { 232 gpio-hog; 233 gpios = <7 GPIO_ACTIVE_HIGH>; 234 output-low; 235 line-name = "lvds_brg_en"; 236 }; 237 }; 238 239 st33ktpm2xi2c: tpm@2e { 240 compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; 241 reg = <0x2e>; 242 label = "tpm"; 243 reset-gpios = <&pca6408 4 GPIO_ACTIVE_LOW>; 244 }; 245 246 /* Capacitive touch */ 247 ft5x06_ts: touchscreen@38 { 248 compatible = "edt,edt-ft5406"; 249 pinctrl-names = "default"; 250 reg = <0x38>; 251 pinctrl-0 = <&pinctrl_captouch>; 252 interrupt-parent = <&lsio_gpio0>; 253 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 254 touchscreen-size-x = <800>; 255 touchscreen-size-y = <480>; 256 touchscreen-inverted-x; 257 touchscreen-inverted-y; 258 wakeup-source; 259 }; 260 261 rtc@68 { 262 compatible = "dallas,ds1337"; 263 reg = <0x68>; 264 }; 265}; 266 267&lpspi1 { 268 #address-cells = <1>; 269 #size-cells = <0>; 270 pinctrl-names = "default"; 271 pinctrl-0 = <&pinctrl_lpspi1>; 272 cs-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>; 273 status = "okay"; 274}; 275 276/* console */ 277&lpuart0 { 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_lpuart0>; 280 status = "okay"; 281}; 282 283/* header */ 284&lpuart2 { 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_lpuart2>; 287 status = "okay"; 288}; 289 290/* header */ 291&lpuart4 { 292 pinctrl-names = "default"; 293 pinctrl-0 = <&pinctrl_lpuart4>; 294 status = "okay"; 295}; 296 297&pca9534 { 298 usb3-signal-route-hog { 299 gpio-hog; 300 gpios = <4 GPIO_ACTIVE_HIGH>; 301 output-low; 302 line-name = "usb3_signal_route"; 303 }; 304}; 305 306&pciea{ 307 phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; 308 phy-names = "pcie-phy"; 309 status = "okay"; 310}; 311 312&pciea_port0 { 313 reset-gpios = <&pca6408 1 GPIO_ACTIVE_LOW>; 314}; 315 316&usb3_phy { 317 status = "okay"; 318}; 319 320&usbotg1 { 321 dr_mode = "host"; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_usbotg1>; 324 vbus-supply = <®_usb_otg1_vbus>; 325 srp-disable; 326 hnp-disable; 327 adp-disable; 328 disable-over-current; 329 status = "okay"; 330}; 331 332&usbotg3 { 333 status = "okay"; 334}; 335 336&usbotg3_cdns3 { 337 dr_mode = "otg"; 338 usb-role-switch; 339 status = "okay"; 340 341 port { 342 usb3_drd_sw: endpoint { 343 remote-endpoint = <&typec_dr_sw>; 344 }; 345 }; 346}; 347 348&usbphy1 { 349 status = "okay"; 350}; 351 352&usdhc2 { 353 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 354 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 355 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 356 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 357 bus-width = <4>; 358 cd-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_LOW>; 359 vmmc-supply = <®_usdhc2_vmmc>; 360 status = "okay"; 361}; 362 363&iomuxc { 364 pinctrl_captouch: captouchgrp { 365 fsl,pins = < 366 IMX8QM_GPT1_COMPARE_LSIO_GPIO0_IO19 0x06000021 367 >; 368 }; 369 370 pinctrl_fec2: fec2grp { 371 fsl,pins = < 372 IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000048 373 IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000048 374 IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000048 375 IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000048 376 IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000048 377 IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000048 378 IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000048 379 IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000048 380 IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000048 381 IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000048 382 IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000048 383 IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000048 384 >; 385 }; 386 387 pinctrl_flexcan1: flexcan0grp { 388 fsl,pins = < 389 IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x00000021 390 IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x00000021 391 >; 392 }; 393 394 pinctrl_flexcan2: flexcan1grp { 395 fsl,pins = < 396 IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x00000021 397 IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x00000021 398 >; 399 }; 400 401 pinctrl_i2c1: i2c1grp { 402 fsl,pins = < 403 IMX8QM_USB_SS3_TC3_DMA_I2C1_SDA 0xc6000020 404 IMX8QM_USB_SS3_TC1_DMA_I2C1_SCL 0xc6000020 405 >; 406 }; 407 408 pinctrl_i2c4: i2c4grp { 409 fsl,pins = < 410 IMX8QM_ENET1_MDC_DMA_I2C4_SCL 0xc6000020 411 IMX8QM_ENET1_MDIO_DMA_I2C4_SDA 0xc6000020 412 >; 413 }; 414 415 pinctrl_lpspi1: lpspi1grp { 416 fsl,pins = < 417 IMX8QM_ADC_IN3_DMA_SPI1_SCK 0x0600004c 418 IMX8QM_ADC_IN4_DMA_SPI1_SDO 0x0600004c 419 IMX8QM_ADC_IN5_DMA_SPI1_SDI 0x0600004c 420 IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 0x00000021 421 >; 422 }; 423 424 pinctrl_lpuart0: lpuart0grp { 425 fsl,pins = < 426 IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 427 IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 428 >; 429 }; 430 431 pinctrl_lpuart2: lpuart2grp { 432 fsl,pins = < 433 IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020 434 IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020 435 >; 436 }; 437 438 pinctrl_lpuart4: lpuart4grp { 439 fsl,pins = < 440 IMX8QM_M40_GPIO0_01_DMA_UART4_TX 0x06000020 441 IMX8QM_M40_GPIO0_00_DMA_UART4_RX 0x06000020 442 >; 443 }; 444 445 pinctrl_pca9534: pca9534grp { 446 fsl,pins = < 447 IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 0x00000021 448 >; 449 }; 450 451 pinctrl_ptn5150: ptn5150grp { 452 fsl,pins = < 453 IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021 454 >; 455 }; 456 457 pinctrl_usbotg1: otg1grp { 458 fsl,pins = < 459 IMX8QM_GPT1_CAPTURE_LSIO_GPIO0_IO18 0x06000048 460 >; 461 }; 462 463 pinctrl_usdhc2: usdhc2grp { 464 fsl,pins = < 465 IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 466 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 467 IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 468 IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 469 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 470 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 471 IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 472 >; 473 }; 474 475 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 476 fsl,pins = < 477 IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 478 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 479 IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 480 IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 481 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 482 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 483 IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 484 >; 485 }; 486 487 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 488 fsl,pins = < 489 IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 490 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 491 IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 492 IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 493 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 494 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 495 IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 496 >; 497 }; 498 499 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 500 fsl,pins = < 501 IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0x00000021 502 >; 503 }; 504}; 505