xref: /linux/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi (revision b2128290c29902315e632ea59e0504d6bc9e9b42) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2/*
3 * Copyright (c) 2019-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Alexander Stein
6 */
7
8#include <dt-bindings/firmware/imx/rsrc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/thermal/thermal.h>
11
12#include "imx8qm.dtsi"
13
14/ {
15	model = "TQ-Systems i.MX8QM TQMa8QM";
16	compatible = "tq,imx8qm-tqma8qm", "fsl,imx8qm";
17
18	/* Due to missing workaround for ERR050104 */
19	cpus {
20		/delete-node/ cpu-map;
21		/delete-node/ cpu@100;
22		/delete-node/ cpu@101;
23	};
24
25	memory@80000000 {
26		device_type = "memory";
27		/*
28		 * DRAM base addr, size : 1024 MiB DRAM
29		 * should be corrected by bootloader
30		 */
31		reg = <0x00000000 0x80000000 0 0x40000000>;
32	};
33
34	reg_tqma8x_v3v3: regulator-tqma8x-v3v3 {
35		compatible = "regulator-fixed";
36		regulator-name = "V_3V3";
37		regulator-min-microvolt = <3300000>;
38		regulator-max-microvolt = <3300000>;
39		regulator-always-on;
40	};
41
42	/* SW7 controlled by SCU */
43	reg_1v8_io1: regulator-v1v8-io1 {
44		compatible = "regulator-fixed";
45		regulator-name = "V_1V8_IO1";
46		regulator-min-microvolt = <1800000>;
47		regulator-max-microvolt = <1800000>;
48		regulator-always-on;
49	};
50
51	/* LDO4 controlled by SCU */
52	reg_3v3_emmc: regulator-v3v3-emmc {
53		compatible = "regulator-fixed";
54		regulator-name = "V_3V3_EMMC";
55		regulator-min-microvolt = <3300000>;
56		regulator-max-microvolt = <3300000>;
57		regulator-always-on;
58	};
59};
60
61&acm {
62	status = "okay";
63};
64
65&adc0 {
66	pinctrl-names = "default";
67	pinctrl-0 = <&pinctrl_adc0>;
68	vref-supply = <&reg_vref_v1v8>;
69	status = "okay";
70};
71
72/* TQMa8QM only uses industrial grade, reduce trip points accordingly */
73&cpu_alert0 {
74	temperature = <95000>;
75};
76
77&cpu_crit0 {
78	temperature = <100000>;
79};
80
81&cpu_alert1 {
82	temperature = <95000>;
83};
84
85&cpu_crit1 {
86	temperature = <100000>;
87};
88
89&gpu_alert0 {
90	temperature = <95000>;
91};
92
93&gpu_crit0 {
94	temperature = <100000>;
95};
96
97&gpu_alert1 {
98	temperature = <95000>;
99};
100
101&gpu_crit1 {
102	temperature = <100000>;
103};
104
105&drc_alert0 {
106	temperature = <95000>;
107};
108
109&drc_crit0 {
110	temperature = <100000>;
111};
112/* end of temperature grade adjustments */
113
114&flexspi0 {
115	pinctrl-names = "default";
116	pinctrl-0 = <&pinctrl_flexspi0>;
117	status = "okay";
118
119	flash0: flash@0 {
120		compatible = "jedec,spi-nor";
121		reg = <0>;
122		spi-max-frequency = <66000000>;
123		spi-tx-bus-width = <4>;
124		spi-rx-bus-width = <4>;
125		vcc-supply = <&reg_1v8_io1>;
126
127		partitions {
128			compatible = "fixed-partitions";
129			#address-cells = <1>;
130			#size-cells = <1>;
131		};
132	};
133};
134
135&i2c1 {
136	clock-frequency = <400000>;
137	pinctrl-names = "default", "gpio";
138	pinctrl-0 = <&pinctrl_lpi2c1>;
139	pinctrl-1 = <&pinctrl_lpi2c1gpio>;
140	scl-gpios = <&lsio_gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
141	sda-gpios = <&lsio_gpio0 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
142	status = "okay";
143
144	se97: temperature-sensor@1b {
145		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
146		reg = <0x1b>;
147	};
148
149	pcf85063: rtc@51 {
150		compatible = "nxp,pcf85063a";
151		reg = <0x51>;
152		quartz-load-femtofarads = <7000>;
153	};
154
155	at24c02: eeprom@53 {
156		compatible = "nxp,se97b", "atmel,24c02";
157		reg = <0x53>;
158		pagesize = <16>;
159		read-only;
160		vcc-supply = <&reg_tqma8x_v3v3>;
161	};
162
163	m24c64: eeprom@57 {
164		compatible = "atmel,24c64";
165		reg = <0x57>;
166		pagesize = <32>;
167		vcc-supply = <&reg_tqma8x_v3v3>;
168	};
169};
170
171&mu_m0 {
172	status = "okay";
173};
174
175&mu1_m0 {
176	status = "okay";
177};
178
179&mu2_m0 {
180	status = "okay";
181};
182
183&thermal_zones {
184	/delete-node/ cpu1-thermal;
185
186	pmic0-thermal {
187		polling-delay-passive = <250>;
188		polling-delay = <2000>;
189		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
190
191		trips {
192			pmic_alert0: trip0 {
193				temperature = <110000>;
194				hysteresis = <2000>;
195				type = "passive";
196			};
197			pmic_crit0: trip1 {
198				temperature = <125000>;
199				hysteresis = <2000>;
200				type = "critical";
201			};
202		};
203
204		cooling-maps {
205			map0 {
206				trip = <&pmic_alert0>;
207				cooling-device =
208					<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
209					<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
210					<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
211					<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
212			};
213		};
214	};
215};
216
217&usdhc1 {
218	pinctrl-names = "default", "state_100mhz", "state_200mhz";
219	pinctrl-0 = <&pinctrl_usdhc1>;
220	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
221	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
222	bus-width = <8>;
223	vmmc-supply = <&reg_3v3_emmc>;
224	vqmmc-supply = <&reg_1v8_io1>;
225	no-sd;
226	no-sdio;
227	non-removable;
228	status = "okay";
229};
230
231&vpu {
232	compatible = "nxp,imx8qm-vpu";
233	status = "okay";
234};
235
236&vpu_core0 {
237	memory-region = <&decoder_boot>, <&decoder_rpc>;
238	status = "okay";
239};
240
241&vpu_core1 {
242	memory-region = <&encoder1_boot>, <&encoder1_rpc>;
243	status = "okay";
244};
245
246&vpu_core2 {
247	memory-region = <&encoder2_boot>, <&encoder2_rpc>;
248	status = "okay";
249};
250
251&iomuxc {
252	pinctrl_lpi2c1: lpi2c1grp {
253		fsl,pins = <IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA		0x0600004d>,
254			   <IMX8QM_GPT0_CLK_DMA_I2C1_SCL		0x0600004d>;
255	};
256
257	pinctrl_lpi2c1gpio: lpi2c1gpiogrp {
258		fsl,pins = <IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15		0x0600004d>,
259			   <IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14		0x0600004d>;
260	};
261
262	pinctrl_usdhc1: usdhc1grp {
263		fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041>,
264			   <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021>,
265			   <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0		0x00000021>,
266			   <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1		0x00000021>,
267			   <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2		0x00000021>,
268			   <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3		0x00000021>,
269			   <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4		0x00000021>,
270			   <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5		0x00000021>,
271			   <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6		0x00000021>,
272			   <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7		0x00000021>,
273			   <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041>,
274			   <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021>;
275	};
276
277	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
278		fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040>,
279			   <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021>,
280			   <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0		0x00000021>,
281			   <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1		0x00000021>,
282			   <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2		0x00000021>,
283			   <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3		0x00000021>,
284			   <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4		0x00000021>,
285			   <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5		0x00000021>,
286			   <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6		0x00000021>,
287			   <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7		0x00000021>,
288			   <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041>,
289			   <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021>;
290	};
291
292	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
293		fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040>,
294			   <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021>,
295			   <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0		0x00000021>,
296			   <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1		0x00000021>,
297			   <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2		0x00000021>,
298			   <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3		0x00000021>,
299			   <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4		0x00000021>,
300			   <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5		0x00000021>,
301			   <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6		0x00000021>,
302			   <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7		0x00000021>,
303			   <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041>,
304			   <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021>;
305	};
306
307	pinctrl_flexspi0: flexspi0grp {
308		fsl,pins = <IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x0000004d>,
309			   <IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x0000004d>,
310			   <IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x0000004d>,
311			   <IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x0000004d>,
312			   <IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x0000004d>,
313			   <IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x0000004d>,
314			   <IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B	0x0000004d>,
315			   <IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK		0x0000004d>,
316			   <IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK		0x0000004d>,
317			   <IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x0000004d>,
318			   <IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x0000004d>,
319			   <IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x0000004d>,
320			   <IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x0000004d>,
321			   <IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS		0x0000004d>,
322			   <IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x0000004d>,
323			   <IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x0000004d>;
324	};
325};
326