1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2020 Purism SPC 4 */ 5 6/dts-v1/; 7 8#include "dt-bindings/input/input.h" 9#include <dt-bindings/interrupt-controller/irq.h> 10#include "dt-bindings/pwm/pwm.h" 11#include "dt-bindings/usb/pd.h" 12#include "imx8mq.dtsi" 13 14/ { 15 model = "Purism Librem 5"; 16 compatible = "purism,librem5", "fsl,imx8mq"; 17 chassis-type = "handset"; 18 19 backlight_dsi: backlight-dsi { 20 compatible = "led-backlight"; 21 leds = <&led_backlight>; 22 }; 23 24 pmic_osc: clock-pmic { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <32768>; 28 clock-output-names = "pmic_osc"; 29 }; 30 31 chosen { 32 stdout-path = &uart1; 33 }; 34 35 gpio-keys { 36 compatible = "gpio-keys"; 37 pinctrl-names = "default"; 38 pinctrl-0 = <&pinctrl_keys>; 39 40 vol-down { 41 label = "VOL_DOWN"; 42 gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; 43 linux,code = <KEY_VOLUMEDOWN>; 44 debounce-interval = <50>; 45 }; 46 47 vol-up { 48 label = "VOL_UP"; 49 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; 50 linux,code = <KEY_VOLUMEUP>; 51 debounce-interval = <50>; 52 }; 53 }; 54 55 reg_aud_1v8: regulator-audio-1v8 { 56 compatible = "regulator-fixed"; 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_audiopwr>; 59 regulator-name = "AUDIO_PWR_EN"; 60 regulator-min-microvolt = <1800000>; 61 regulator-max-microvolt = <1800000>; 62 gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; 63 enable-active-high; 64 }; 65 66 /* 67 * the pinctrl for reg_csi_1v8 and reg_vcam_1v8 is added to the PMIC 68 * since we can't have it twice in the 2 different regulator nodes. 69 */ 70 reg_csi_1v8: regulator-csi-1v8 { 71 compatible = "regulator-fixed"; 72 regulator-name = "CAMERA_VDDIO_1V8"; 73 regulator-min-microvolt = <1800000>; 74 regulator-max-microvolt = <1800000>; 75 vin-supply = <®_vdd_3v3>; 76 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 77 enable-active-high; 78 }; 79 80 /* controlled by the CAMERA_POWER_KEY HKS */ 81 reg_vcam_1v2: regulator-vcam-1v2 { 82 compatible = "regulator-fixed"; 83 regulator-name = "CAMERA_VDDD_1V2"; 84 regulator-min-microvolt = <1200000>; 85 regulator-max-microvolt = <1200000>; 86 vin-supply = <®_vdd_1v8>; 87 enable-active-high; 88 }; 89 90 reg_vcam_2v8: regulator-vcam-2v8 { 91 compatible = "regulator-fixed"; 92 regulator-name = "CAMERA_VDDA_2V8"; 93 regulator-min-microvolt = <2800000>; 94 regulator-max-microvolt = <2800000>; 95 vin-supply = <®_vdd_3v3>; 96 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 97 enable-active-high; 98 }; 99 100 reg_gnss: regulator-gnss { 101 compatible = "regulator-fixed"; 102 pinctrl-names = "default"; 103 pinctrl-0 = <&pinctrl_gnsspwr>; 104 regulator-name = "GNSS"; 105 regulator-min-microvolt = <3300000>; 106 regulator-max-microvolt = <3300000>; 107 gpio = <&gpio3 12 GPIO_ACTIVE_HIGH>; 108 enable-active-high; 109 }; 110 111 reg_hub: regulator-hub { 112 compatible = "regulator-fixed"; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_hub_pwr>; 115 regulator-name = "HUB"; 116 regulator-min-microvolt = <3300000>; 117 regulator-max-microvolt = <3300000>; 118 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 119 enable-active-high; 120 }; 121 122 reg_lcd_1v8: regulator-lcd-1v8 { 123 compatible = "regulator-fixed"; 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_dsien>; 126 regulator-name = "LCD_1V8"; 127 regulator-min-microvolt = <1800000>; 128 regulator-max-microvolt = <1800000>; 129 vin-supply = <®_vdd_1v8>; 130 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 131 enable-active-high; 132 /* Otherwise i2c3 is not functional */ 133 regulator-always-on; 134 }; 135 136 reg_lcd_3v4: regulator-lcd-3v4 { 137 compatible = "regulator-fixed"; 138 regulator-name = "LCD_3V4"; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_dsibiasen>; 141 vin-supply = <®_vsys_3v4>; 142 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; 143 enable-active-high; 144 }; 145 146 reg_vdd_sen: regulator-vdd-sen { 147 compatible = "regulator-fixed"; 148 regulator-name = "VDD_SEN"; 149 regulator-min-microvolt = <3300000>; 150 regulator-max-microvolt = <3300000>; 151 }; 152 153 reg_vdd_1v8: regulator-vdd-1v8 { 154 compatible = "regulator-fixed"; 155 regulator-name = "VDD_1V8"; 156 regulator-min-microvolt = <1800000>; 157 regulator-max-microvolt = <1800000>; 158 vin-supply = <&buck7_reg>; 159 }; 160 161 reg_vdd_3v3: regulator-vdd-3v3 { 162 compatible = "regulator-fixed"; 163 regulator-name = "VDD_3V3"; 164 regulator-min-microvolt = <3300000>; 165 regulator-max-microvolt = <3300000>; 166 }; 167 168 reg_vsys_3v4: regulator-vsys-3v4 { 169 compatible = "regulator-fixed"; 170 regulator-name = "VSYS_3V4"; 171 regulator-min-microvolt = <3400000>; 172 regulator-max-microvolt = <3400000>; 173 regulator-always-on; 174 }; 175 176 reg_wifi_3v3: regulator-wifi-3v3 { 177 compatible = "regulator-fixed"; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_wifi_pwr>; 180 regulator-name = "3V3_WIFI"; 181 regulator-min-microvolt = <3300000>; 182 regulator-max-microvolt = <3300000>; 183 gpio = <&gpio3 10 GPIO_ACTIVE_HIGH>; 184 enable-active-high; 185 vin-supply = <®_vdd_3v3>; 186 }; 187 188 sound { 189 compatible = "simple-audio-card"; 190 pinctrl-names = "default"; 191 pinctrl-0 = <&pinctrl_hp>; 192 simple-audio-card,name = "Librem 5"; 193 simple-audio-card,format = "i2s"; 194 simple-audio-card,widgets = 195 "Headphone", "Headphones", 196 "Microphone", "Headset Mic", 197 "Microphone", "Digital Mic", 198 "Speaker", "Speaker"; 199 simple-audio-card,routing = 200 "Headphones", "HPOUTL", 201 "Headphones", "HPOUTR", 202 "Speaker", "SPKOUTL", 203 "Speaker", "SPKOUTR", 204 "Headset Mic", "MICBIAS", 205 "IN3R", "Headset Mic", 206 "DMICDAT", "Digital Mic"; 207 simple-audio-card,hp-det-gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; 208 209 simple-audio-card,cpu { 210 sound-dai = <&sai2>; 211 }; 212 213 simple-audio-card,codec { 214 sound-dai = <&codec>; 215 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 216 frame-master; 217 bitclock-master; 218 }; 219 }; 220 221 sound-wwan { 222 compatible = "simple-audio-card"; 223 simple-audio-card,name = "Modem"; 224 simple-audio-card,format = "i2s"; 225 226 simple-audio-card,cpu { 227 sound-dai = <&sai6>; 228 frame-inversion; 229 }; 230 231 simple-audio-card,codec { 232 sound-dai = <&bm818_codec>; 233 frame-master; 234 bitclock-master; 235 }; 236 }; 237 238 usdhc2_pwrseq: pwrseq { 239 pinctrl-names = "default"; 240 pinctrl-0 = <&pinctrl_bt>, <&pinctrl_wifi_disable>; 241 compatible = "mmc-pwrseq-simple"; 242 reset-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>, 243 <&gpio4 29 GPIO_ACTIVE_HIGH>; 244 }; 245 246 bm818_codec: sound-wwan-codec { 247 compatible = "broadmobi,bm818", "option,gtm601"; 248 #sound-dai-cells = <0>; 249 }; 250 251 vibrator { 252 compatible = "pwm-vibrator"; 253 pwms = <&pwm1 0 1000000000 0>; 254 pwm-names = "enable"; 255 vcc-supply = <®_vdd_3v3>; 256 }; 257}; 258 259&A53_0 { 260 cpu-supply = <&buck2_reg>; 261}; 262 263&A53_1 { 264 cpu-supply = <&buck2_reg>; 265}; 266 267&A53_2 { 268 cpu-supply = <&buck2_reg>; 269}; 270 271&A53_3 { 272 cpu-supply = <&buck2_reg>; 273}; 274 275&csi1 { 276 status = "okay"; 277}; 278 279&ddrc { 280 operating-points-v2 = <&ddrc_opp_table>; 281 status = "okay"; 282 283 ddrc_opp_table: opp-table { 284 compatible = "operating-points-v2"; 285 286 opp-25M { 287 opp-hz = /bits/ 64 <25000000>; 288 }; 289 290 opp-100M { 291 opp-hz = /bits/ 64 <100000000>; 292 }; 293 294 opp-800M { 295 opp-hz = /bits/ 64 <800000000>; 296 }; 297 }; 298}; 299 300&dphy { 301 status = "okay"; 302}; 303 304&ecspi1 { 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_ecspi1>; 307 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 status = "okay"; 311 312 nor_flash: flash@0 { 313 compatible = "jedec,spi-nor"; 314 reg = <0>; 315 spi-max-frequency = <1000000>; 316 #address-cells = <1>; 317 #size-cells = <1>; 318 319 partition@0 { 320 label = "protected0"; 321 reg = <0x0 0x30000>; 322 read-only; 323 }; 324 325 partition@30000 { 326 label = "protected1"; 327 reg = <0x30000 0x10000>; 328 read-only; 329 }; 330 331 partition@40000 { 332 label = "rw"; 333 reg = <0x40000 0x1C0000>; 334 }; 335 }; 336}; 337 338&gpio1 { 339 pinctrl-names = "default"; 340 pinctrl-0 = <&pinctrl_pmic_5v>; 341 342 pmic-5v-hog { 343 gpio-hog; 344 gpios = <1 GPIO_ACTIVE_HIGH>; 345 input; 346 lane-mapping = "pmic-5v"; 347 }; 348}; 349 350&iomuxc { 351 pinctrl_audiopwr: audiopwrgrp { 352 fsl,pins = < 353 /* AUDIO_POWER_EN_3V3 */ 354 MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x83 355 >; 356 }; 357 358 pinctrl_bl: blgrp { 359 fsl,pins = < 360 /* BACKLINGE_EN */ 361 MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x83 362 >; 363 }; 364 365 pinctrl_bt: btgrp { 366 fsl,pins = < 367 /* BT_REG_ON */ 368 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x83 369 >; 370 }; 371 372 pinctrl_camera_pwr: camerapwrgrp { 373 fsl,pins = < 374 /* CAMERA_PWR_EN_3V3 */ 375 MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x83 376 >; 377 }; 378 379 pinctrl_csi1: csi1grp { 380 fsl,pins = < 381 /* CSI1_NRST */ 382 MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x83 383 >; 384 }; 385 386 pinctrl_charger_in: chargeringrp { 387 fsl,pins = < 388 /* CHRG_INT */ 389 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x80 390 /* CHG_STATUS_B */ 391 MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x80 392 >; 393 }; 394 395 pinctrl_dsibiasen: dsibiasengrp { 396 fsl,pins = < 397 /* DSI_BIAS_EN */ 398 MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x83 399 >; 400 }; 401 402 pinctrl_dsien: dsiengrp { 403 fsl,pins = < 404 /* DSI_EN_3V3 */ 405 MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x83 406 >; 407 }; 408 409 pinctrl_dsirst: dsirstgrp { 410 fsl,pins = < 411 /* DSI_RST */ 412 MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x83 413 /* DSI_TE */ 414 MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x83 415 /* TP_RST */ 416 MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x83 417 >; 418 }; 419 420 pinctrl_ecspi1: ecspigrp { 421 fsl,pins = < 422 MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x83 423 MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x83 424 MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 425 MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x83 426 >; 427 }; 428 429 pinctrl_gauge: gaugegrp { 430 fsl,pins = < 431 /* BAT_LOW */ 432 MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x80 433 >; 434 }; 435 436 pinctrl_gnsspwr: gnsspwrgrp { 437 fsl,pins = < 438 /* GPS3V3_EN */ 439 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x83 440 >; 441 }; 442 443 pinctrl_haptic: hapticgrp { 444 fsl,pins = < 445 /* MOTO */ 446 MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x83 447 >; 448 }; 449 450 pinctrl_hp: hpgrp { 451 fsl,pins = < 452 /* HEADPHONE_DET_1V8 */ 453 MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x180 454 >; 455 }; 456 457 pinctrl_hub_pwr: hubpwrgrp { 458 fsl,pins = < 459 /* HUB_PWR_3V3_EN */ 460 MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x83 461 >; 462 }; 463 464 pinctrl_i2c1: i2c1grp { 465 fsl,pins = < 466 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000026 467 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000026 468 >; 469 }; 470 471 pinctrl_i2c2: i2c2grp { 472 fsl,pins = < 473 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000026 474 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000026 475 >; 476 }; 477 478 pinctrl_i2c3: i2c3grp { 479 fsl,pins = < 480 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000026 481 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000026 482 >; 483 }; 484 485 pinctrl_i2c4: i2c4grp { 486 fsl,pins = < 487 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000026 488 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000026 489 >; 490 }; 491 492 pinctrl_keys: keysgrp { 493 fsl,pins = < 494 /* VOL- */ 495 MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01C0 496 /* VOL+ */ 497 MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01C0 498 >; 499 }; 500 501 pinctrl_led_b: ledbgrp { 502 fsl,pins = < 503 /* LED_B */ 504 MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x06 505 >; 506 }; 507 508 pinctrl_led_g: ledggrp { 509 fsl,pins = < 510 /* LED_G */ 511 MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x06 512 >; 513 }; 514 515 pinctrl_led_r: ledrgrp { 516 fsl,pins = < 517 /* LED_R */ 518 MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x06 519 >; 520 }; 521 522 pinctrl_mag: maggrp { 523 fsl,pins = < 524 /* INT_MAG */ 525 MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x80 526 >; 527 }; 528 529 pinctrl_pmic: pmicgrp { 530 fsl,pins = < 531 /* PMIC_NINT */ 532 MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x80 533 >; 534 }; 535 536 pinctrl_pmic_5v: pmic5vgrp { 537 fsl,pins = < 538 /* PMIC_5V */ 539 MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x80 540 >; 541 }; 542 543 pinctrl_prox: proxgrp { 544 fsl,pins = < 545 /* INT_LIGHT */ 546 MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x80 547 >; 548 }; 549 550 pinctrl_rtc: rtcgrp { 551 fsl,pins = < 552 /* RTC_INT */ 553 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x80 554 >; 555 }; 556 557 pinctrl_sai2: sai2grp { 558 fsl,pins = < 559 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 560 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 561 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 562 MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 563 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 564 >; 565 }; 566 567 pinctrl_sai6: sai6grp { 568 fsl,pins = < 569 MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 570 MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 571 MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 572 MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 573 >; 574 }; 575 576 pinctrl_tcpc: tcpcgrp { 577 fsl,pins = < 578 /* TCPC_INT */ 579 MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01C0 580 >; 581 }; 582 583 pinctrl_touch: touchgrp { 584 fsl,pins = < 585 /* TP_INT */ 586 MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x80 587 >; 588 }; 589 590 pinctrl_typec: typecgrp { 591 fsl,pins = < 592 /* TYPEC_MUX_EN */ 593 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x83 594 >; 595 }; 596 597 pinctrl_uart1: uart1grp { 598 fsl,pins = < 599 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 600 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 601 >; 602 }; 603 604 pinctrl_uart2: uart2grp { 605 fsl,pins = < 606 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 607 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 608 >; 609 }; 610 611 pinctrl_uart3: uart3grp { 612 fsl,pins = < 613 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 614 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 615 >; 616 }; 617 618 pinctrl_uart4: uart4grp { 619 fsl,pins = < 620 MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 621 MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 622 MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 623 MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 624 >; 625 }; 626 627 pinctrl_usdhc1: usdhc1grp { 628 fsl,pins = < 629 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 630 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 631 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 632 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 633 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 634 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 635 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 636 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 637 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 638 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 639 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 640 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 641 >; 642 }; 643 644 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 645 fsl,pins = < 646 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 647 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 648 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 649 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 650 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 651 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 652 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 653 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 654 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 655 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 656 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 657 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 658 >; 659 }; 660 661 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 662 fsl,pins = < 663 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 664 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 665 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 666 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 667 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 668 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 669 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 670 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 671 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 672 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 673 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 674 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 675 >; 676 }; 677 678 pinctrl_usdhc2: usdhc2grp { 679 fsl,pins = < 680 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 681 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 682 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 683 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 684 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 685 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 686 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 687 MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 688 >; 689 }; 690 691 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 692 fsl,pins = < 693 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 694 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d 695 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd 696 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd 697 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd 698 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd 699 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd 700 MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 701 >; 702 }; 703 704 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 705 fsl,pins = < 706 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 707 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f 708 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf 709 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf 710 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf 711 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf 712 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf 713 MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 714 >; 715 }; 716 717 pinctrl_wifi_disable: wifidisablegrp { 718 fsl,pins = < 719 /* WIFI_REG_ON */ 720 MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x83 721 >; 722 }; 723 724 pinctrl_wifi_pwr: wifipwrgrp { 725 fsl,pins = < 726 /* WIFI3V3_EN */ 727 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x83 728 >; 729 }; 730 731 pinctrl_wdog: wdoggrp { 732 fsl,pins = < 733 /* nWDOG */ 734 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x1f 735 >; 736 }; 737}; 738 739&i2c1 { 740 clock-frequency = <387000>; 741 pinctrl-names = "default"; 742 pinctrl-0 = <&pinctrl_i2c1>; 743 status = "okay"; 744 745 typec_pd: usb-pd@3f { 746 compatible = "ti,tps6598x"; 747 reg = <0x3f>; 748 pinctrl-names = "default"; 749 pinctrl-0 = <&pinctrl_typec>, <&pinctrl_tcpc>; 750 interrupt-parent = <&gpio1>; 751 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 752 interrupt-names = "irq"; 753 754 connector { 755 ports { 756 #address-cells = <1>; 757 #size-cells = <0>; 758 759 port@0 { 760 reg = <0>; 761 762 usb_con_hs: endpoint { 763 remote-endpoint = <&typec_hs>; 764 }; 765 }; 766 767 port@1 { 768 reg = <1>; 769 770 usb_con_ss: endpoint { 771 remote-endpoint = <&typec_ss>; 772 }; 773 }; 774 }; 775 }; 776 }; 777 778 pmic: pmic@4b { 779 compatible = "rohm,bd71837"; 780 reg = <0x4b>; 781 pinctrl-names = "default"; 782 pinctrl-0 = <&pinctrl_pmic>, <&pinctrl_camera_pwr>; 783 clocks = <&pmic_osc>; 784 clock-names = "osc"; 785 clock-output-names = "pmic_clk"; 786 interrupt-parent = <&gpio1>; 787 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 788 rohm,reset-snvs-powered; 789 790 regulators { 791 buck1_reg: BUCK1 { 792 regulator-name = "buck1"; 793 regulator-min-microvolt = <700000>; 794 regulator-max-microvolt = <1300000>; 795 regulator-boot-on; 796 regulator-ramp-delay = <1250>; 797 rohm,dvs-run-voltage = <900000>; 798 rohm,dvs-idle-voltage = <850000>; 799 rohm,dvs-suspend-voltage = <800000>; 800 regulator-always-on; 801 }; 802 803 buck2_reg: BUCK2 { 804 regulator-name = "buck2"; 805 regulator-min-microvolt = <700000>; 806 regulator-max-microvolt = <1300000>; 807 regulator-boot-on; 808 regulator-ramp-delay = <1250>; 809 rohm,dvs-run-voltage = <1000000>; 810 rohm,dvs-idle-voltage = <900000>; 811 regulator-always-on; 812 }; 813 814 buck3_reg: BUCK3 { 815 regulator-name = "buck3"; 816 regulator-min-microvolt = <700000>; 817 regulator-max-microvolt = <1300000>; 818 regulator-boot-on; 819 rohm,dvs-run-voltage = <900000>; 820 }; 821 822 buck4_reg: BUCK4 { 823 regulator-name = "buck4"; 824 regulator-min-microvolt = <700000>; 825 regulator-max-microvolt = <1300000>; 826 rohm,dvs-run-voltage = <1000000>; 827 }; 828 829 buck5_reg: BUCK5 { 830 regulator-name = "buck5"; 831 regulator-min-microvolt = <700000>; 832 regulator-max-microvolt = <1350000>; 833 regulator-boot-on; 834 regulator-always-on; 835 }; 836 837 buck6_reg: BUCK6 { 838 regulator-name = "buck6"; 839 regulator-min-microvolt = <3000000>; 840 regulator-max-microvolt = <3300000>; 841 regulator-boot-on; 842 regulator-always-on; 843 }; 844 845 buck7_reg: BUCK7 { 846 regulator-name = "buck7"; 847 regulator-min-microvolt = <1605000>; 848 regulator-max-microvolt = <1995000>; 849 regulator-boot-on; 850 regulator-always-on; 851 }; 852 853 buck8_reg: BUCK8 { 854 regulator-name = "buck8"; 855 regulator-min-microvolt = <800000>; 856 regulator-max-microvolt = <1400000>; 857 regulator-boot-on; 858 regulator-always-on; 859 }; 860 861 ldo1_reg: LDO1 { 862 regulator-name = "ldo1"; 863 regulator-min-microvolt = <3000000>; 864 regulator-max-microvolt = <3300000>; 865 regulator-boot-on; 866 /* leave on for snvs power button */ 867 regulator-always-on; 868 }; 869 870 ldo2_reg: LDO2 { 871 regulator-name = "ldo2"; 872 regulator-min-microvolt = <900000>; 873 regulator-max-microvolt = <900000>; 874 regulator-boot-on; 875 /* leave on for snvs power button */ 876 regulator-always-on; 877 }; 878 879 ldo3_reg: LDO3 { 880 regulator-name = "ldo3"; 881 regulator-min-microvolt = <1800000>; 882 regulator-max-microvolt = <3300000>; 883 regulator-boot-on; 884 regulator-always-on; 885 }; 886 887 ldo4_reg: LDO4 { 888 regulator-name = "ldo4"; 889 regulator-min-microvolt = <900000>; 890 regulator-max-microvolt = <1800000>; 891 regulator-boot-on; 892 regulator-always-on; 893 }; 894 895 ldo5_reg: LDO5 { 896 /* VDD_PHY_0V9 - MIPI and HDMI domains */ 897 regulator-name = "ldo5"; 898 regulator-min-microvolt = <1800000>; 899 regulator-max-microvolt = <3300000>; 900 regulator-always-on; 901 }; 902 903 ldo6_reg: LDO6 { 904 /* VDD_PHY_0V9 - MIPI, HDMI and USB domains */ 905 regulator-name = "ldo6"; 906 regulator-min-microvolt = <900000>; 907 regulator-max-microvolt = <1800000>; 908 regulator-boot-on; 909 regulator-always-on; 910 }; 911 912 ldo7_reg: LDO7 { 913 /* VDD_PHY_3V3 - USB domain */ 914 regulator-name = "ldo7"; 915 regulator-min-microvolt = <1800000>; 916 regulator-max-microvolt = <3300000>; 917 regulator-boot-on; 918 regulator-always-on; 919 }; 920 }; 921 }; 922 923 rtc@68 { 924 compatible = "microcrystal,rv4162"; 925 reg = <0x68>; 926 pinctrl-names = "default"; 927 pinctrl-0 = <&pinctrl_rtc>; 928 interrupt-parent = <&gpio1>; 929 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 930 }; 931}; 932 933&i2c2 { 934 clock-frequency = <387000>; 935 pinctrl-names = "default"; 936 pinctrl-0 = <&pinctrl_i2c2>; 937 status = "okay"; 938 939 magnetometer@1e { 940 compatible = "st,lsm9ds1-magn"; 941 reg = <0x1e>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&pinctrl_mag>; 944 interrupt-parent = <&gpio3>; 945 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 946 vdd-supply = <®_vdd_sen>; 947 vddio-supply = <®_vdd_1v8>; 948 }; 949 950 regulator@3e { 951 compatible = "tps65132"; 952 reg = <0x3e>; 953 954 reg_lcd_avdd: outp { 955 regulator-name = "LCD_AVDD"; 956 vin-supply = <®_lcd_3v4>; 957 }; 958 959 reg_lcd_avee: outn { 960 regulator-name = "LCD_AVEE"; 961 vin-supply = <®_lcd_3v4>; 962 }; 963 }; 964 965 proximity: prox@60 { 966 compatible = "vishay,vcnl4040"; 967 reg = <0x60>; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&pinctrl_prox>; 970 interrupt-parent = <&gpio3>; 971 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 972 }; 973 974 accel_gyro: accel-gyro@6a { 975 compatible = "st,lsm9ds1-imu"; 976 reg = <0x6a>; 977 vdd-supply = <®_vdd_sen>; 978 vddio-supply = <®_vdd_1v8>; 979 }; 980}; 981 982&i2c3 { 983 clock-frequency = <387000>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&pinctrl_i2c3>; 986 status = "okay"; 987 988 codec: audio-codec@1a { 989 compatible = "wlf,wm8962"; 990 reg = <0x1a>; 991 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 992 assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; 993 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 994 assigned-clock-rates = <24576000>; 995 #sound-dai-cells = <0>; 996 mic-cfg = <0x200>; 997 DCVDD-supply = <®_aud_1v8>; 998 DBVDD-supply = <®_aud_1v8>; 999 AVDD-supply = <®_aud_1v8>; 1000 CPVDD-supply = <®_aud_1v8>; 1001 MICVDD-supply = <®_aud_1v8>; 1002 PLLVDD-supply = <®_aud_1v8>; 1003 SPKVDD1-supply = <®_vsys_3v4>; 1004 SPKVDD2-supply = <®_vsys_3v4>; 1005 gpio-cfg = < 1006 0x0000 /* n/c */ 1007 0x0001 /* gpio2, 1: default */ 1008 0x0013 /* gpio3, 2: dmicclk */ 1009 0x0000 /* n/c, 3: default */ 1010 0x8014 /* gpio5, 4: dmic_dat */ 1011 0x0000 /* gpio6, 5: default */ 1012 >; 1013 }; 1014 1015 camera_front: camera@20 { 1016 compatible = "hynix,hi846"; 1017 reg = <0x20>; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&pinctrl_csi1>; 1020 clocks = <&clk IMX8MQ_CLK_CLKO2>; 1021 assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; 1022 assigned-clock-rates = <25000000>; 1023 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 1024 vdda-supply = <®_vcam_2v8>; 1025 vddd-supply = <®_vcam_1v2>; 1026 vddio-supply = <®_csi_1v8>; 1027 rotation = <90>; 1028 orientation = <0>; 1029 1030 port { 1031 camera1_ep: endpoint { 1032 data-lanes = <1 2>; 1033 link-frequencies = /bits/ 64 1034 <80000000 200000000 300000000>; 1035 remote-endpoint = <&mipi1_sensor_ep>; 1036 }; 1037 }; 1038 }; 1039 1040 backlight@36 { 1041 compatible = "ti,lm36922"; 1042 reg = <0x36>; 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&pinctrl_bl>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 enable-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; 1048 vled-supply = <®_vsys_3v4>; 1049 ti,ovp-microvolt = <25000000>; 1050 1051 led_backlight: led@0 { 1052 reg = <0>; 1053 label = ":backlight"; 1054 linux,default-trigger = "backlight"; 1055 led-max-microamp = <20000>; 1056 }; 1057 }; 1058 1059 touchscreen@38 { 1060 compatible = "edt,edt-ft5506"; 1061 reg = <0x38>; 1062 pinctrl-names = "default"; 1063 pinctrl-0 = <&pinctrl_touch>; 1064 interrupt-parent = <&gpio1>; 1065 interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 1066 touchscreen-size-x = <720>; 1067 touchscreen-size-y = <1440>; 1068 vcc-supply = <®_lcd_1v8>; 1069 }; 1070}; 1071 1072&i2c4 { 1073 clock-frequency = <387000>; 1074 pinctrl-names = "default"; 1075 pinctrl-0 = <&pinctrl_i2c4>; 1076 status = "okay"; 1077 1078 bat: fuel-gauge@36 { 1079 compatible = "maxim,max17055"; 1080 reg = <0x36>; 1081 interrupt-parent = <&gpio3>; 1082 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 1083 pinctrl-names = "default"; 1084 pinctrl-0 = <&pinctrl_gauge>; 1085 maxim,over-heat-temp = <700>; 1086 maxim,over-volt = <4500>; 1087 maxim,rsns-microohm = <5000>; 1088 }; 1089 1090 bq25895: charger@6a { 1091 compatible = "ti,bq25895", "ti,bq25890"; 1092 reg = <0x6a>; 1093 pinctrl-names = "default"; 1094 pinctrl-0 = <&pinctrl_charger_in>; 1095 interrupt-parent = <&gpio3>; 1096 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 1097 phys = <&usb3_phy0>; 1098 ti,precharge-current = <130000>; /* uA */ 1099 ti,minimum-sys-voltage = <3700000>; /* uV */ 1100 ti,boost-voltage = <5000000>; /* uV */ 1101 ti,boost-max-current = <500000>; /* uA */ 1102 ti,use-vinmin-threshold = <1>; /* enable VINDPM */ 1103 ti,vinmin-threshold = <3900000>; /* uV */ 1104 monitored-battery = <&bat>; 1105 power-supplies = <&typec_pd>; 1106 }; 1107}; 1108 1109&lcdif { 1110 status = "okay"; 1111}; 1112 1113&mipi_csi1 { 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 status = "okay"; 1117 1118 ports { 1119 port@0 { 1120 reg = <0>; 1121 1122 mipi1_sensor_ep: endpoint { 1123 remote-endpoint = <&camera1_ep>; 1124 data-lanes = <1 2>; 1125 }; 1126 }; 1127 }; 1128}; 1129 1130&mipi_dsi { 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 status = "okay"; 1134 1135 lcd_panel: panel@0 { 1136 compatible = "mantix,mlaf057we51-x"; 1137 reg = <0>; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&pinctrl_dsirst>; 1140 avdd-supply = <®_lcd_avdd>; 1141 avee-supply = <®_lcd_avee>; 1142 vddi-supply = <®_lcd_1v8>; 1143 backlight = <&backlight_dsi>; 1144 reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; 1145 mantix,tp-rstn-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; 1146 1147 port { 1148 panel_in: endpoint { 1149 remote-endpoint = <&mipi_dsi_out>; 1150 }; 1151 }; 1152 }; 1153 1154 ports { 1155 port@1 { 1156 reg = <1>; 1157 1158 mipi_dsi_out: endpoint { 1159 remote-endpoint = <&panel_in>; 1160 }; 1161 }; 1162 }; 1163}; 1164 1165&pgc_gpu { 1166 power-supply = <&buck3_reg>; 1167}; 1168 1169&pgc_mipi { 1170 power-supply = <&ldo5_reg>; 1171}; 1172 1173&pgc_vpu { 1174 power-supply = <&buck4_reg>; 1175}; 1176 1177&pwm1 { 1178 pinctrl-names = "default"; 1179 pinctrl-0 = <&pinctrl_haptic>; 1180 status = "okay"; 1181}; 1182 1183&pwm2 { 1184 pinctrl-names = "default"; 1185 pinctrl-0 = <&pinctrl_led_b>; 1186 status = "okay"; 1187}; 1188 1189&pwm3 { 1190 pinctrl-names = "default"; 1191 pinctrl-0 = <&pinctrl_led_r>; 1192 status = "okay"; 1193}; 1194 1195&pwm4 { 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&pinctrl_led_g>; 1198 status = "okay"; 1199}; 1200 1201&sai2 { 1202 pinctrl-names = "default"; 1203 pinctrl-0 = <&pinctrl_sai2>; 1204 assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; 1205 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 1206 assigned-clock-rates = <24576000>; 1207 status = "okay"; 1208}; 1209 1210&sai6 { 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&pinctrl_sai6>; 1213 assigned-clocks = <&clk IMX8MQ_CLK_SAI6>; 1214 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 1215 assigned-clock-rates = <24576000>; 1216 fsl,sai-synchronous-rx; 1217 status = "okay"; 1218}; 1219 1220&snvs_pwrkey { 1221 status = "okay"; 1222}; 1223 1224&snvs_rtc { 1225 status = "disabled"; 1226}; 1227 1228&uart1 { /* console */ 1229 pinctrl-names = "default"; 1230 pinctrl-0 = <&pinctrl_uart1>; 1231 status = "okay"; 1232}; 1233 1234&uart2 { /* TPS - GPS - DEBUG */ 1235 pinctrl-names = "default"; 1236 pinctrl-0 = <&pinctrl_uart2>; 1237 status = "okay"; 1238 1239 gnss { 1240 compatible = "globaltop,pa6h"; 1241 vcc-supply = <®_gnss>; 1242 current-speed = <9600>; 1243 }; 1244}; 1245 1246&uart3 { /* SMC */ 1247 pinctrl-names = "default"; 1248 pinctrl-0 = <&pinctrl_uart3>; 1249 status = "okay"; 1250}; 1251 1252&uart4 { /* BT */ 1253 pinctrl-names = "default"; 1254 pinctrl-0 = <&pinctrl_uart4>; 1255 uart-has-rtscts; 1256 status = "okay"; 1257}; 1258 1259&usb3_phy0 { 1260 status = "okay"; 1261}; 1262 1263&usb3_phy1 { 1264 vbus-supply = <®_hub>; 1265 status = "okay"; 1266}; 1267 1268&usb_dwc3_0 { 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 dr_mode = "otg"; 1272 snps,dis_u3_susphy_quirk; 1273 status = "okay"; 1274 1275 port@0 { 1276 reg = <0>; 1277 1278 typec_hs: endpoint { 1279 remote-endpoint = <&usb_con_hs>; 1280 }; 1281 }; 1282 1283 port@1 { 1284 reg = <1>; 1285 1286 typec_ss: endpoint { 1287 remote-endpoint = <&usb_con_ss>; 1288 }; 1289 }; 1290}; 1291 1292&usb_dwc3_1 { 1293 dr_mode = "host"; 1294 status = "okay"; 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 1298 /* Microchip USB2642 */ 1299 hub@1 { 1300 compatible = "usb424,2640"; 1301 reg = <1>; 1302 #address-cells = <1>; 1303 #size-cells = <0>; 1304 1305 mass-storage@1 { 1306 compatible = "usb424,4041"; 1307 reg = <1>; 1308 }; 1309 }; 1310}; 1311 1312&usdhc1 { 1313 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; 1314 assigned-clock-rates = <400000000>; 1315 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 1316 pinctrl-0 = <&pinctrl_usdhc1>; 1317 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 1318 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 1319 bus-width = <8>; 1320 vmmc-supply = <®_vdd_3v3>; 1321 power-supply = <®_vdd_1v8>; 1322 non-removable; 1323 status = "okay"; 1324}; 1325 1326&usdhc2 { 1327 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; 1328 assigned-clock-rates = <200000000>; 1329 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 1330 pinctrl-0 = <&pinctrl_usdhc2>; 1331 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 1332 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 1333 bus-width = <4>; 1334 vmmc-supply = <®_wifi_3v3>; 1335 mmc-pwrseq = <&usdhc2_pwrseq>; 1336 post-power-on-delay-ms = <1000>; 1337 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 1338 max-frequency = <50000000>; 1339 disable-wp; 1340 cap-sdio-irq; 1341 keep-power-in-suspend; 1342 wakeup-source; 1343 status = "okay"; 1344}; 1345 1346&wdog1 { 1347 pinctrl-names = "default"; 1348 pinctrl-0 = <&pinctrl_wdog>; 1349 fsl,ext-reset-output; 1350 status = "okay"; 1351}; 1352