1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024 Variscite Ltd. 4 * 5 * Author: Tarang Raval <tarang.raval@siliconsignals.io> 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/phy/phy-imx8-pcie.h> 11#include <dt-bindings/leds/common.h> 12#include <dt-bindings/usb/pd.h> 13#include "imx8mp.dtsi" 14 15/ { 16 model = "Variscite VAR-SOM-MX8M Plus module"; 17 18 chosen { 19 stdout-path = &uart2; 20 }; 21 22 gpio-leds { 23 compatible = "gpio-leds"; 24 25 led-0 { 26 function = LED_FUNCTION_POWER; 27 gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; 28 linux,default-trigger = "heartbeat"; 29 }; 30 }; 31 32 memory@40000000 { 33 device_type = "memory"; 34 reg = <0x0 0x40000000 0 0xc0000000>, 35 <0x1 0x00000000 0 0xc0000000>; 36 }; 37 38 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 39 compatible = "regulator-fixed"; 40 regulator-name = "VSD_3V3"; 41 regulator-min-microvolt = <3300000>; 42 regulator-max-microvolt = <3300000>; 43 gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; 44 enable-active-high; 45 startup-delay-us = <100>; 46 off-on-delay-us = <12000>; 47 }; 48 49 reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 50 compatible = "regulator-gpio"; 51 regulator-name = "VSD_VSEL"; 52 regulator-min-microvolt = <1800000>; 53 regulator-max-microvolt = <3300000>; 54 gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; 55 states = <3300000 0x0 1800000 0x1>; 56 vin-supply = <&ldo5>; 57 }; 58 59 reg_phy_supply: regulator-phy-supply { 60 compatible = "regulator-fixed"; 61 regulator-name = "phy-supply"; 62 regulator-min-microvolt = <3300000>; 63 regulator-max-microvolt = <3300000>; 64 regulator-enable-ramp-delay = <20000>; 65 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; 66 enable-active-high; 67 regulator-always-on; 68 }; 69 70 reg_phy_vddio: regulator-phy-vddio { 71 compatible = "regulator-fixed"; 72 regulator-name = "vddio-1v8"; 73 regulator-min-microvolt = <1800000>; 74 regulator-max-microvolt = <1800000>; 75 }; 76}; 77 78&A53_0 { 79 cpu-supply = <&buck2>; 80}; 81 82&A53_1 { 83 cpu-supply = <&buck2>; 84}; 85 86&A53_2 { 87 cpu-supply = <&buck2>; 88}; 89 90&A53_3 { 91 cpu-supply = <&buck2>; 92}; 93 94&eqos { 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_eqos>; 97 /* 98 * The required RGMII TX and RX 2ns delays are implemented directly 99 * in hardware via passive delay elements on the SOM PCB. 100 * No delay configuration is needed in software via PHY driver. 101 */ 102 phy-mode = "rgmii"; 103 phy-handle = <ðphy0>; 104 status = "okay"; 105 106 mdio { 107 compatible = "snps,dwmac-mdio"; 108 #address-cells = <1>; 109 #size-cells = <0>; 110 111 ethphy0: ethernet-phy@4 { 112 compatible = "ethernet-phy-ieee802.3-c22"; 113 reg = <4>; 114 reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 115 reset-assert-us = <10000>; 116 reset-deassert-us = <100000>; 117 vddio-supply = <®_phy_vddio>; 118 119 leds { 120 #address-cells = <1>; 121 #size-cells = <0>; 122 123 led@0 { 124 reg = <0>; 125 color = <LED_COLOR_ID_YELLOW>; 126 function = LED_FUNCTION_LAN; 127 linux,default-trigger = "netdev"; 128 }; 129 130 led@1 { 131 reg = <1>; 132 color = <LED_COLOR_ID_GREEN>; 133 function = LED_FUNCTION_LAN; 134 linux,default-trigger = "netdev"; 135 }; 136 }; 137 }; 138 }; 139}; 140 141&i2c1 { 142 clock-frequency = <400000>; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&pinctrl_i2c1>; 145 status = "okay"; 146 147 pmic@25 { 148 compatible = "nxp,pca9450c"; 149 reg = <0x25>; 150 pinctrl-names = "default"; 151 pinctrl-0 = <&pinctrl_pmic>; 152 interrupt-parent = <&gpio5>; 153 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 154 155 regulators { 156 buck1: BUCK1 { 157 regulator-name = "BUCK1"; 158 regulator-min-microvolt = <600000>; 159 regulator-max-microvolt = <2187500>; 160 regulator-boot-on; 161 regulator-always-on; 162 regulator-ramp-delay = <3125>; 163 }; 164 165 buck2: BUCK2 { 166 regulator-name = "BUCK2"; 167 regulator-min-microvolt = <600000>; 168 regulator-max-microvolt = <2187500>; 169 regulator-boot-on; 170 regulator-always-on; 171 regulator-ramp-delay = <3125>; 172 nxp,dvs-run-voltage = <950000>; 173 nxp,dvs-standby-voltage = <850000>; 174 }; 175 176 buck4: BUCK4 { 177 regulator-name = "BUCK4"; 178 regulator-min-microvolt = <600000>; 179 regulator-max-microvolt = <3400000>; 180 regulator-boot-on; 181 regulator-always-on; 182 }; 183 184 buck5: BUCK5 { 185 regulator-name = "BUCK5"; 186 regulator-min-microvolt = <600000>; 187 regulator-max-microvolt = <3400000>; 188 regulator-boot-on; 189 regulator-always-on; 190 }; 191 192 buck6: BUCK6 { 193 regulator-name = "BUCK6"; 194 regulator-min-microvolt = <600000>; 195 regulator-max-microvolt = <3400000>; 196 regulator-boot-on; 197 regulator-always-on; 198 }; 199 200 ldo1: LDO1 { 201 regulator-name = "LDO1"; 202 regulator-min-microvolt = <1600000>; 203 regulator-max-microvolt = <3300000>; 204 regulator-boot-on; 205 regulator-always-on; 206 }; 207 208 ldo2: LDO2 { 209 regulator-name = "LDO2"; 210 regulator-min-microvolt = <800000>; 211 regulator-max-microvolt = <1150000>; 212 regulator-boot-on; 213 regulator-always-on; 214 }; 215 216 ldo3: LDO3 { 217 regulator-name = "LDO3"; 218 regulator-min-microvolt = <800000>; 219 regulator-max-microvolt = <3300000>; 220 regulator-boot-on; 221 regulator-always-on; 222 }; 223 224 ldo4: LDO4 { 225 regulator-name = "LDO4"; 226 regulator-min-microvolt = <1800000>; 227 regulator-max-microvolt = <1800000>; 228 regulator-always-on; 229 }; 230 231 ldo5: LDO5 { 232 regulator-name = "LDO5"; 233 regulator-min-microvolt = <1800000>; 234 regulator-max-microvolt = <3300000>; 235 }; 236 }; 237 }; 238}; 239 240&i2c3 { 241 clock-frequency = <400000>; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_i2c3>; 244 status = "okay"; 245 246 /* GPIO expander */ 247 pca9534: gpio@20 { 248 compatible = "nxp,pca9534"; 249 reg = <0x20>; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&pinctrl_pca9534>; 252 gpio-controller; 253 #gpio-cells = <2>; 254 interrupt-parent = <&gpio1>; 255 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 256 wakeup-source; 257 258 usb3-sata-sel-hog { 259 gpio-hog; 260 gpios = <4 0>; 261 output-low; 262 line-name = "usb3_sata_sel"; 263 }; 264 }; 265}; 266 267/* Console */ 268&uart2 { 269 pinctrl-names = "default"; 270 pinctrl-0 = <&pinctrl_uart2>; 271 status = "okay"; 272}; 273 274/* SD-card */ 275&usdhc2 { 276 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 277 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 278 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 279 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 280 cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 281 vmmc-supply = <®_usdhc2_vmmc>; 282 vqmmc-supply = <®_usdhc2_vqmmc>; 283 bus-width = <4>; 284 status = "okay"; 285}; 286 287/* eMMC */ 288&usdhc3 { 289 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 290 pinctrl-0 = <&pinctrl_usdhc3>; 291 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 292 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 293 bus-width = <8>; 294 non-removable; 295 status = "okay"; 296}; 297 298&wdog1 { 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_wdog>; 301 fsl,ext-reset-output; 302 status = "okay"; 303}; 304 305&iomuxc { 306 307 pinctrl_eqos: eqosgrp { 308 fsl,pins = < 309 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 310 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 311 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 312 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 313 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 314 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 315 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 316 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 317 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 318 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 319 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 320 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 321 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 322 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 323 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x10 324 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x150 325 >; 326 }; 327 328 pinctrl_i2c1: i2c1grp { 329 fsl,pins = < 330 MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x400001c2 331 MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x400001c2 332 >; 333 }; 334 335 pinctrl_i2c3: i2c3grp { 336 fsl,pins = < 337 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 338 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 339 >; 340 }; 341 342 pinctrl_pca9534: pca9534grp { 343 fsl,pins = < 344 MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0 345 >; 346 }; 347 348 pinctrl_pmic: pmicgrp { 349 fsl,pins = < 350 MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1c0 351 >; 352 }; 353 354 pinctrl_uart2: uart2grp { 355 fsl,pins = < 356 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 357 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 358 >; 359 }; 360 361 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 362 fsl,pins = < 363 MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 364 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 365 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0xc0 366 >; 367 }; 368 369 pinctrl_usdhc2: usdhc2grp { 370 fsl,pins = < 371 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 372 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 373 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 374 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 375 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 376 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 377 >; 378 }; 379 380 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 381 fsl,pins = < 382 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 383 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 384 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 385 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 386 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 387 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 388 >; 389 }; 390 391 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 392 fsl,pins = < 393 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 394 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 395 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 396 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 397 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 398 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 399 >; 400 }; 401 402 pinctrl_usdhc3: usdhc3grp { 403 fsl,pins = < 404 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 405 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 406 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 407 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 408 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 409 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 410 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 411 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 412 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 413 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 414 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 415 >; 416 }; 417 418 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 419 fsl,pins = < 420 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 421 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 422 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 423 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 424 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 425 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 426 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 427 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 428 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 429 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 430 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 431 >; 432 }; 433 434 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 435 fsl,pins = < 436 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 437 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 438 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 439 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 440 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 441 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 442 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 443 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 444 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 445 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 446 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 447 >; 448 }; 449 450 pinctrl_wdog: wdoggrp { 451 fsl,pins = < 452 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 453 >; 454 }; 455}; 456