1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024 Variscite Ltd. 4 * 5 * Author: Tarang Raval <tarang.raval@siliconsignals.io> 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/phy/phy-imx8-pcie.h> 11#include <dt-bindings/leds/common.h> 12#include <dt-bindings/usb/pd.h> 13#include "imx8mp.dtsi" 14 15/ { 16 model = "Variscite VAR-SOM-MX8M Plus module"; 17 18 chosen { 19 stdout-path = &uart2; 20 }; 21 22 gpio-leds { 23 compatible = "gpio-leds"; 24 25 led-0 { 26 function = LED_FUNCTION_POWER; 27 gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; 28 linux,default-trigger = "heartbeat"; 29 }; 30 }; 31 32 memory@40000000 { 33 device_type = "memory"; 34 reg = <0x0 0x40000000 0 0xc0000000>, 35 <0x1 0x00000000 0 0xc0000000>; 36 }; 37 38 39 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 40 compatible = "regulator-fixed"; 41 regulator-name = "VSD_3V3"; 42 regulator-min-microvolt = <3300000>; 43 regulator-max-microvolt = <3300000>; 44 gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; 45 enable-active-high; 46 startup-delay-us = <100>; 47 off-on-delay-us = <12000>; 48 }; 49}; 50 51&A53_0 { 52 cpu-supply = <&buck2>; 53}; 54 55&A53_1 { 56 cpu-supply = <&buck2>; 57}; 58 59&A53_2 { 60 cpu-supply = <&buck2>; 61}; 62 63&A53_3 { 64 cpu-supply = <&buck2>; 65}; 66 67&i2c1 { 68 clock-frequency = <400000>; 69 pinctrl-names = "default"; 70 pinctrl-0 = <&pinctrl_i2c1>; 71 status = "okay"; 72 73 pmic@25 { 74 compatible = "nxp,pca9450c"; 75 reg = <0x25>; 76 pinctrl-names = "default"; 77 pinctrl-0 = <&pinctrl_pmic>; 78 interrupt-parent = <&gpio5>; 79 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 80 81 regulators { 82 buck1: BUCK1 { 83 regulator-name = "BUCK1"; 84 regulator-min-microvolt = <600000>; 85 regulator-max-microvolt = <2187500>; 86 regulator-boot-on; 87 regulator-always-on; 88 regulator-ramp-delay = <3125>; 89 }; 90 91 buck2: BUCK2 { 92 regulator-name = "BUCK2"; 93 regulator-min-microvolt = <600000>; 94 regulator-max-microvolt = <2187500>; 95 regulator-boot-on; 96 regulator-always-on; 97 regulator-ramp-delay = <3125>; 98 nxp,dvs-run-voltage = <950000>; 99 nxp,dvs-standby-voltage = <850000>; 100 }; 101 102 buck4: BUCK4 { 103 regulator-name = "BUCK4"; 104 regulator-min-microvolt = <600000>; 105 regulator-max-microvolt = <3400000>; 106 regulator-boot-on; 107 regulator-always-on; 108 }; 109 110 buck5: BUCK5 { 111 regulator-name = "BUCK5"; 112 regulator-min-microvolt = <600000>; 113 regulator-max-microvolt = <3400000>; 114 regulator-boot-on; 115 regulator-always-on; 116 }; 117 118 buck6: BUCK6 { 119 regulator-name = "BUCK6"; 120 regulator-min-microvolt = <600000>; 121 regulator-max-microvolt = <3400000>; 122 regulator-boot-on; 123 regulator-always-on; 124 }; 125 126 ldo1: LDO1 { 127 regulator-name = "LDO1"; 128 regulator-min-microvolt = <1600000>; 129 regulator-max-microvolt = <3300000>; 130 regulator-boot-on; 131 regulator-always-on; 132 }; 133 134 ldo2: LDO2 { 135 regulator-name = "LDO2"; 136 regulator-min-microvolt = <800000>; 137 regulator-max-microvolt = <1150000>; 138 regulator-boot-on; 139 regulator-always-on; 140 }; 141 142 ldo3: LDO3 { 143 regulator-name = "LDO3"; 144 regulator-min-microvolt = <800000>; 145 regulator-max-microvolt = <3300000>; 146 regulator-boot-on; 147 regulator-always-on; 148 }; 149 150 ldo4: LDO4 { 151 regulator-name = "LDO4"; 152 regulator-min-microvolt = <1800000>; 153 regulator-max-microvolt = <1800000>; 154 regulator-always-on; 155 }; 156 157 ldo5: LDO5 { 158 regulator-name = "LDO5"; 159 regulator-min-microvolt = <1800000>; 160 regulator-max-microvolt = <3300000>; 161 }; 162 }; 163 }; 164}; 165 166&i2c3 { 167 clock-frequency = <400000>; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_i2c3>; 170 status = "okay"; 171 172 /* GPIO expander */ 173 pca9534: gpio@20 { 174 compatible = "nxp,pca9534"; 175 reg = <0x20>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_pca9534>; 178 gpio-controller; 179 #gpio-cells = <2>; 180 interrupt-parent = <&gpio1>; 181 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 182 wakeup-source; 183 184 usb3-sata-sel-hog { 185 gpio-hog; 186 gpios = <4 0>; 187 output-low; 188 line-name = "usb3_sata_sel"; 189 }; 190 }; 191}; 192 193/* Console */ 194&uart2 { 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_uart2>; 197 status = "okay"; 198}; 199 200/* SD-card */ 201&usdhc2 { 202 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 203 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 204 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 205 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 206 cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 207 vmmc-supply = <®_usdhc2_vmmc>; 208 bus-width = <4>; 209 status = "okay"; 210}; 211 212/* eMMC */ 213&usdhc3 { 214 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 215 pinctrl-0 = <&pinctrl_usdhc3>; 216 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 217 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 218 bus-width = <8>; 219 non-removable; 220 status = "okay"; 221}; 222 223&wdog1 { 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_wdog>; 226 fsl,ext-reset-output; 227 status = "okay"; 228}; 229 230&iomuxc { 231 232 pinctrl_i2c1: i2c1grp { 233 fsl,pins = < 234 MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x400001c2 235 MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x400001c2 236 >; 237 }; 238 239 pinctrl_i2c3: i2c3grp { 240 fsl,pins = < 241 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 242 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 243 >; 244 }; 245 246 pinctrl_pca9534: pca9534grp { 247 fsl,pins = < 248 MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0 249 >; 250 }; 251 252 pinctrl_pmic: pmicgrp { 253 fsl,pins = < 254 MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1c0 255 >; 256 }; 257 258 pinctrl_uart2: uart2grp { 259 fsl,pins = < 260 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 261 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 262 >; 263 }; 264 265 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 266 fsl,pins = < 267 MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 268 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 269 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0xc0 270 >; 271 }; 272 273 pinctrl_usdhc2: usdhc2grp { 274 fsl,pins = < 275 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 276 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 277 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 278 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 279 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 280 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 281 >; 282 }; 283 284 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 285 fsl,pins = < 286 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 287 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 288 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 289 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 290 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 291 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 292 >; 293 }; 294 295 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 296 fsl,pins = < 297 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 298 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 299 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 300 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 301 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 302 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 303 >; 304 }; 305 306 pinctrl_usdhc3: usdhc3grp { 307 fsl,pins = < 308 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 309 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 310 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 311 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 312 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 313 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 314 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 315 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 316 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 317 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 318 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 319 >; 320 }; 321 322 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 323 fsl,pins = < 324 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 325 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 326 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 327 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 328 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 329 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 330 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 331 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 332 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 333 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 334 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 335 >; 336 }; 337 338 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 339 fsl,pins = < 340 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 341 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 342 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 343 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 344 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 345 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 346 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 347 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 348 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 349 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 350 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 351 >; 352 }; 353 354 pinctrl_wdog: wdoggrp { 355 fsl,pins = < 356 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 357 >; 358 }; 359}; 360