1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Common dtsi for Variscite DART-MX8M-PLUS 4 * 5 * Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-plus/dart-mx8m-plus/ 6 * 7 * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11/dts-v1/; 12 13#include "imx8mp.dtsi" 14 15/ { 16 model = "Variscite DART-MX8M-PLUS Module"; 17 compatible = "variscite,var-dart-mx8mp", "fsl,imx8mp"; 18 19 reg_audio_supply: regulator-3p3v { 20 compatible = "regulator-fixed"; 21 regulator-name = "wm8904-supply"; 22 regulator-min-microvolt = <3300000>; 23 regulator-max-microvolt = <3300000>; 24 regulator-always-on; 25 }; 26 27 reg_phy_vddio: regulator-phy-vddio { 28 compatible = "regulator-fixed"; 29 regulator-name = "vddio-1v8"; 30 regulator-min-microvolt = <1800000>; 31 regulator-max-microvolt = <1800000>; 32 }; 33 34 sound-wm8904 { 35 compatible = "simple-audio-card"; 36 simple-audio-card,bitclock-master = <&codec_dai>; 37 simple-audio-card,format = "i2s"; 38 simple-audio-card,frame-master = <&codec_dai>; 39 simple-audio-card,mclk-fs = <256>; 40 simple-audio-card,name = "wm8904-audio"; 41 simple-audio-card,routing = 42 "Headphone Jack", "HPOUTL", 43 "Headphone Jack", "HPOUTR", 44 "IN2L", "Line In Jack", 45 "IN2R", "Line In Jack", 46 "IN1L", "Microphone Jack", 47 "IN1R", "Microphone Jack"; 48 simple-audio-card,widgets = 49 "Microphone", "Microphone Jack", 50 "Headphone", "Headphone Jack", 51 "Line", "Line In Jack"; 52 53 codec_dai: simple-audio-card,codec { 54 sound-dai = <&wm8904>; 55 }; 56 57 simple-audio-card,cpu { 58 sound-dai = <&sai3>; 59 }; 60 }; 61 62 wifi_pwrseq: wifi-pwrseq { 63 compatible = "mmc-pwrseq-simple"; 64 post-power-on-delay-ms = <100>; 65 power-off-delay-us = <10000>; 66 reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ 67 <&gpio2 8 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ 68 }; 69}; 70 71&A53_0 { 72 cpu-supply = <&buck2>; 73}; 74 75&A53_1 { 76 cpu-supply = <&buck2>; 77}; 78 79&A53_2 { 80 cpu-supply = <&buck2>; 81}; 82 83&A53_3 { 84 cpu-supply = <&buck2>; 85}; 86 87&eqos { 88 pinctrl-names = "default"; 89 pinctrl-0 = <&pinctrl_eqos>; 90 /* 91 * The required RGMII TX and RX 2ns delays are implemented directly 92 * in hardware via passive delay elements on the SOM PCB. 93 * No delay configuration is needed in software via PHY driver. 94 */ 95 phy-mode = "rgmii"; 96 phy-handle = <ðphy0>; 97 status = "okay"; 98 99 mdio { 100 compatible = "snps,dwmac-mdio"; 101 #address-cells = <1>; 102 #size-cells = <0>; 103 104 ethphy0: ethernet-phy@0 { 105 compatible = "ethernet-phy-ieee802.3-c22"; 106 reg = <0>; 107 reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; 108 reset-assert-us = <10000>; 109 reset-deassert-us = <100000>; 110 vddio-supply = <®_phy_vddio>; 111 }; 112 }; 113}; 114 115&i2c1 { 116 clock-frequency = <400000>; 117 pinctrl-names = "default", "gpio"; 118 pinctrl-0 = <&pinctrl_i2c1>; 119 pinctrl-1 = <&pinctrl_i2c1_gpio>; 120 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 121 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 122 status = "okay"; 123 124 wm8904: audio-codec@1a { 125 compatible = "wlf,wm8904"; 126 reg = <0x1a>; 127 #sound-dai-cells = <0>; 128 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; 129 clock-names = "mclk"; 130 AVDD-supply = <®_audio_supply>; 131 CPVDD-supply = <®_audio_supply>; 132 DBVDD-supply = <®_audio_supply>; 133 DCVDD-supply = <®_audio_supply>; 134 MICVDD-supply = <®_audio_supply>; 135 wlf,drc-cfg-names = "default", "peaklimiter", "tradition", 136 "soft", "music"; 137 /* 138 * Config registers per name, respectively: 139 * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 140 * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 141 * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 142 * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 143 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 144 */ 145 wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, 146 /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, 147 /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, 148 /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, 149 /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; 150 /* GPIO1 = DMIC_CLK, don't touch others */ 151 wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; 152 }; 153 154 pca9450: pmic@25 { 155 compatible = "nxp,pca9450c"; 156 reg = <0x25>; 157 pinctrl-names = "default"; 158 pinctrl-0 = <&pinctrl_pmic>; 159 interrupt-parent = <&gpio1>; 160 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 161 162 regulators { 163 buck1: BUCK1 { 164 regulator-name = "BUCK1"; 165 regulator-min-microvolt = <600000>; 166 regulator-max-microvolt = <2187500>; 167 regulator-boot-on; 168 regulator-always-on; 169 regulator-ramp-delay = <3125>; 170 }; 171 172 buck2: BUCK2 { 173 regulator-name = "BUCK2"; 174 regulator-min-microvolt = <600000>; 175 regulator-max-microvolt = <2187500>; 176 regulator-boot-on; 177 regulator-always-on; 178 regulator-ramp-delay = <3125>; 179 nxp,dvs-run-voltage = <950000>; 180 nxp,dvs-standby-voltage = <850000>; 181 }; 182 183 buck4: BUCK4 { 184 regulator-name = "BUCK4"; 185 regulator-min-microvolt = <600000>; 186 regulator-max-microvolt = <3400000>; 187 regulator-boot-on; 188 regulator-always-on; 189 }; 190 191 buck5: BUCK5 { 192 regulator-name = "BUCK5"; 193 regulator-min-microvolt = <600000>; 194 regulator-max-microvolt = <3400000>; 195 regulator-boot-on; 196 regulator-always-on; 197 }; 198 199 buck6: BUCK6 { 200 regulator-name = "BUCK6"; 201 regulator-min-microvolt = <600000>; 202 regulator-max-microvolt = <3400000>; 203 regulator-boot-on; 204 regulator-always-on; 205 }; 206 207 ldo1: LDO1 { 208 regulator-name = "LDO1"; 209 regulator-min-microvolt = <1600000>; 210 regulator-max-microvolt = <3300000>; 211 regulator-boot-on; 212 regulator-always-on; 213 }; 214 215 ldo2: LDO2 { 216 regulator-name = "LDO2"; 217 regulator-min-microvolt = <800000>; 218 regulator-max-microvolt = <1150000>; 219 regulator-boot-on; 220 regulator-always-on; 221 }; 222 223 ldo3: LDO3 { 224 regulator-name = "LDO3"; 225 regulator-min-microvolt = <800000>; 226 regulator-max-microvolt = <3300000>; 227 regulator-boot-on; 228 regulator-always-on; 229 }; 230 231 ldo4: LDO4 { 232 regulator-name = "LDO4"; 233 regulator-min-microvolt = <1800000>; 234 regulator-max-microvolt = <1800000>; 235 regulator-always-on; 236 }; 237 238 ldo5: LDO5 { 239 regulator-name = "LDO5"; 240 regulator-min-microvolt = <1800000>; 241 regulator-max-microvolt = <3300000>; 242 }; 243 }; 244 }; 245}; 246 247&mu2 { 248 status = "okay"; 249}; 250 251&sai3 { 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_sai3>; 254 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 255 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 256 assigned-clock-rates = <11536000>; 257 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, 258 <&clk IMX8MP_CLK_DUMMY>, 259 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, 260 <&clk IMX8MP_CLK_DUMMY>, 261 <&clk IMX8MP_CLK_DUMMY>; 262 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 263 #sound-dai-cells = <0>; 264 fsl,sai-mclk-direction-output; 265 status = "okay"; 266}; 267 268/* BT module */ 269&uart4 { 270 pinctrl-names = "default"; 271 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; 272 assigned-clocks = <&clk IMX8MP_CLK_UART4>; 273 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 274 uart-has-rtscts; 275 status = "okay"; 276 277 bluetooth_iw61x: bluetooth { 278 compatible = "nxp,88w8987-bt"; 279 }; 280}; 281 282/* WIFI */ 283&usdhc1 { 284 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 285 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>; 286 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>; 287 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>; 288 mmc-pwrseq = <&wifi_pwrseq>; 289 bus-width = <4>; 290 non-removable; 291 keep-power-in-suspend; 292 status = "okay"; 293}; 294 295/* eMMC */ 296&usdhc3 { 297 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 298 pinctrl-0 = <&pinctrl_usdhc3>; 299 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 300 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 301 bus-width = <8>; 302 non-removable; 303 status = "okay"; 304}; 305 306&wdog1 { 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_wdog>; 309 fsl,ext-reset-output; 310 status = "okay"; 311}; 312 313&iomuxc { 314 pinctrl_bt: btgrp { 315 fsl,pins = < 316 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0xc0 317 MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0xc0 318 >; 319 }; 320 321 pinctrl_eqos: eqosgrp { 322 fsl,pins = < 323 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 324 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 325 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 326 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 327 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 328 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 329 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 330 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 331 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 332 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 333 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 334 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 335 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 336 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 337 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x150 338 >; 339 }; 340 341 pinctrl_i2c1: i2c1grp { 342 fsl,pins = < 343 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 344 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 345 >; 346 }; 347 348 pinctrl_i2c1_gpio: i2c1gpiogrp { 349 fsl,pins = < 350 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c2 351 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c2 352 >; 353 }; 354 355 pinctrl_pmic: pmicgrp { 356 fsl,pins = < 357 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 358 >; 359 }; 360 361 pinctrl_sai3: sai3grp { 362 fsl,pins = < 363 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 364 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 365 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 366 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 367 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 368 MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6 369 MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6 370 >; 371 }; 372 373 pinctrl_uart4: uart4grp { 374 fsl,pins = < 375 MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x140 376 MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x140 377 MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x140 378 MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x140 379 >; 380 }; 381 382 pinctrl_usdhc1: usdhc1grp { 383 fsl,pins = < 384 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 385 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 386 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 387 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 388 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 389 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 390 >; 391 }; 392 393 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 394 fsl,pins = < 395 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 396 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 397 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 398 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 399 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 400 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 401 >; 402 }; 403 404 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 405 fsl,pins = < 406 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 407 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 408 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 409 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 410 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 411 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 412 >; 413 }; 414 415 pinctrl_usdhc3: usdhc3grp { 416 fsl,pins = < 417 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 418 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 419 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 420 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 421 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 422 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 423 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 424 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 425 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 426 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 427 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 428 >; 429 }; 430 431 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 432 fsl,pins = < 433 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 434 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 435 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 436 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 437 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 438 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 439 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 440 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 441 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 442 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 443 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 444 >; 445 }; 446 447 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 448 fsl,pins = < 449 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 450 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 451 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 452 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 453 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 454 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 455 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 456 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 457 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 458 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 459 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 460 >; 461 }; 462 463 pinctrl_wdog: wdoggrp { 464 fsl,pins = < 465 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 466 >; 467 }; 468 469 pinctrl_wifi: wifigrp { 470 fsl,pins = < 471 MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0xc0 472 MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0xc0 473 >; 474 }; 475}; 476