1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Variscite Sonata carrier board for DART-MX8M-PLUS 4 * 5 * Link: https://variscite.com/carrier-boards/sonata-board/ 6 * 7 * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11/dts-v1/; 12 13#include <dt-bindings/leds/common.h> 14#include <dt-bindings/phy/phy-imx8-pcie.h> 15#include "imx8mp-var-dart.dtsi" 16 17/ { 18 model = "Variscite DART-MX8M-PLUS on Sonata-Board"; 19 compatible = "variscite,var-dart-mx8mp-sonata", 20 "variscite,var-dart-mx8mp", 21 "fsl,imx8mp"; 22 23 chosen { 24 stdout-path = &uart1; 25 }; 26 27 gpio-keys { 28 compatible = "gpio-keys"; 29 30 button-home { 31 label = "Home"; 32 linux,code = <KEY_HOME>; 33 gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; 34 wakeup-source; 35 }; 36 37 button-up { 38 label = "Up"; 39 linux,code = <KEY_UP>; 40 gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; 41 wakeup-source; 42 }; 43 44 button-down { 45 label = "Down"; 46 linux,code = <KEY_DOWN>; 47 gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; 48 wakeup-source; 49 }; 50 51 button-back { 52 label = "Back"; 53 linux,code = <KEY_BACK>; 54 gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; 55 wakeup-source; 56 }; 57 }; 58 59 gpio-leds { 60 compatible = "gpio-leds"; 61 pinctrl-names = "default"; 62 pinctrl-0 = <&pinctrl_gpio_leds>; 63 64 led-emmc { 65 gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; 66 label = "eMMC"; 67 linux,default-trigger = "mmc2"; 68 }; 69 }; 70 71 native-hdmi-connector { 72 compatible = "hdmi-connector"; 73 label = "HDMI OUT"; 74 type = "a"; 75 76 port { 77 hdmi_in: endpoint { 78 remote-endpoint = <&hdmi_tx_out>; 79 }; 80 }; 81 }; 82 83 clk40m: oscillator { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <40000000>; 87 clock-output-names = "can_osc"; 88 }; 89 90 pcie0_refclk: pcie0-refclk { 91 compatible = "fixed-clock"; 92 #clock-cells = <0>; 93 clock-frequency = <100000000>; 94 }; 95 96 reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { 97 compatible = "regulator-fixed"; 98 pinctrl-names = "default"; 99 pinctrl-0 = <&pinctrl_vmmc_usdhc2>; 100 regulator-name = "VSD_3V3"; 101 regulator-min-microvolt = <3300000>; 102 regulator-max-microvolt = <3300000>; 103 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 104 enable-active-high; 105 startup-delay-us = <100>; 106 off-on-delay-us = <12000>; 107 }; 108 109 sound-hdmi { 110 compatible = "fsl,imx-audio-hdmi"; 111 model = "audio-hdmi"; 112 audio-cpu = <&aud2htx>; 113 hdmi-out; 114 }; 115 116 sound-xcvr { 117 compatible = "fsl,imx-audio-card"; 118 model = "imx-audio-xcvr"; 119 120 pri-dai-link { 121 link-name = "XCVR PCM"; 122 123 cpu { 124 sound-dai = <&xcvr>; 125 }; 126 }; 127 }; 128}; 129 130&aud2htx { 131 status = "okay"; 132}; 133 134&ecspi1 { 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_ecspi1>; 137 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, 138 <&gpio1 12 GPIO_ACTIVE_LOW>; 139 status = "okay"; 140 141 ads7846: touchscreen@0 { 142 compatible = "ti,ads7846"; 143 reg = <0>; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_restouch>; 146 interrupt-parent = <&gpio1>; 147 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 148 spi-max-frequency = <1500000>; 149 pendown-gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; 150 ti,x-min = /bits/ 16 <125>; 151 ti,x-max = /bits/ 16 <4008>; 152 ti,y-min = /bits/ 16 <282>; 153 ti,y-max = /bits/ 16 <3864>; 154 ti,x-plate-ohms = /bits/ 16 <180>; 155 ti,pressure-max = /bits/ 16 <255>; 156 ti,debounce-max = /bits/ 16 <10>; 157 ti,debounce-tol = /bits/ 16 <3>; 158 ti,debounce-rep = /bits/ 16 <1>; 159 ti,settle-delay-usec = /bits/ 16 <150>; 160 ti,keep-vref-on; 161 wakeup-source; 162 }; 163 164 can0: can@1 { 165 compatible = "microchip,mcp251xfd"; 166 reg = <1>; 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_can>; 169 interrupt-parent = <&gpio1>; 170 interrupts = <6 IRQ_TYPE_LEVEL_LOW>; 171 microchip,rx-int-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; 172 clocks = <&clk40m>; 173 spi-max-frequency = <20000000>; 174 }; 175}; 176 177&eqos { 178 mdio { 179 ethphy1: ethernet-phy@1 { 180 compatible = "ethernet-phy-ieee802.3-c22"; 181 reg = <1>; 182 reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; 183 reset-assert-us = <10000>; 184 reset-deassert-us = <20000>; 185 vddio-supply = <®_phy_vddio>; 186 187 leds { 188 #address-cells = <1>; 189 #size-cells = <0>; 190 191 led@0 { 192 reg = <0>; 193 color = <LED_COLOR_ID_YELLOW>; 194 function = LED_FUNCTION_LAN; 195 linux,default-trigger = "netdev"; 196 }; 197 198 led@1 { 199 reg = <1>; 200 color = <LED_COLOR_ID_GREEN>; 201 function = LED_FUNCTION_LAN; 202 linux,default-trigger = "netdev"; 203 }; 204 }; 205 }; 206 }; 207}; 208 209ðphy0 { 210 leds { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 214 led@0 { 215 reg = <0>; 216 color = <LED_COLOR_ID_YELLOW>; 217 function = LED_FUNCTION_LAN; 218 linux,default-trigger = "netdev"; 219 }; 220 221 led@1 { 222 reg = <1>; 223 color = <LED_COLOR_ID_GREEN>; 224 function = LED_FUNCTION_LAN; 225 linux,default-trigger = "netdev"; 226 }; 227 }; 228}; 229 230&fec { 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_fec>; 233 /* 234 * The required RGMII TX and RX 2ns delays are implemented directly 235 * in hardware via passive delay elements on the SOM PCB. 236 * No delay configuration is needed in software via PHY driver. 237 */ 238 phy-mode = "rgmii"; 239 phy-handle = <ðphy1>; 240 status = "okay"; 241}; 242 243&flexcan1 { 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_flexcan1>; 246 status = "okay"; 247}; 248 249&flexcan2 { 250 pinctrl-names = "default"; 251 pinctrl-0 = <&pinctrl_flexcan2>; 252 status = "okay"; 253}; 254 255&hdmi_pai { 256 status = "okay"; 257}; 258 259&hdmi_pvi { 260 status = "okay"; 261}; 262 263&hdmi_tx { 264 pinctrl-names = "default"; 265 pinctrl-0 = <&pinctrl_hdmi>; 266 status = "okay"; 267 268 ports { 269 port@1 { 270 hdmi_tx_out: endpoint { 271 remote-endpoint = <&hdmi_in>; 272 }; 273 }; 274 }; 275}; 276 277&hdmi_tx_phy { 278 status = "okay"; 279}; 280 281&i2c2 { 282 clock-frequency = <400000>; 283 pinctrl-names = "default", "gpio"; 284 pinctrl-0 = <&pinctrl_i2c2>; 285 pinctrl-1 = <&pinctrl_i2c2_gpio>; 286 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 287 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 288 status = "okay"; 289 290 pca9534: gpio@22 { 291 compatible = "nxp,pca9534"; 292 reg = <0x22>; 293 gpio-controller; 294 #gpio-cells = <2>; 295 296 eth10g-en-hog { 297 gpio-hog; 298 gpios = <5 GPIO_ACTIVE_HIGH>; 299 output-low; 300 line-name = "eth10g_sel"; 301 }; 302 303 pcie2-en-hog { 304 gpio-hog; 305 gpios = <6 GPIO_ACTIVE_HIGH>; 306 output-high; 307 line-name = "pcie2_sel"; 308 }; 309 310 /* RGB_SEL 311 * Keep signal low and not floating 312 */ 313 lvds-brg-enable-hog { 314 gpio-hog; 315 gpios = <7 GPIO_ACTIVE_HIGH>; 316 output-low; 317 line-name = "lvds_brg_en"; 318 }; 319 }; 320 321 /* Capacitive touch controller */ 322 ft5x06_ts: touchscreen@38 { 323 compatible = "edt,edt-ft5206"; 324 reg = <0x38>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pinctrl_captouch>; 327 reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; 328 interrupt-parent = <&gpio1>; 329 interrupts = <14 IRQ_TYPE_EDGE_FALLING>; 330 touchscreen-size-x = <800>; 331 touchscreen-size-y = <480>; 332 touchscreen-inverted-x; 333 touchscreen-inverted-y; 334 wakeup-source; 335 }; 336 337 typec@3d { 338 compatible = "nxp,ptn5150"; 339 reg = <0x3d>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pinctrl_extcon>; 342 interrupt-parent = <&gpio1>; 343 interrupts = <10 IRQ_TYPE_EDGE_FALLING>; 344 345 port { 346 typec_dr_sw: endpoint { 347 remote-endpoint = <&usb3_drd_sw>; 348 }; 349 }; 350 }; 351 352 rtc@68 { 353 compatible = "dallas,ds1337"; 354 reg = <0x68>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&pinctrl_rtc>; 357 interrupt-parent = <&gpio1>; 358 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 359 wakeup-source; 360 }; 361}; 362 363&i2c3 { 364 clock-frequency = <400000>; 365 pinctrl-names = "default", "gpio"; 366 pinctrl-0 = <&pinctrl_i2c3>; 367 pinctrl-1 = <&pinctrl_i2c3_gpio>; 368 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 369 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 370 status = "okay"; 371}; 372 373&i2c4 { 374 clock-frequency = <400000>; 375 pinctrl-names = "default", "gpio"; 376 pinctrl-0 = <&pinctrl_i2c4>; 377 pinctrl-1 = <&pinctrl_i2c4_gpio>; 378 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 379 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 380 status = "okay"; 381 382 pca6408_1: gpio@20 { 383 compatible = "nxp,pcal6408"; 384 reg = <0x20>; 385 gpio-controller; 386 #gpio-cells = <2>; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&pinctrl_pca6408>; 389 interrupt-parent = <&gpio1>; 390 interrupts = <5 IRQ_TYPE_LEVEL_LOW>; 391 }; 392 393 pca6408_2: gpio@21 { 394 compatible = "nxp,pcal6408"; 395 reg = <0x21>; 396 gpio-controller; 397 #gpio-cells = <2>; 398 interrupt-parent = <&gpio1>; 399 interrupts = <5 IRQ_TYPE_LEVEL_LOW>; 400 }; 401 402 st33ktpm2xi2c: tpm@2e { 403 compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; 404 reg = <0x2e>; 405 label = "tpm"; 406 reset-gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; 407 }; 408}; 409 410&lcdif3 { 411 status = "okay"; 412}; 413 414&pcie { 415 reset-gpios = <&pca6408_2 3 GPIO_ACTIVE_LOW>; 416 status = "okay"; 417}; 418 419&pcie_phy { 420 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 421 clocks = <&pcie0_refclk>; 422 clock-names = "ref"; 423 status = "okay"; 424}; 425 426&pwm1 { 427 pinctrl-names = "default"; 428 pinctrl-0 = <&pinctrl_pwm1>; 429 status = "okay"; 430}; 431 432&snvs_pwrkey { 433 status = "okay"; 434}; 435 436&snvs_rtc { 437 status = "disabled"; 438}; 439 440/* Console */ 441&uart1 { 442 pinctrl-names = "default"; 443 pinctrl-0 = <&pinctrl_uart1>; 444 status = "okay"; 445}; 446 447/* Header */ 448&uart2 { 449 pinctrl-names = "default"; 450 pinctrl-0 = <&pinctrl_uart2>; 451 status = "okay"; 452}; 453 454/* Header */ 455&uart3 { 456 pinctrl-names = "default"; 457 pinctrl-0 = <&pinctrl_uart3>; 458 status = "okay"; 459}; 460 461&usb3_0 { 462 status = "okay"; 463}; 464 465&usb3_1 { 466 status = "okay"; 467}; 468 469&usb_dwc3_0 { 470 dr_mode = "otg"; 471 hnp-disable; 472 srp-disable; 473 adp-disable; 474 usb-role-switch; 475 snps,dis-u1-entry-quirk; 476 snps,dis-u2-entry-quirk; 477 status = "okay"; 478 479 port { 480 usb3_drd_sw: endpoint { 481 remote-endpoint = <&typec_dr_sw>; 482 }; 483 }; 484}; 485 486&usb_dwc3_1 { 487 dr_mode = "host"; 488 status = "okay"; 489}; 490 491&usb3_phy0 { 492 fsl,phy-tx-vref-tune-percent = <122>; 493 fsl,phy-tx-preemp-amp-tune-microamp = <1800>; 494 fsl,phy-tx-vboost-level-microvolt = <1156>; 495 fsl,phy-comp-dis-tune-percent = <115>; 496 fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>; 497 fsl,phy-pcs-tx-swing-full-percent = <100>; 498 status = "okay"; 499}; 500 501&usb3_phy1 { 502 fsl,phy-tx-preemp-amp-tune-microamp = <1800>; 503 fsl,phy-tx-vref-tune-percent = <116>; 504 status = "okay"; 505}; 506 507&usdhc2 { 508 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 509 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 510 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 511 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 512 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 513 vmmc-supply = <®_usdhc2_vmmc>; 514 bus-width = <4>; 515 status = "okay"; 516}; 517 518&xcvr { 519 #sound-dai-cells = <0>; 520 status = "okay"; 521}; 522 523&iomuxc { 524 pinctrl_can: cangrp { 525 fsl,pins = < 526 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x1c6 527 MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x16 528 >; 529 }; 530 531 pinctrl_captouch: captouchgrp { 532 fsl,pins = < 533 MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x16 534 >; 535 }; 536 537 pinctrl_ecspi1: ecspi1grp { 538 fsl,pins = < 539 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x12 540 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x12 541 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x12 542 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x12 543 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x12 544 >; 545 }; 546 547 pinctrl_extcon: extcongrp { 548 fsl,pins = < 549 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10 550 >; 551 }; 552 553 pinctrl_fec: fecgrp { 554 fsl,pins = < 555 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 556 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 557 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 558 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x1d0 559 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 560 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 561 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x00 562 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x00 563 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x00 564 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x00 565 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x00 566 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x00 567 >; 568 }; 569 570 pinctrl_flexcan1: flexcan1grp { 571 fsl,pins = < 572 MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154 573 MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154 574 >; 575 }; 576 577 pinctrl_flexcan2: flexcan2grp { 578 fsl,pins = < 579 MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154 580 MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 581 >; 582 }; 583 584 pinctrl_gpio_leds: ledgrp { 585 fsl,pins = < 586 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0xc6 587 >; 588 }; 589 590 pinctrl_hdmi: hdmigrp { 591 fsl,pins = < 592 MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 593 MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 594 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 595 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10 596 >; 597 }; 598 599 pinctrl_i2c2: i2c2grp { 600 fsl,pins = < 601 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 602 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 603 >; 604 }; 605 606 pinctrl_i2c2_gpio: i2c2gpiogrp { 607 fsl,pins = < 608 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c2 609 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c2 610 >; 611 }; 612 613 pinctrl_i2c3: i2c3grp { 614 fsl,pins = < 615 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 616 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 617 >; 618 }; 619 620 pinctrl_i2c3_gpio: i2c3gpiogrp { 621 fsl,pins = < 622 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c2 623 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c2 624 >; 625 }; 626 627 pinctrl_i2c4: i2c4grp { 628 fsl,pins = < 629 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 630 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 631 >; 632 }; 633 634 pinctrl_i2c4_gpio: i2c4gpiogrp { 635 fsl,pins = < 636 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c2 637 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c2 638 >; 639 }; 640 641 pinctrl_pca6408: pca6408grp { 642 fsl,pins = < 643 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x1c6 644 >; 645 }; 646 647 pinctrl_pwm1: pwm1grp { 648 fsl,pins = < 649 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 650 >; 651 }; 652 653 pinctrl_restouch: restouchgrp { 654 fsl,pins = < 655 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0xc0 656 >; 657 }; 658 659 pinctrl_rtc: rtcgrp { 660 fsl,pins = < 661 MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c0 662 >; 663 }; 664 665 pinctrl_uart1: uart1grp { 666 fsl,pins = < 667 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 668 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40 669 >; 670 }; 671 672 pinctrl_uart2: uart2grp { 673 fsl,pins = < 674 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 675 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 676 >; 677 }; 678 679 pinctrl_uart3: uart3grp { 680 fsl,pins = < 681 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x40 682 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x40 683 >; 684 }; 685 686 pinctrl_usdhc2: usdhc2grp { 687 fsl,pins = < 688 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 689 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 690 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 691 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 692 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 693 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 694 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 695 >; 696 }; 697 698 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 699 fsl,pins = < 700 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 701 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 702 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 703 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 704 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 705 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 706 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 707 >; 708 }; 709 710 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 711 fsl,pins = < 712 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 713 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 714 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 715 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 716 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 717 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 718 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 719 >; 720 }; 721 722 pinctrl_vmmc_usdhc2: regvmmc-usdhc2grp { 723 fsl,pins = < 724 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 725 >; 726 }; 727 728 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 729 fsl,pins = < 730 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 731 >; 732 }; 733}; 734