1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2025-2026 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 5 * Author: Paul Gerber 6 */ 7 8#include <dt-bindings/net/ti-dp83867.h> 9#include <dt-bindings/phy/phy-imx8-pcie.h> 10#include "imx8mp.dtsi" 11 12/ { 13 model = "TQ-Systems i.MX8MPlus TQMa8MPxS"; 14 compatible = "tq,imx8mp-tqma8mpqs", "fsl,imx8mp"; 15 16 clk_dp: clk-dp { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 clock-frequency = <26000000>; 20 }; 21 22 clk_xtal25: clk-xtal25 { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <25000000>; 26 }; 27 28 memory@40000000 { 29 device_type = "memory"; 30 reg = <0x0 0x40000000 0 0x80000000>; 31 }; 32 33 reg_5v0: regulator-5v0 { 34 compatible = "regulator-fixed"; 35 regulator-name = "VCC_5V0"; 36 regulator-min-microvolt = <5000000>; 37 regulator-max-microvolt = <5000000>; 38 regulator-always-on; 39 }; 40 41 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 42 compatible = "regulator-fixed"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 45 regulator-name = "SDIO_PWR_EN"; 46 regulator-min-microvolt = <3300000>; 47 regulator-max-microvolt = <3300000>; 48 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 49 enable-active-high; 50 status = "disabled"; 51 }; 52 53 reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 54 compatible = "regulator-gpio"; 55 pinctrl-names = "default"; 56 pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>; 57 regulator-name = "V_SD"; 58 regulator-min-microvolt = <1800000>; 59 regulator-max-microvolt = <3300000>; 60 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 61 states = <1800000 0x1>, 62 <3300000 0x0>; 63 vin-supply = <&ldo5>; 64 status = "disabled"; 65 }; 66}; 67 68&A53_0 { 69 cpu-supply = <&buck2>; 70}; 71 72&audio_blk_ctrl { 73 assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, 74 <&clk IMX8MP_AUDIO_PLL2>; 75 assigned-clock-rates = <393216000>, <147333333>; 76}; 77 78&ecspi1 { 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_ecspi1>; 81 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio5 12 GPIO_ACTIVE_LOW>; 82}; 83 84/* GBE0 */ 85&eqos { 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_eqos>; 88 phy-mode = "rgmii-id"; 89 phy-handle = <ðphy0>; 90 snps,force_thresh_dma_mode; 91 snps,mtl-tx-config = <&mtl_tx_setup>; 92 snps,mtl-rx-config = <&mtl_rx_setup>; 93 94 mdio { 95 compatible = "snps,dwmac-mdio"; 96 #address-cells = <1>; 97 #size-cells = <0>; 98 99 ethphy0: ethernet-phy@0 { 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pinctrl_eqos_phy>; 102 compatible = "ethernet-phy-ieee802.3-c22"; 103 reg = <0>; 104 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 105 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 106 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 107 ti,dp83867-rxctrl-strap-quirk; 108 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 109 reset-gpios = <&expander0 6 GPIO_ACTIVE_LOW>; 110 reset-assert-us = <500000>; 111 reset-deassert-us = <50000>; 112 enet-phy-lane-no-swap; 113 interrupt-parent = <&gpio2>; 114 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 115 }; 116 117 ethphy3: ethernet-phy@3 { 118 pinctrl-names = "default"; 119 pinctrl-0 = <&pinctrl_fec_phy>; 120 compatible = "ethernet-phy-ieee802.3-c22"; 121 reg = <3>; 122 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 123 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 124 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 125 ti,dp83867-rxctrl-strap-quirk; 126 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 127 reset-gpios = <&expander0 7 GPIO_ACTIVE_LOW>; 128 reset-assert-us = <500000>; 129 reset-deassert-us = <50000>; 130 enet-phy-lane-no-swap; 131 interrupt-parent = <&gpio2>; 132 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 133 }; 134 }; 135 136 mtl_tx_setup: tx-queues-config { 137 snps,tx-queues-to-use = <5>; 138 139 queue0 { 140 snps,dcb-algorithm; 141 snps,priority = <0x1>; 142 }; 143 144 queue1 { 145 snps,dcb-algorithm; 146 snps,priority = <0x2>; 147 }; 148 149 queue2 { 150 snps,dcb-algorithm; 151 snps,priority = <0x4>; 152 }; 153 154 queue3 { 155 snps,dcb-algorithm; 156 snps,priority = <0x8>; 157 }; 158 159 queue4 { 160 snps,dcb-algorithm; 161 snps,priority = <0xf0>; 162 }; 163 }; 164 165 mtl_rx_setup: rx-queues-config { 166 snps,rx-queues-to-use = <5>; 167 snps,rx-sched-sp; 168 169 queue0 { 170 snps,dcb-algorithm; 171 snps,priority = <0x1>; 172 snps,map-to-dma-channel = <0>; 173 }; 174 175 queue1 { 176 snps,dcb-algorithm; 177 snps,priority = <0x2>; 178 snps,map-to-dma-channel = <1>; 179 }; 180 181 queue2 { 182 snps,dcb-algorithm; 183 snps,priority = <0x4>; 184 snps,map-to-dma-channel = <2>; 185 }; 186 187 queue3 { 188 snps,dcb-algorithm; 189 snps,priority = <0x8>; 190 snps,map-to-dma-channel = <3>; 191 }; 192 193 queue4 { 194 snps,dcb-algorithm; 195 snps,priority = <0xf0>; 196 snps,map-to-dma-channel = <4>; 197 }; 198 }; 199}; 200 201/* GBE1 */ 202&fec { 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_fec>; 205 phy-mode = "rgmii-id"; 206 phy-handle = <ðphy3>; 207 fsl,magic-packet; 208}; 209 210&flexcan1 { 211 pinctrl-names = "default"; 212 pinctrl-0 = <&pinctrl_flexcan1>; 213}; 214 215&flexcan2 { 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_flexcan2>; 218}; 219 220&flexspi { 221 pinctrl-names = "default"; 222 pinctrl-0 = <&pinctrl_flexspi0>; 223 status = "okay"; 224 225 flash0: flash@0 { 226 reg = <0>; 227 compatible = "jedec,spi-nor"; 228 spi-max-frequency = <66666666>; 229 spi-tx-bus-width = <4>; 230 spi-rx-bus-width = <4>; 231 vcc-supply = <&buck5>; 232 233 partitions { 234 compatible = "fixed-partitions"; 235 #address-cells = <1>; 236 #size-cells = <1>; 237 }; 238 }; 239}; 240 241&gpio1 { 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_gpio1>; 244 245 gpio-line-names = "SLEEP", "BATLOW#", "", "LID", 246 "", "GPIO10", "CHARGING#", "CHG_PRSNT#", 247 "PMIC_IRQ#", "ESPI_CS1_ALERT#", "USB1_OTG_ID", "USB2_OTG_ID", 248 "", "", "", "", 249 "", "", "", "", 250 "", "", "", "", 251 "", "", "", "", 252 "", "", "", ""; 253 254 pmic_irq_hog: pmic-irq-hog { 255 gpio-hog; 256 gpios = <8 0>; 257 input; 258 line-name = "PMIC_IRQ#"; 259 }; 260}; 261 262&gpio2 { 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_hoggpio2>; 265 266 gpio-line-names = "", "", "", "", 267 "", "", "", "", 268 "", "", "PERST#", "PEWAKE#", 269 "SDIO_CD#", "", "", "", 270 "", "", "", "SDIO_PWR_EN", 271 "", "", "", "", 272 "", "", "", "", 273 "", "", "", ""; 274 275 enet0-int-hog { 276 gpio-hog; 277 gpios = <0 0>; 278 input; 279 line-name = "ENET0_INT#"; 280 }; 281 282 enet1-int-hog { 283 gpio-hog; 284 gpios = <1 0>; 285 input; 286 line-name = "ENET_INT#"; 287 }; 288 289 pewake-hog { 290 gpio-hog; 291 gpios = <11 0>; 292 input; 293 line-name = "PEWAKE#"; 294 }; 295}; 296 297&gpio3 { 298 pinctrl-names = "default"; 299 pinctrl-0 = <&pinctrl_gpio3>; 300 301 gpio-line-names = "", "", "", "", 302 "", "", "", "", 303 "", "", "", "", 304 "", "", "", "", 305 "", "", "", "GPIO4", 306 "GPIO3", "", "", "", 307 "", "", "", "", 308 "TEMP_EVENT#", "", "", ""; 309 310 temp-event-hog { 311 gpio-hog; 312 gpios = <28 0>; 313 input; 314 line-name = "TEMP_EVENT#"; 315 }; 316}; 317 318&gpio4 { 319 pinctrl-names = "default"; 320 pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_sdp>, <&pinctrl_espi_rst>; 321 322 gpio-line-names = "RTC_INT#", "GPIO8", "", "", 323 "GPIO9", "ESPI_RST#", "", "", 324 "", "", "", "", 325 "", "", "", "", 326 "", "", "GBE0_SDP_DIR", "", 327 "GPIO7", "", "", "", 328 "", "GPIO0", "GPIO1", "", 329 "GPIO2", "GPIO6", "", ""; 330 331 rtc-int-hog { 332 gpio-hog; 333 gpios = <0 0>; 334 input; 335 line-name = "RTC_INT#"; 336 }; 337 338 espi-reset-hog { 339 gpio-hog; 340 gpios = <5 0>; 341 output-high; 342 line-name = "ESPI_RST#"; 343 }; 344}; 345 346&gpio5 { 347 pinctrl-names = "default"; 348 pinctrl-0 = <&pinctrl_gpio5>; 349 350 gpio-line-names = "", "", "", "", 351 "", "GPIO5", "", "", 352 "", "", "GPIO12", "GPIO11", 353 "", "GPIO13", "", "", 354 "", "", "", "", 355 "", "", "", "", 356 "", "", "", "", 357 "", "", "", ""; 358 359 dp-hpd-int-hog { 360 gpio-hog; 361 gpios = <21 0>; 362 input; 363 line-name = "DP_HPD_INT"; 364 }; 365}; 366 367&hdmi_tx { 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_hdmi>; 370}; 371 372&i2c1 { 373 clock-frequency = <384000>; 374 pinctrl-names = "default", "gpio"; 375 pinctrl-0 = <&pinctrl_i2c1>; 376 pinctrl-1 = <&pinctrl_i2c1_gpio>; 377 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 378 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 379 status = "okay"; 380 381 eeprom0: eeprom@50 { 382 compatible = "atmel,24c64"; 383 reg = <0x50>; 384 pagesize = <32>; 385 read-only; 386 vcc-supply = <&buck5>; 387 }; 388 389 pcf85063: rtc@51 { 390 compatible = "nxp,pcf85063a"; 391 reg = <0x51>; 392 quartz-load-femtofarads = <7000>; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&pinctrl_pcf85063>; 395 interrupt-parent = <&gpio4>; 396 interrupts = <0 IRQ_TYPE_EDGE_FALLING>; 397 }; 398 399 eeprom1: eeprom@54 { 400 compatible = "atmel,24c64"; 401 reg = <0x54>; 402 pagesize = <32>; 403 vcc-supply = <&buck5>; 404 }; 405 406 /* protectable identification memory (part of M24C64-D @50) */ 407 eeprom@58 { 408 compatible = "atmel,24c64d-wl"; 409 reg = <0x58>; 410 size = <32>; 411 pagesize = <32>; 412 vcc-supply = <&buck5>; 413 }; 414 415 /* protectable identification memory (part of M24C64-D @54) */ 416 eeprom@5c { 417 compatible = "atmel,24c64d-wl"; 418 reg = <0x5c>; 419 size = <32>; 420 pagesize = <32>; 421 vcc-supply = <&buck5>; 422 }; 423 424 pcieclk: clock-generator@6a { 425 compatible = "renesas,9fgv0241"; 426 reg = <0x6a>; 427 clocks = <&clk_xtal25>; 428 #clock-cells = <1>; 429 }; 430 431 inertial-sensor@6b { 432 compatible = "st,ism330dhcx"; 433 reg = <0x6b>; 434 vdd-supply = <&buck4>; 435 vddio-supply = <&buck4>; 436 }; 437}; 438 439&i2c2 { 440 clock-frequency = <384000>; 441 pinctrl-names = "default", "gpio"; 442 pinctrl-0 = <&pinctrl_i2c2>; 443 pinctrl-1 = <&pinctrl_i2c2_gpio>; 444 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 445 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 446 status = "okay"; 447 448 pmic: pmic@25 { 449 reg = <0x25>; 450 compatible = "nxp,pca9450c"; 451 452 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ 453 pinctrl-names = "default"; 454 pinctrl-0 = <&pinctrl_pmic>; 455 interrupt-parent = <&gpio1>; 456 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 457 458 regulators { 459 /* V_0V85_SOC: 0.85 .. 0.95 */ 460 buck1: BUCK1 { 461 regulator-name = "BUCK1"; 462 regulator-min-microvolt = <850000>; 463 regulator-max-microvolt = <950000>; 464 regulator-boot-on; 465 regulator-always-on; 466 regulator-ramp-delay = <3125>; 467 }; 468 469 /* VDD_ARM */ 470 buck2: BUCK2 { 471 regulator-name = "BUCK2"; 472 regulator-min-microvolt = <850000>; 473 regulator-max-microvolt = <1000000>; 474 regulator-boot-on; 475 regulator-always-on; 476 nxp,dvs-run-voltage = <950000>; 477 nxp,dvs-standby-voltage = <850000>; 478 regulator-ramp-delay = <3125>; 479 }; 480 481 /* VCC3V3 -> VMMC, ... must not be changed */ 482 buck4: BUCK4 { 483 regulator-name = "BUCK4"; 484 regulator-min-microvolt = <3300000>; 485 regulator-max-microvolt = <3300000>; 486 regulator-boot-on; 487 regulator-always-on; 488 }; 489 490 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ 491 buck5: BUCK5 { 492 regulator-name = "BUCK5"; 493 regulator-min-microvolt = <1800000>; 494 regulator-max-microvolt = <1800000>; 495 regulator-boot-on; 496 regulator-always-on; 497 }; 498 499 /* V_1V1 -> RAM, ... must not be changed */ 500 buck6: BUCK6 { 501 regulator-name = "BUCK6"; 502 regulator-min-microvolt = <1100000>; 503 regulator-max-microvolt = <1100000>; 504 regulator-boot-on; 505 regulator-always-on; 506 }; 507 508 /* V_1V8_SNVS */ 509 ldo1: LDO1 { 510 regulator-name = "LDO1"; 511 regulator-min-microvolt = <1800000>; 512 regulator-max-microvolt = <1800000>; 513 regulator-boot-on; 514 regulator-always-on; 515 }; 516 517 /* V_1V8_ANA */ 518 ldo3: LDO3 { 519 regulator-name = "LDO3"; 520 regulator-min-microvolt = <1800000>; 521 regulator-max-microvolt = <1800000>; 522 regulator-boot-on; 523 regulator-always-on; 524 }; 525 526 /* unused */ 527 ldo4: LDO4 { 528 regulator-name = "LDO4"; 529 regulator-min-microvolt = <800000>; 530 regulator-max-microvolt = <3300000>; 531 }; 532 533 /* VCC SD IO - switched using SD2 VSELECT */ 534 ldo5: LDO5 { 535 regulator-name = "LDO5"; 536 regulator-min-microvolt = <1800000>; 537 regulator-max-microvolt = <3300000>; 538 }; 539 }; 540 }; 541 542 tmp1075: temperature-sensor@4a { 543 compatible = "ti,tmp1075"; 544 reg = <0x4a>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&pinctrl_tmp1075>; 547 vs-supply = <&buck4>; 548 }; 549 550 expander0: gpio@73 { 551 compatible = "nxp,pca9538"; 552 reg = <0x73>; 553 gpio-controller; 554 #gpio-cells = <2>; 555 vcc-supply = <&buck5>; 556 gpio-line-names = "LCD0_BKLT_EN", "LCD0_VDD_EN", 557 "LCD1_BKLT_EN", "LCD1_VDD_EN", 558 "DP_BRIDGE_EN", "HUB_RST#", 559 "ENET0_RESET#", "ENET1_RESET#"; 560 }; 561}; 562 563&i2c3 { 564 clock-frequency = <384000>; 565 pinctrl-names = "default", "gpio"; 566 pinctrl-0 = <&pinctrl_i2c3>; 567 pinctrl-1 = <&pinctrl_i2c3_gpio>; 568 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 569 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 570 status = "okay"; 571 572 dp_bridge: dp-bridge@f { 573 compatible = "toshiba,tc9595", "toshiba,tc358767"; 574 reg = <0xf>; 575 pinctrl-names = "default"; 576 pinctrl-0 = <&pinctrl_tc9595>; 577 clock-names = "ref"; 578 clocks = <&clk_dp>; 579 reset-gpios = <&expander0 4 GPIO_ACTIVE_HIGH>; 580 toshiba,hpd-pin = <0>; 581 interrupts-extended = <&gpio5 21 IRQ_TYPE_LEVEL_HIGH>; 582 status = "disabled"; 583 584 ports { 585 #address-cells = <1>; 586 #size-cells = <0>; 587 588 port@0 { 589 reg = <0>; 590 591 dsi_in: endpoint { 592 remote-endpoint = <&dsi_out>; 593 data-lanes = <1 2 3 4>; 594 }; 595 }; 596 597 port@2 { 598 reg = <2>; 599 600 endpoint { 601 toshiba,pre-emphasis = /bits/ 8 <1 1>; 602 }; 603 }; 604 }; 605 }; 606}; 607 608&i2c4 { 609 clock-frequency = <384000>; 610 pinctrl-names = "default", "gpio"; 611 pinctrl-0 = <&pinctrl_i2c4>; 612 pinctrl-1 = <&pinctrl_i2c4_gpio>; 613 scl-gpios = <&gpio2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 614 sda-gpios = <&gpio2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 615 status = "okay"; 616}; 617 618&i2c6 { 619 clock-frequency = <384000>; 620 pinctrl-names = "default", "gpio"; 621 pinctrl-0 = <&pinctrl_i2c6>; 622 pinctrl-1 = <&pinctrl_i2c6_gpio>; 623 scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 624 sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 625 status = "okay"; 626}; 627 628// Change parent clock of disp1 pixel clock to audio_pll2 629&media_blk_ctrl { 630 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, 631 <&clk IMX8MP_CLK_MEDIA_APB>, 632 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, 633 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, 634 <&clk IMX8MP_CLK_MEDIA_ISP>, 635 <&clk IMX8MP_VIDEO_PLL1>; 636 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 637 <&clk IMX8MP_SYS_PLL1_800M>, 638 <&clk IMX8MP_AUDIO_PLL2_OUT>, 639 <&clk IMX8MP_VIDEO_PLL1_OUT>, 640 <&clk IMX8MP_SYS_PLL2_500M>; 641}; 642 643&mipi_dsi { 644 samsung,burst-clock-frequency = <1000000000>; 645 samsung,esc-clock-frequency = <10000000>; 646 647 ports { 648 port@1 { 649 reg = <1>; 650 651 dsi_out: endpoint { 652 remote-endpoint = <&dsi_in>; 653 data-lanes = <1 2 3 4>; 654 }; 655 }; 656 }; 657}; 658 659&pcie_phy { 660 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 661 clock-names = "ref"; 662 clocks = <&pcieclk 0>; 663}; 664 665&pcie { 666 pinctrl-names = "default"; 667 pinctrl-0 = <&pinctrl_pcie>; 668 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 669 <&clk IMX8MP_CLK_HSIO_AXI>, 670 <&clk IMX8MP_CLK_PCIE_ROOT>; 671 clock-names = "pcie", "pcie_bus", "pcie_aux"; 672 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 673 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 674 assigned-clock-rates = <10000000>; 675 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 676}; 677 678&pwm2 { 679 pinctrl-names = "default"; 680 pinctrl-0 = <&pinctrl_pwm2>; 681}; 682 683&pwm3 { 684 pinctrl-names = "default"; 685 pinctrl-0 = <&pinctrl_pwm3>; 686}; 687 688&sai3 { 689 pinctrl-names = "default"; 690 pinctrl-0 = <&pinctrl_sai3>; 691 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 692 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 693 assigned-clock-rates = <12288000>; 694}; 695 696&sai5 { 697 pinctrl-names = "default"; 698 pinctrl-0 = <&pinctrl_sai5>; 699 assigned-clocks = <&clk IMX8MP_CLK_SAI5>; 700 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 701 assigned-clock-rates = <12288000>; 702 fsl,sai-mclk-direction-output; 703}; 704 705&uart1 { 706 pinctrl-names = "default"; 707 pinctrl-0 = <&pinctrl_uart1>; 708 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 709 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 710 uart-has-rtscts; 711}; 712 713&uart2 { 714 pinctrl-names = "default"; 715 pinctrl-0 = <&pinctrl_uart2>; 716 assigned-clocks = <&clk IMX8MP_CLK_UART2>; 717 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 718 uart-has-rtscts; 719}; 720 721&uart3 { 722 /* console */ 723 pinctrl-names = "default"; 724 pinctrl-0 = <&pinctrl_uart3>; 725 status = "okay"; 726}; 727 728&uart4 { 729 pinctrl-names = "default"; 730 pinctrl-0 = <&pinctrl_uart4>; 731 assigned-clocks = <&clk IMX8MP_CLK_UART4>; 732 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 733}; 734 735&usb3_phy0 { 736 vbus-supply = <®_5v0>; 737 status = "okay"; 738}; 739 740&usb3_phy1 { 741 vbus-supply = <®_5v0>; 742 status = "okay"; 743}; 744 745&usb3_0 { 746 pinctrl-names = "default"; 747 pinctrl-0 = <&pinctrl_usb0>; 748 fsl,over-current-active-low; 749}; 750 751&usb3_1 { 752 pinctrl-names = "default"; 753 pinctrl-0 = <&pinctrl_usb1>; 754 fsl,over-current-active-low; 755 status = "okay"; 756}; 757 758&usb_dwc3_0 { 759 /* dual role is implemented, but not a full featured OTG */ 760 hnp-disable; 761 srp-disable; 762 adp-disable; 763 dr_mode = "otg"; 764 usb-role-switch; 765 role-switch-default-mode = "peripheral"; 766 /* SMARC-2 USB0 interface only supports USB 2.0 signals */ 767 maximum-speed = "high-speed"; 768}; 769 770&usb_dwc3_1 { 771 dr_mode = "host"; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 status = "okay"; 775 776 hub_2_0: hub@1 { 777 compatible = "usb451,8142"; 778 reg = <1>; 779 peer-hub = <&hub_3_0>; 780 reset-gpios = <&expander0 5 GPIO_ACTIVE_LOW>; 781 vdd-supply = <®_3v3>; 782 }; 783 784 hub_3_0: hub@2 { 785 compatible = "usb451,8140"; 786 reg = <2>; 787 peer-hub = <&hub_2_0>; 788 reset-gpios = <&expander0 5 GPIO_ACTIVE_LOW>; 789 vdd-supply = <®_3v3>; 790 }; 791}; 792 793&usdhc2 { 794 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 795 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 796 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 797 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 798 bus-width = <4>; 799 vqmmc-supply = <®_usdhc2_vqmmc>; 800 /* NOTE: CD / WP and VMMC support depends on mainboard */ 801}; 802 803&usdhc3 { 804 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 805 pinctrl-0 = <&pinctrl_usdhc3>; 806 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 807 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 808 bus-width = <8>; 809 non-removable; 810 no-sdio; 811 no-sd; 812 vmmc-supply = <&buck4>; 813 vqmmc-supply = <&buck5>; 814 status = "okay"; 815}; 816 817&wdog1 { 818 pinctrl-names = "default"; 819 pinctrl-0 = <&pinctrl_wdog>; 820 fsl,ext-reset-output; 821 status = "okay"; 822}; 823 824&iomuxc { 825 pinctrl_ecspi1: ecspi1grp { 826 fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c0>, 827 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1c0>, 828 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1c0>, 829 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c0>, 830 <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c0>; 831 }; 832 833 pinctrl_eqos: eqosgrp { 834 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>, 835 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>, 836 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, 837 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, 838 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, 839 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, 840 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, 841 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, 842 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>, 843 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>, 844 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>, 845 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>, 846 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>, 847 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>; 848 }; 849 850 pinctrl_eqos_event: eqosevtgrp { 851 fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN 0x100>, 852 <MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT 0x1c0>; 853 }; 854 855 pinctrl_eqos_phy: eqosphygrp { 856 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x1c0>; 857 }; 858 859 pinctrl_espi_rst: espirstgrp { 860 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x144>; 861 }; 862 863 pinctrl_fec: fecgrp { 864 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, 865 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, 866 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, 867 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, 868 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, 869 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, 870 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>, 871 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>, 872 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>, 873 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>, 874 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>, 875 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>; 876 }; 877 878 pinctrl_fec_event: fecevtgrp { 879 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x100>, 880 <MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1c0>; 881 }; 882 883 pinctrl_fec_phy: fecphygrp { 884 fsl,pins = <MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x1c0>; 885 }; 886 887 pinctrl_flexcan1: flexcan1grp { 888 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150>, 889 <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150>; 890 }; 891 892 pinctrl_flexcan2: flexcan2grp { 893 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x150>, 894 <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x150>; 895 }; 896 897 pinctrl_flexspi0: flexspi0grp { 898 fsl,pins = <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x142>, 899 <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, 900 <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x40000010>, 901 <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, 902 <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, 903 <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, 904 <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>; 905 }; 906 907 pinctrl_sdp: gbegrp { 908 fsl,pins = <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10>, 909 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x10>; 910 }; 911 912 pinctrl_gpio1: gpio1grp { 913 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>, 914 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>, 915 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x10>, 916 <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10>, 917 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>, 918 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80>, 919 <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x80>; 920 }; 921 922 pinctrl_gpio3: gpio3grp { 923 fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x10>, 924 <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; 925 }; 926 927 pinctrl_gpio4: gpio4grp { 928 fsl,pins = <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x10>, 929 <MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x10>, 930 <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10>, 931 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x10>, 932 <MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x10>, 933 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x10>, 934 <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x10>; 935 }; 936 937 pinctrl_gpio5: gpio5grp { 938 fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x10>, 939 <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x10>, 940 <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x10>, 941 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x10>; 942 }; 943 944 pinctrl_hdmi: hdmigrp { 945 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>, 946 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>, 947 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>; 948 }; 949 950 pinctrl_hoggpio2: hoggpio2grp { 951 fsl,pins = <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140>; 952 }; 953 954 pinctrl_i2c1: i2c1grp { 955 fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001e2>, 956 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001e2>; 957 }; 958 959 pinctrl_i2c1_gpio: i2c1-gpiogrp { 960 fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001e2>, 961 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001e2>; 962 }; 963 964 pinctrl_i2c2: i2c2grp { 965 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>, 966 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>; 967 }; 968 969 pinctrl_i2c2_gpio: i2c2-gpiogrp { 970 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>, 971 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>; 972 }; 973 974 pinctrl_i2c3: i2c3grp { 975 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001e2>, 976 <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001e2>; 977 }; 978 979 pinctrl_i2c3_gpio: i2c3-gpiogrp { 980 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001e2>, 981 <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001e2>; 982 }; 983 984 pinctrl_i2c4: i2c4grp { 985 fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 0x400001e2>, 986 <MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 0x400001e2>; 987 }; 988 989 pinctrl_i2c4_gpio: i2c4-gpiogrp { 990 fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x400001e2>, 991 <MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x400001e2>; 992 }; 993 994 pinctrl_i2c6: i2c6grp { 995 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>, 996 <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>; 997 }; 998 999 pinctrl_i2c6_gpio: i2c6-gpiogrp { 1000 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>, 1001 <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>; 1002 }; 1003 1004 pinctrl_pcf85063: pcf85063grp { 1005 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x80>; 1006 }; 1007 1008 pinctrl_pcie: pciegrp { 1009 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60>, 1010 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x94>; 1011 }; 1012 1013 pinctrl_pmic: pmicirqgrp { 1014 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x1c0>; 1015 }; 1016 1017 pinctrl_pwm2: pwm2grp { 1018 fsl,pins = <MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x14>; 1019 }; 1020 1021 pinctrl_pwm3: pwm3grp { 1022 fsl,pins = <MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x14>; 1023 }; 1024 1025 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 1026 fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x10>; 1027 }; 1028 1029 pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp { 1030 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0xc0>; 1031 }; 1032 1033 pinctrl_sai3: sai3grp { 1034 fsl,pins = < 1035 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94 1036 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94 1037 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94 1038 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94 1039 >; 1040 }; 1041 1042 pinctrl_sai5: sai5grp { 1043 fsl,pins = < 1044 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x94 1045 MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x94 1046 MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x94 1047 MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x94 1048 MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x94 1049 >; 1050 }; 1051 1052 pinctrl_tc9595: tc9595grp { 1053 fsl,pins = <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x10>; 1054 }; 1055 1056 pinctrl_tmp1075: tmp1075grp { 1057 fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x140>; 1058 }; 1059 1060 pinctrl_uart1: uart1grp { 1061 fsl,pins = <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140>, 1062 <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140>, 1063 <MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140>, 1064 <MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140>; 1065 }; 1066 1067 pinctrl_uart2: uart2grp { 1068 fsl,pins = <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140>, 1069 <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140>, 1070 <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x140>, 1071 <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x140>; 1072 }; 1073 1074 pinctrl_uart3: uart3grp { 1075 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>, 1076 <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>; 1077 }; 1078 1079 pinctrl_uart4: uart4grp { 1080 fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>, 1081 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>; 1082 }; 1083 1084 pinctrl_usb0: usb0grp { 1085 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0>, 1086 <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x1c0>; 1087 }; 1088 1089 pinctrl_usb1: usb1grp { 1090 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x1c0>, 1091 <MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x1c0>; 1092 }; 1093 1094 pinctrl_usbcon0: usb0congrp { 1095 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0>; 1096 }; 1097 1098 pinctrl_usdhc2: usdhc2grp { 1099 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>, 1100 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>, 1101 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 1102 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 1103 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 1104 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>; 1105 }; 1106 1107 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1108 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 1109 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 1110 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 1111 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 1112 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 1113 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 1114 }; 1115 1116 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1117 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 1118 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 1119 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 1120 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 1121 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 1122 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 1123 }; 1124 1125 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 1126 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>, 1127 <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c0>; 1128 }; 1129 1130 pinctrl_usdhc3: usdhc3grp { 1131 fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, 1132 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, 1133 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, 1134 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, 1135 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, 1136 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, 1137 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, 1138 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, 1139 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, 1140 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, 1141 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>, 1142 <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>; 1143 }; 1144 1145 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1146 fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, 1147 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, 1148 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, 1149 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, 1150 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, 1151 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, 1152 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, 1153 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, 1154 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, 1155 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, 1156 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>, 1157 <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>; 1158 }; 1159 1160 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1161 fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, 1162 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, 1163 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, 1164 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, 1165 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, 1166 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, 1167 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, 1168 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, 1169 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, 1170 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, 1171 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>, 1172 <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>; 1173 }; 1174 1175 pinctrl_wdog: wdoggrp { 1176 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x1c4>; 1177 }; 1178}; 1179