xref: /linux/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso (revision 0cac5ce06e524755b3dac1e0a060b05992076d93)
1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright (C) 2025 PHYTEC Messtechnik GmbH
4 */
5
6/dts-v1/;
7/plugin/;
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/clock/imx8mp-clock.h>
11#include "imx8mp-phyboard-pollux-peb-av-10.dtsi"
12
13&backlight_lvds0 {
14	brightness-levels = <0 8 16 32 64 128 255>;
15	default-brightness-level = <8>;
16	enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
17	num-interpolated-steps = <2>;
18	pwms = <&pwm4 0 50000 0>;
19	status = "okay";
20};
21
22&lcdif2 {
23	status = "okay";
24};
25
26&lvds_bridge {
27	assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
28	assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
29	/*
30	 * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
31	 * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout
32	 * engine can reach accurate pixel clock of exactly 72.4 MHz.
33	 */
34	assigned-clock-rates = <0>, <506800000>;
35	status = "okay";
36};
37
38&panel_lvds0 {
39	compatible = "edt,etml1010g3dra";
40	status = "okay";
41};
42
43&pwm4 {
44	status = "okay";
45};
46