1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2024 TechNexion Ltd. 4 * 5 * Author: Ray Chang <ray.chang@technexion.com> 6 */ 7 8#include "imx8mp.dtsi" 9 10/ { 11 chosen { 12 stdout-path = &uart2; 13 }; 14 15 i2c_0: i2c { 16 compatible = "i2c-gpio"; 17 #address-cells = <1>; 18 #size-cells = <0>; 19 clock-frequency = <100000>; 20 pinctrl-0 = <&pinctrl_i2c_brd_conf>; 21 pinctrl-names = "default"; 22 scl-gpios = <&gpio4 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 23 sda-gpios = <&gpio4 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 24 25 eeprom: eeprom@53 { 26 compatible = "atmel,24c02"; 27 reg = <0x53>; 28 pagesize = <16>; 29 }; 30 }; 31 32 memory@40000000 { 33 reg = <0x0 0x40000000 0 0xc0000000>, 34 <0x1 0x00000000 0 0xc0000000>; 35 device_type = "memory"; 36 }; 37 38 reg_usdhc2_vmmc: regulator-usdhc2 { 39 compatible = "regulator-fixed"; 40 off-on-delay-us = <12000>; 41 regulator-max-microvolt = <3300000>; 42 regulator-min-microvolt = <3300000>; 43 regulator-name = "VSD_3V3"; 44 startup-delay-us = <100>; 45 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 46 enable-active-high; 47 }; 48 49 rfkill { 50 compatible = "rfkill-gpio"; 51 name = "rfkill"; 52 pinctrl-0 = <&pinctrl_bt_ctrl>; 53 pinctrl-names = "default"; 54 radio-type = "bluetooth"; 55 shutdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 56 }; 57 58 wl_reg_on: regulator-wl-reg-on { 59 compatible = "regulator-fixed"; 60 off-on-delay-us = <20000>; 61 pinctrl-0 = <&pinctrl_wifi_ctrl>; 62 pinctrl-names = "default"; 63 regulator-max-microvolt = <3300000>; 64 regulator-min-microvolt = <3300000>; 65 regulator-name = "WL_REG_ON"; 66 startup-delay-us = <100>; 67 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 68 enable-active-high; 69 }; 70}; 71 72&A53_0 { 73 cpu-supply = <®_arm>; 74}; 75 76&A53_1 { 77 cpu-supply = <®_arm>; 78}; 79 80&A53_2 { 81 cpu-supply = <®_arm>; 82}; 83 84&A53_3 { 85 cpu-supply = <®_arm>; 86}; 87 88&ecspi1 { 89 #address-cells = <1>; 90 #size-cells = <0>; 91 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 92 num-cs = <1>; 93 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 94 pinctrl-names = "default"; 95}; 96 97&eqos { 98 phy-handle = <ðphy0>; 99 phy-mode = "rgmii-id"; 100 pinctrl-0 = <&pinctrl_eqos>; 101 pinctrl-names = "default"; 102 snps,force_thresh_dma_mode; 103 snps,mtl-rx-config = <&mtl_rx_setup>; 104 snps,mtl-tx-config = <&mtl_tx_setup>; 105 status = "okay"; 106 107 mdio { 108 compatible = "snps,dwmac-mdio"; 109 #address-cells = <1>; 110 #size-cells = <0>; 111 112 ethphy0: ethernet-phy@1 { 113 compatible = "ethernet-phy-ieee802.3-c22"; 114 reg = <1>; 115 eee-broken-1000t; 116 reset-assert-us = <35000>; 117 reset-deassert-us = <75000>; 118 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 119 realtek,clkout-disable; 120 }; 121 }; 122 123 mtl_rx_setup: rx-queues-config { 124 snps,rx-queues-to-use = <5>; 125 126 queue0 { 127 snps,dcb-algorithm; 128 snps,map-to-dma-channel = <0>; 129 snps,priority = <0x1>; 130 }; 131 132 queue1 { 133 snps,dcb-algorithm; 134 snps,map-to-dma-channel = <1>; 135 snps,priority = <0x2>; 136 }; 137 138 queue2 { 139 snps,dcb-algorithm; 140 snps,map-to-dma-channel = <2>; 141 snps,priority = <0x4>; 142 }; 143 144 queue3 { 145 snps,dcb-algorithm; 146 snps,map-to-dma-channel = <3>; 147 snps,priority = <0x8>; 148 }; 149 150 queue4 { 151 snps,dcb-algorithm; 152 snps,map-to-dma-channel = <4>; 153 snps,priority = <0xf0>; 154 }; 155 }; 156 157 mtl_tx_setup: tx-queues-config { 158 snps,tx-queues-to-use = <5>; 159 160 queue0 { 161 snps,dcb-algorithm; 162 snps,priority = <0x1>; 163 }; 164 165 queue1 { 166 snps,dcb-algorithm; 167 snps,priority = <0x2>; 168 }; 169 170 queue2 { 171 snps,dcb-algorithm; 172 snps,priority = <0x4>; 173 }; 174 175 queue3 { 176 snps,dcb-algorithm; 177 snps,priority = <0x8>; 178 }; 179 180 queue4 { 181 snps,dcb-algorithm; 182 snps,priority = <0xf0>; 183 }; 184 }; 185}; 186 187&flexcan1 { 188 pinctrl-0 = <&pinctrl_flexcan1>; 189 pinctrl-names = "default"; 190}; 191 192&flexcan2 { 193 pinctrl-0 = <&pinctrl_flexcan2>; 194 pinctrl-names = "default"; 195}; 196 197&i2c1 { 198 clock-frequency = <100000>; 199 pinctrl-0 = <&pinctrl_i2c1>; 200 pinctrl-names = "default"; 201 status = "okay"; 202 203 pmic: pmic@25 { 204 compatible = "nxp,pca9450c"; 205 reg = <0x25>; 206 interrupt-parent = <&gpio1>; 207 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_pmic>; 210 211 regulators { 212 BUCK1 { 213 regulator-always-on; 214 regulator-boot-on; 215 regulator-max-microvolt = <1000000>; 216 regulator-min-microvolt = <720000>; 217 regulator-name = "BUCK1"; 218 regulator-ramp-delay = <3125>; 219 }; 220 221 reg_arm: BUCK2 { 222 regulator-always-on; 223 regulator-boot-on; 224 regulator-max-microvolt = <1025000>; 225 regulator-min-microvolt = <720000>; 226 regulator-name = "BUCK2"; 227 regulator-ramp-delay = <3125>; 228 nxp,dvs-run-voltage = <950000>; 229 nxp,dvs-standby-voltage = <850000>; 230 }; 231 232 BUCK4 { 233 regulator-always-on; 234 regulator-boot-on; 235 regulator-max-microvolt = <3600000>; 236 regulator-min-microvolt = <3000000>; 237 regulator-name = "BUCK4"; 238 }; 239 240 reg_buck5: BUCK5 { 241 regulator-always-on; 242 regulator-boot-on; 243 regulator-max-microvolt = <1950000>; 244 regulator-min-microvolt = <1650000>; 245 regulator-name = "BUCK5"; 246 }; 247 248 BUCK6 { 249 regulator-always-on; 250 regulator-boot-on; 251 regulator-max-microvolt = <1155000>; 252 regulator-min-microvolt = <1045000>; 253 regulator-name = "BUCK6"; 254 }; 255 256 LDO1 { 257 regulator-always-on; 258 regulator-boot-on; 259 regulator-max-microvolt = <1950000>; 260 regulator-min-microvolt = <1650000>; 261 regulator-name = "LDO1"; 262 }; 263 264 LDO3 { 265 regulator-always-on; 266 regulator-boot-on; 267 regulator-max-microvolt = <1890000>; 268 regulator-min-microvolt = <1710000>; 269 regulator-name = "LDO3"; 270 }; 271 272 LDO5 { 273 regulator-always-on; 274 regulator-boot-on; 275 regulator-max-microvolt = <3300000>; 276 regulator-min-microvolt = <1800000>; 277 regulator-name = "LDO5"; 278 }; 279 }; 280 }; 281}; 282 283&i2c2 { 284 /* I2C_B on EDMG */ 285 clock-frequency = <400000>; 286 pinctrl-0 = <&pinctrl_i2c2>; 287 pinctrl-names = "default"; 288}; 289 290&i2c3 { 291 clock-frequency = <100000>; 292 pinctrl-0 = <&pinctrl_i2c3>; 293 pinctrl-names = "default"; 294}; 295 296&i2c4 { 297 /* I2C_A on EDMG */ 298 clock-frequency = <100000>; 299 pinctrl-0 = <&pinctrl_i2c4>; 300 pinctrl-names = "default"; 301}; 302 303&i2c5 { 304 /* I2C_C on EDMG */ 305 clock-frequency = <400000>; 306 pinctrl-0 = <&pinctrl_i2c5>; 307 pinctrl-names = "default"; 308}; 309 310&pcie { 311 pinctrl-0 = <&pinctrl_pcie>; 312 pinctrl-names = "default"; 313 reset-gpio = <&gpio1 1 GPIO_ACTIVE_LOW>; 314}; 315 316&pwm1 { 317 pinctrl-0 = <&pinctrl_pwm1>; 318 pinctrl-names = "default"; 319 status = "okay"; 320}; 321 322&pwm2 { 323 pinctrl-0 = <&pinctrl_pwm2>; 324 pinctrl-names = "default"; 325 status = "okay"; 326}; 327 328&pwm3 { 329 pinctrl-0 = <&pinctrl_pwm3>; 330 pinctrl-names = "default"; 331 status = "okay"; 332}; 333 334&pwm4 { 335 pinctrl-0 = <&pinctrl_pwm4>; 336 pinctrl-names = "default"; 337 status = "okay"; 338}; 339 340&sai2 { 341 /* AUD_B on EDMG */ 342 assigned-clocks = <&clk IMX8MP_CLK_SAI2>; 343 assigned-clock-rates = <12288000>; 344 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 345 pinctrl-0 = <&pinctrl_sai2>; 346 pinctrl-names = "default"; 347 fsl,sai-mclk-direction-output; 348 status = "okay"; 349}; 350 351&sai3 { 352 /* AUD_A on EDMG */ 353 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 354 assigned-clock-rates = <12288000>; 355 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 356 pinctrl-0 = <&pinctrl_sai3>; 357 pinctrl-names = "default"; 358 fsl,sai-mclk-direction-output; 359 status = "okay"; 360}; 361 362&uart1 { 363 /* BT */ 364 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 365 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 366 pinctrl-0 = <&pinctrl_uart1>; 367 pinctrl-names = "default"; 368 uart-has-rtscts; 369 status = "okay"; 370}; 371 372&uart2 { 373 /* UART_A on EDMG, console */ 374 pinctrl-0 = <&pinctrl_uart2>; 375 pinctrl-names = "default"; 376 status = "okay"; 377}; 378 379&uart3 { 380 /* UART_C on EDMG */ 381 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 382 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 383 pinctrl-0 = <&pinctrl_uart3>; 384 pinctrl-names = "default"; 385 uart-has-rtscts; 386 status = "okay"; 387}; 388 389&uart4 { 390 /* UART_B on EDMG */ 391 assigned-clocks = <&clk IMX8MP_CLK_UART4>; 392 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 393 pinctrl-0 = <&pinctrl_uart4>; 394 pinctrl-names = "default"; 395 uart-has-rtscts; 396 status = "okay"; 397}; 398 399&usdhc1 { 400 /* WIFI SDIO */ 401 assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; 402 assigned-clock-rates = <200000000>; 403 bus-width = <4>; 404 keep-power-in-suspend; 405 non-removable; 406 pinctrl-0 = <&pinctrl_usdhc1>; 407 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 408 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 409 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 410 vmmc-supply = <&wl_reg_on>; 411 status = "okay"; 412}; 413 414&usdhc2 { 415 /* SD card on baseboard */ 416 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 417 assigned-clock-rates = <400000000>; 418 bus-width = <4>; 419 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 420 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 421 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 422 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 423 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 424 vmmc-supply = <®_usdhc2_vmmc>; 425 status = "okay"; 426}; 427 428&usdhc3 { 429 /* eMMC on SOM */ 430 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 431 assigned-clock-rates = <400000000>; 432 bus-width = <8>; 433 non-removable; 434 pinctrl-0 = <&pinctrl_usdhc3>; 435 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 436 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 437 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 438 status = "okay"; 439}; 440 441&wdog1 { 442 pinctrl-0 = <&pinctrl_wdog>; 443 pinctrl-names = "default"; 444 fsl,ext-reset-output; 445 status = "okay"; 446}; 447 448&iomuxc { 449 pinctrl-0 = <&pinctrl_hog>; 450 pinctrl-names = "default"; 451 452 pinctrl_bt_ctrl: bt-ctrlgrp { 453 fsl,pins = < 454 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x41 /* BT_REG_ON */ 455 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x41 /* BT_WAKE_HOST */ 456 >; 457 }; 458 459 pinctrl_ecspi1_cs: ecspi1csgrp { 460 fsl,pins = < 461 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40000 462 >; 463 }; 464 465 pinctrl_ecspi1: ecspi1grp { 466 fsl,pins = < 467 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 468 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 469 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 470 >; 471 }; 472 473 pinctrl_eqos: eqosgrp { 474 fsl,pins = < 475 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 476 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x23 477 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 478 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 479 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 480 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 481 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 482 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 483 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 484 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 485 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 486 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 487 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 488 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 489 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x19 490 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19 491 >; 492 }; 493 494 pinctrl_flexcan1: flexcan1grp { 495 fsl,pins = < 496 MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 497 MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 498 >; 499 }; 500 501 pinctrl_flexcan2: flexcan2grp { 502 fsl,pins = < 503 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 504 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 505 >; 506 }; 507 508 pinctrl_hog: hoggrp { 509 fsl,pins = < 510 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 511 >; 512 }; 513 514 pinctrl_i2c1: i2c1grp { 515 fsl,pins = < 516 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001a3 517 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001a3 518 >; 519 }; 520 521 pinctrl_i2c2: i2c2grp { 522 fsl,pins = < 523 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001a3 524 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001a3 525 >; 526 }; 527 528 pinctrl_i2c3: i2c3grp { 529 fsl,pins = < 530 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 531 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 532 >; 533 }; 534 535 pinctrl_i2c4: i2c4grp { 536 fsl,pins = < 537 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 538 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 539 >; 540 }; 541 542 pinctrl_i2c5: i2c5grp { 543 fsl,pins = < 544 MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001a3 545 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001a3 546 >; 547 }; 548 549 pinctrl_i2c_brd_conf: i2cbrdconfgrp { 550 fsl,pins = < 551 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c3 /* BRD_CONF_SCL, bitbang */ 552 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c3 /* BRD_CONF_SDA, bitbang */ 553 >; 554 }; 555 556 pinctrl_pcie: pciegrp { 557 fsl,pins = < 558 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x41 /* PCIE CLKREQ */ 559 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x41 /* PCIE WAKE */ 560 MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x41 /* PCIE RST */ 561 >; 562 }; 563 564 pinctrl_pmic: pmicirqgrp { 565 fsl,pins = < 566 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 567 >; 568 }; 569 570 pinctrl_pwm1: pwm1grp { 571 fsl,pins = < 572 MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116 573 >; 574 }; 575 576 pinctrl_pwm2: pwm2grp { 577 fsl,pins = < 578 MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116 579 >; 580 }; 581 582 pinctrl_pwm3: pwm3grp { 583 fsl,pins = < 584 MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116 585 >; 586 }; 587 588 pinctrl_pwm4: pwm4grp { 589 fsl,pins = < 590 MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 591 >; 592 }; 593 594 pinctrl_sai2: sai2grp { 595 fsl,pins = < 596 MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 597 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 598 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 599 MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 600 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 601 >; 602 }; 603 604 pinctrl_sai3: sai3grp { 605 fsl,pins = < 606 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 607 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 608 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 609 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 610 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 611 >; 612 }; 613 614 pinctrl_uart1: uart1grp { 615 fsl,pins = < 616 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 617 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 618 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 619 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 620 >; 621 }; 622 623 pinctrl_uart2: uart2grp { 624 fsl,pins = < 625 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 626 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 627 MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x140 628 MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x140 629 >; 630 }; 631 632 pinctrl_uart3: uart3grp { 633 fsl,pins = < 634 MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140 635 MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140 636 MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140 637 MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x140 638 >; 639 }; 640 641 pinctrl_uart4: uart4grp { 642 fsl,pins = < 643 MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x140 644 MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x140 645 MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x140 646 MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x140 647 >; 648 }; 649 650 pinctrl_usdhc1: usdhc1grp { 651 fsl,pins = < 652 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 653 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 654 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 655 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 656 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 657 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 658 >; 659 }; 660 661 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 662 fsl,pins = < 663 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 664 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 665 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 666 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 667 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 668 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 669 >; 670 }; 671 672 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 673 fsl,pins = < 674 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 675 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 676 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 677 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 678 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 679 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 680 >; 681 }; 682 683 pinctrl_usdhc2: usdhc2grp { 684 fsl,pins = < 685 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 686 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 687 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 688 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 689 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 690 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 691 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 692 >; 693 }; 694 695 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 696 fsl,pins = < 697 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 698 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 699 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 700 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 701 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 702 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 703 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 704 >; 705 }; 706 707 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 708 fsl,pins = < 709 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 710 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 711 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 712 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 713 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 714 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 715 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 716 >; 717 }; 718 719 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 720 fsl,pins = < 721 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 722 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 723 >; 724 }; 725 726 pinctrl_usdhc3: usdhc3grp { 727 fsl,pins = < 728 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 729 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 730 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 731 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 732 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 733 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 734 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 735 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 736 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 737 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 738 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 739 >; 740 }; 741 742 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 743 fsl,pins = < 744 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 745 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 746 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 747 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 748 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 749 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 750 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 751 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 752 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 753 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 754 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 755 >; 756 }; 757 758 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 759 fsl,pins = < 760 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 761 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 762 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 763 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 764 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 765 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 766 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 767 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 768 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 769 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 770 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 771 >; 772 }; 773 774 pinctrl_wdog: wdoggrp { 775 fsl,pins = < 776 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 777 >; 778 }; 779 780 pinctrl_wifi_ctrl: wifi-ctrlgrp { 781 fsl,pins = < 782 MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x41 /* WL_REG_ON */ 783 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x41 /* WL_WAKE_HOST */ 784 >; 785 }; 786}; 787