xref: /linux/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-clock.dtsi (revision b2128290c29902315e632ea59e0504d6bc9e9b42)
1*bb020f38SMarek Vasut// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*bb020f38SMarek Vasut/*
3*bb020f38SMarek Vasut * Copyright (C) 2024-2026 Marek Vasut
4*bb020f38SMarek Vasut */
5*bb020f38SMarek Vasut
6*bb020f38SMarek Vasut#include <dt-bindings/clock/imx8mp-clock.h>
7*bb020f38SMarek Vasut
8*bb020f38SMarek Vasut&media_blk_ctrl {
9*bb020f38SMarek Vasut	/*
10*bb020f38SMarek Vasut	 * Sys PLL3 supplies TC9595 RefClk
11*bb020f38SMarek Vasut	 * Audio PLL2 supplies MEDIA_DISP1_PIX (DSI)
12*bb020f38SMarek Vasut	 * Video PLL1 supplies MEDIA_DISP2_PIX (LVDS)
13*bb020f38SMarek Vasut	 */
14*bb020f38SMarek Vasut	assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
15*bb020f38SMarek Vasut			  <&clk IMX8MP_CLK_MEDIA_APB>,
16*bb020f38SMarek Vasut			  <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
17*bb020f38SMarek Vasut			  <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
18*bb020f38SMarek Vasut			  <&clk IMX8MP_AUDIO_PLL2>,
19*bb020f38SMarek Vasut			  <&clk IMX8MP_VIDEO_PLL1>;
20*bb020f38SMarek Vasut	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
21*bb020f38SMarek Vasut				 <&clk IMX8MP_SYS_PLL1_800M>,
22*bb020f38SMarek Vasut				 <&clk IMX8MP_AUDIO_PLL2_OUT>,
23*bb020f38SMarek Vasut				 <&clk IMX8MP_VIDEO_PLL1_OUT>;
24*bb020f38SMarek Vasut	assigned-clock-rates = <500000000>, <200000000>,
25*bb020f38SMarek Vasut			       <0>, <0>, <0>, <0>;
26*bb020f38SMarek Vasut};
27*bb020f38SMarek Vasut
28*bb020f38SMarek Vasut&tc_bridge {
29*bb020f38SMarek Vasut	assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>,
30*bb020f38SMarek Vasut			  <&clk IMX8MP_CLK_CLKOUT2>,
31*bb020f38SMarek Vasut			  <&clk IMX8MP_SYS_PLL3_OUT>;
32*bb020f38SMarek Vasut	assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>;
33*bb020f38SMarek Vasut};
34