xref: /linux/arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-clock.dtsi (revision b2128290c29902315e632ea59e0504d6bc9e9b42)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2024-2026 Marek Vasut
4 */
5
6#include <dt-bindings/clock/imx8mp-clock.h>
7
8&media_blk_ctrl {
9	/*
10	 * Sys PLL3 supplies TC9595 RefClk
11	 * Audio PLL2 supplies MEDIA_DISP1_PIX (DSI)
12	 * Video PLL1 supplies MEDIA_DISP2_PIX (LVDS)
13	 */
14	assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
15			  <&clk IMX8MP_CLK_MEDIA_APB>,
16			  <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
17			  <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
18			  <&clk IMX8MP_AUDIO_PLL2>,
19			  <&clk IMX8MP_VIDEO_PLL1>;
20	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
21				 <&clk IMX8MP_SYS_PLL1_800M>,
22				 <&clk IMX8MP_AUDIO_PLL2_OUT>,
23				 <&clk IMX8MP_VIDEO_PLL1_OUT>;
24	assigned-clock-rates = <500000000>, <200000000>,
25			       <0>, <0>, <0>, <0>;
26};
27
28&tc_bridge {
29	assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>,
30			  <&clk IMX8MP_CLK_CLKOUT2>,
31			  <&clk IMX8MP_SYS_PLL3_OUT>;
32	assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>;
33};
34