1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2020-2026 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx8mp.dtsi" 10 11/ { 12 compatible = "fsl,imx8mp-ab2", "fsl,imx8mp"; 13 model = "NXP i.MX8MP SOM on AB2"; 14 15 chosen { 16 stdout-path = &uart2; 17 }; 18 19 gpio-leds { 20 compatible = "gpio-leds"; 21 pinctrl-0 = <&pinctrl_gpio_led>; 22 pinctrl-names = "default"; 23 24 status { 25 default-state = "on"; 26 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 27 label = "yellow:status"; 28 }; 29 }; 30 31 native-hdmi-connector { 32 compatible = "hdmi-connector"; 33 label = "HDMI OUT"; 34 type = "a"; 35 36 port { 37 hdmi_in: endpoint { 38 remote-endpoint = <&hdmi_tx_out>; 39 }; 40 }; 41 }; 42 43 reg_ab2_ana_pwr: regulator-ab2-ana-pwr { 44 compatible = "regulator-fixed"; 45 regulator-name = "ab2_ana_pwr"; 46 pinctrl-0 = <&pinctrl_ab2_ana_pwr>; 47 pinctrl-names = "default"; 48 regulator-always-on; 49 regulator-max-microvolt = <3300000>; 50 regulator-min-microvolt = <3300000>; 51 gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; 52 enable-active-high; 53 }; 54 55 reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { 56 compatible = "regulator-fixed"; 57 regulator-name = "ab2_vdd_pwr_5v0"; 58 pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; 59 pinctrl-names = "default"; 60 regulator-always-on; 61 regulator-max-microvolt = <3300000>; 62 regulator-min-microvolt = <3300000>; 63 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 64 enable-active-high; 65 }; 66 67 reg_usdhc2_vmmc: regulator-usdhc2 { 68 compatible = "regulator-fixed"; 69 regulator-name = "VSD_3V3"; 70 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 71 pinctrl-names = "default"; 72 regulator-max-microvolt = <3300000>; 73 regulator-min-microvolt = <3300000>; 74 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 75 enable-active-high; 76 }; 77 78 reserved-memory { 79 ranges; 80 #address-cells = <2>; 81 #size-cells = <2>; 82 83 dsp_vdev0vring0: vdev0vring0@942f0000 { 84 reg = <0 0x942f0000 0 0x8000>; 85 no-map; 86 }; 87 88 dsp_vdev0vring1: vdev0vring1@942f8000 { 89 reg = <0 0x942f8000 0 0x8000>; 90 no-map; 91 }; 92 93 dsp_vdev0buffer: vdev0buffer@94300000 { 94 compatible = "shared-dma-pool"; 95 reg = <0 0x94300000 0 0x100000>; 96 no-map; 97 }; 98 }; 99 100 sound-ak4458 { 101 compatible = "fsl,imx-audio-card"; 102 model = "ak4458-audio"; 103 104 pri-dai-link { 105 format = "i2s"; 106 link-name = "akcodec"; 107 fsl,mclk-equal-bclk; 108 109 codec { 110 sound-dai = <&ak4458_1>, <&ak4458_2>; 111 }; 112 113 cpu { 114 sound-dai = <&sai1>; 115 }; 116 }; 117 }; 118 119 sound-ak5552 { 120 compatible = "fsl,imx-audio-card"; 121 model = "ak5552-audio"; 122 123 pri-dai-link { 124 format = "i2s"; 125 link-name = "akcodec"; 126 fsl,mclk-equal-bclk; 127 128 codec { 129 sound-dai = <&ak5552>; 130 }; 131 132 cpu { 133 sound-dai = <&sai3>; 134 }; 135 }; 136 }; 137 138 sound-hdmi { 139 compatible = "fsl,imx-audio-hdmi"; 140 audio-cpu = <&aud2htx>; 141 hdmi-out; 142 model = "audio-hdmi"; 143 }; 144 145 sound-micfil { 146 compatible = "fsl,imx-audio-card"; 147 model = "micfil-audio"; 148 149 pri-dai-link { 150 format = "i2s"; 151 link-name = "micfil hifi"; 152 153 cpu { 154 sound-dai = <&micfil>; 155 }; 156 }; 157 }; 158 159 sound-xcvr { 160 compatible = "fsl,imx-audio-card"; 161 model = "imx-audio-xcvr"; 162 163 pri-dai-link { 164 link-name = "XCVR PCM"; 165 166 cpu { 167 sound-dai = <&xcvr>; 168 }; 169 }; 170 }; 171 172 memory@40000000 { 173 reg = <0x0 0x40000000 0 0xc0000000>, 174 <0x1 0x00000000 0 0xc0000000>; 175 device_type = "memory"; 176 }; 177}; 178 179&A53_0 { 180 cpu-supply = <&buck2>; 181}; 182 183&A53_1 { 184 cpu-supply = <&buck2>; 185}; 186 187&A53_2 { 188 cpu-supply = <&buck2>; 189}; 190 191&A53_3 { 192 cpu-supply = <&buck2>; 193}; 194 195&aud2htx { 196 status = "okay"; 197}; 198 199&dsp { 200 memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, 201 <&dsp_vdev0vring1>, <&dsp_reserved>; 202 status = "okay"; 203}; 204 205&dsp_reserved { 206 status = "okay"; 207}; 208 209&easrc { 210 #sound-dai-cells = <0>; 211 fsl,asrc-rate = <48000>; 212 status = "okay"; 213}; 214 215&eqos { 216 phy-handle = <ðphy0>; 217 phy-mode = "rgmii-id"; 218 pinctrl-0 = <&pinctrl_eqos>; 219 pinctrl-names = "default"; 220 status = "okay"; 221 222 mdio { 223 compatible = "snps,dwmac-mdio"; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 227 ethphy0: ethernet-phy@1 { 228 compatible = "ethernet-phy-ieee802.3-c22"; 229 reg = <1>; 230 }; 231 }; 232}; 233 234&flexspi { 235 pinctrl-0 = <&pinctrl_flexspi0>; 236 pinctrl-names = "default"; 237 status = "okay"; 238 239 mt25qu256aba: flash@0 { 240 compatible = "jedec,spi-nor"; 241 reg = <0>; 242 spi-max-frequency = <80000000>; 243 spi-rx-bus-width = <4>; 244 spi-tx-bus-width = <1>; 245 }; 246}; 247 248&hdmi_pai { 249 status = "okay"; 250}; 251 252&hdmi_pvi { 253 status = "okay"; 254}; 255 256&hdmi_tx { 257 pinctrl-0 = <&pinctrl_hdmi>; 258 pinctrl-names = "default"; 259 status = "okay"; 260 261 ports { 262 port@1 { 263 hdmi_tx_out: endpoint { 264 remote-endpoint = <&hdmi_in>; 265 }; 266 }; 267 }; 268}; 269 270&hdmi_tx_phy { 271 status = "okay"; 272}; 273 274&i2c1 { 275 clock-frequency = <400000>; 276 pinctrl-0 = <&pinctrl_i2c1>; 277 pinctrl-names = "default"; 278 status = "okay"; 279 280 pca9450: pmic@25 { 281 compatible = "nxp,pca9450c"; 282 reg = <0x25>; 283 interrupt-parent = <&gpio1>; 284 interrupts = <3 GPIO_ACTIVE_LOW>; 285 pinctrl-0 = <&pinctrl_pmic>; 286 287 regulators { 288 buck1: BUCK1 { 289 regulator-name = "BUCK1"; 290 regulator-always-on; 291 regulator-boot-on; 292 regulator-max-microvolt = <2187500>; 293 regulator-min-microvolt = <600000>; 294 regulator-ramp-delay = <3125>; 295 }; 296 297 buck2: BUCK2 { 298 regulator-name = "BUCK2"; 299 regulator-always-on; 300 regulator-boot-on; 301 regulator-max-microvolt = <2187500>; 302 regulator-min-microvolt = <600000>; 303 regulator-ramp-delay = <3125>; 304 nxp,dvs-run-voltage = <950000>; 305 nxp,dvs-standby-voltage = <850000>; 306 }; 307 308 buck4: BUCK4 { 309 regulator-name = "BUCK4"; 310 regulator-always-on; 311 regulator-boot-on; 312 regulator-max-microvolt = <3400000>; 313 regulator-min-microvolt = <600000>; 314 }; 315 316 buck5: BUCK5 { 317 regulator-name = "BUCK5"; 318 regulator-always-on; 319 regulator-boot-on; 320 regulator-max-microvolt = <3400000>; 321 regulator-min-microvolt = <600000>; 322 }; 323 324 buck6: BUCK6 { 325 regulator-name = "BUCK6"; 326 regulator-always-on; 327 regulator-boot-on; 328 regulator-max-microvolt = <3400000>; 329 regulator-min-microvolt = <600000>; 330 }; 331 332 ldo1: LDO1 { 333 regulator-name = "LDO1"; 334 regulator-always-on; 335 regulator-boot-on; 336 regulator-max-microvolt = <3300000>; 337 regulator-min-microvolt = <1600000>; 338 }; 339 340 ldo2: LDO2 { 341 regulator-name = "LDO2"; 342 regulator-always-on; 343 regulator-boot-on; 344 regulator-max-microvolt = <1150000>; 345 regulator-min-microvolt = <800000>; 346 }; 347 348 ldo3: LDO3 { 349 regulator-name = "LDO3"; 350 regulator-always-on; 351 regulator-boot-on; 352 regulator-max-microvolt = <3300000>; 353 regulator-min-microvolt = <800000>; 354 }; 355 356 ldo4: LDO4 { 357 regulator-name = "LDO4"; 358 regulator-always-on; 359 regulator-boot-on; 360 regulator-max-microvolt = <3300000>; 361 regulator-min-microvolt = <800000>; 362 }; 363 364 ldo5: LDO5 { 365 regulator-name = "LDO5"; 366 regulator-always-on; 367 regulator-boot-on; 368 regulator-max-microvolt = <3300000>; 369 regulator-min-microvolt = <1800000>; 370 }; 371 }; 372 }; 373}; 374 375&i2c2 { 376 clock-frequency = <100000>; 377 pinctrl-0 = <&pinctrl_i2c2>; 378 pinctrl-names = "default"; 379 status = "okay"; 380 381 pca6408: gpio@20 { 382 compatible = "ti,tca6408"; 383 reg = <0x20>; 384 #gpio-cells = <2>; 385 gpio-controller; 386 }; 387 388 pca6416_2: gpio@21 { 389 compatible = "ti,tca6416"; 390 reg = <0x21>; 391 #gpio-cells = <2>; 392 gpio-controller; 393 }; 394}; 395 396&i2c3 { 397 clock-frequency = <400000>; 398 pinctrl-0 = <&pinctrl_i2c3>; 399 pinctrl-names = "default"; 400 status = "okay"; 401 402 ak4458_1: audio-codec@10 { 403 compatible = "asahi-kasei,ak4458"; 404 reg = <0x10>; 405 #sound-dai-cells = <0>; 406 AVDD-supply = <®_ab2_ana_pwr>; 407 DVDD-supply = <®_ab2_ana_pwr>; 408 reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; 409 sound-name-prefix = "0"; 410 }; 411 412 ak4458_2: audio-codec@11 { 413 compatible = "asahi-kasei,ak4458"; 414 reg = <0x11>; 415 #sound-dai-cells = <0>; 416 AVDD-supply = <®_ab2_ana_pwr>; 417 DVDD-supply = <®_ab2_ana_pwr>; 418 reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; 419 sound-name-prefix = "1"; 420 }; 421 422 ak4458_3: audio-codec@12 { 423 compatible = "asahi-kasei,ak4458"; 424 reg = <0x12>; 425 #sound-dai-cells = <0>; 426 AVDD-supply = <®_ab2_ana_pwr>; 427 DVDD-supply = <®_ab2_ana_pwr>; 428 reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; 429 }; 430 431 ak5552: audio-codec@13 { 432 compatible = "asahi-kasei,ak5552"; 433 reg = <0x13>; 434 #sound-dai-cells = <0>; 435 AVDD-supply = <®_ab2_ana_pwr>; 436 DVDD-supply = <®_ab2_ana_pwr>; 437 reset-gpios = <&pca6416 2 GPIO_ACTIVE_LOW>; 438 }; 439 440 pca6416: gpio@20 { 441 compatible = "ti,tca6416"; 442 reg = <0x20>; 443 #gpio-cells = <2>; 444 gpio-controller; 445 }; 446}; 447 448&iomuxc { 449 pinctrl-0 = <&pinctrl_hog>; 450 pinctrl-names = "default"; 451 452 pinctrl_ab2_ana_pwr: ab2anapwrgrp { 453 fsl,pins = < 454 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0xd6 455 >; 456 }; 457 458 pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { 459 fsl,pins = < 460 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0xd6 461 >; 462 }; 463 464 pinctrl_eqos: eqosgrp { 465 fsl,pins = < 466 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 467 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 468 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 469 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 470 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 471 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 472 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 473 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 474 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 475 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 476 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 477 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 478 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 479 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 480 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 481 >; 482 }; 483 484 pinctrl_flexspi0: flexspi0grp { 485 fsl,pins = < 486 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 487 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 488 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 489 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 490 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 491 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 492 >; 493 }; 494 495 pinctrl_gpio_led: gpioledgrp { 496 fsl,pins = < 497 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x10 498 >; 499 }; 500 501 pinctrl_hdmi: hdmigrp { 502 fsl,pins = < 503 MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 504 MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 505 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 506 >; 507 }; 508 509 pinctrl_hog: hoggrp { 510 fsl,pins = < 511 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 512 >; 513 }; 514 515 pinctrl_i2c1: i2c1grp { 516 fsl,pins = < 517 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 518 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 519 >; 520 }; 521 522 pinctrl_i2c2: i2c2grp { 523 fsl,pins = < 524 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 525 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 526 >; 527 }; 528 529 pinctrl_i2c3: i2c3grp { 530 fsl,pins = < 531 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 532 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 533 >; 534 }; 535 536 pinctrl_pdm: pdmgrp { 537 fsl,pins = < 538 MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 539 MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 540 MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 541 MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 542 MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 543 >; 544 }; 545 546 pinctrl_pmic: pmicgrp { 547 fsl,pins = < 548 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 549 >; 550 }; 551 552 pinctrl_pwm1: pwm1grp { 553 fsl,pins = < 554 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 555 >; 556 }; 557 558 pinctrl_pwm2: pwm2grp { 559 fsl,pins = < 560 MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 561 >; 562 }; 563 564 pinctrl_pwm4: pwm4grp { 565 fsl,pins = < 566 MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 567 >; 568 }; 569 570 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 571 fsl,pins = < 572 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 573 >; 574 }; 575 576 pinctrl_sai1: sai1grp { 577 fsl,pins = < 578 MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6 579 MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0xd6 580 MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0xd6 581 MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0xd6 582 MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0xd6 583 MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0xd6 584 MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0xd6 585 MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0xd6 586 MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0xd6 587 MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0xd6 588 MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0xd6 589 >; 590 }; 591 592 pinctrl_sai3: sai3grp { 593 fsl,pins = < 594 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 595 MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6 596 MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6 597 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 598 >; 599 }; 600 601 pinctrl_uart1: uart1grp { 602 fsl,pins = < 603 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 604 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 605 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 606 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 607 >; 608 }; 609 610 pinctrl_uart2: uart2grp { 611 fsl,pins = < 612 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 613 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 614 >; 615 }; 616 617 pinctrl_uart3: uart3grp { 618 fsl,pins = < 619 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 620 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 621 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 622 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 623 >; 624 }; 625 626 pinctrl_usdhc1: usdhc1grp { 627 fsl,pins = < 628 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 629 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 630 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 631 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 632 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 633 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 634 >; 635 }; 636 637 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 638 fsl,pins = < 639 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 640 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 641 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 642 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 643 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 644 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 645 >; 646 }; 647 648 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 649 fsl,pins = < 650 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 651 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 652 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 653 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 654 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 655 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 656 >; 657 }; 658 659 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 660 fsl,pins = < 661 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 662 >; 663 }; 664 665 pinctrl_usdhc2: usdhc2grp { 666 fsl,pins = < 667 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 668 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 669 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 670 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 671 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 672 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 673 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 674 >; 675 }; 676 677 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 678 fsl,pins = < 679 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 680 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 681 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 682 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 683 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 684 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 685 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 686 >; 687 }; 688 689 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 690 fsl,pins = < 691 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 692 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 693 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 694 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 695 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 696 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 697 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 698 >; 699 }; 700 701 pinctrl_usdhc3: usdhc3grp { 702 fsl,pins = < 703 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 704 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 705 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 706 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 707 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 708 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 709 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 710 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 711 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 712 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 713 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 714 >; 715 }; 716 717 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 718 fsl,pins = < 719 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 720 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 721 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 722 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 723 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 724 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 725 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 726 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 727 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 728 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 729 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 730 >; 731 }; 732 733 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 734 fsl,pins = < 735 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 736 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 737 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 738 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 739 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 740 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 741 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 742 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 743 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 744 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 745 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 746 >; 747 }; 748 749 pinctrl_wdog: wdoggrp { 750 fsl,pins = < 751 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 752 >; 753 }; 754 755 pinctrl_xcvr: xcvrgrp { 756 fsl,pins = < 757 MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK 0xd6 758 MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0xd6 759 MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0xd6 760 >; 761 }; 762}; 763 764&lcdif3 { 765 status = "okay"; 766}; 767 768&micfil { 769 assigned-clocks = <&clk IMX8MP_CLK_PDM>; 770 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 771 assigned-clock-rates = <196608000>; 772 #sound-dai-cells = <0>; 773 pinctrl-0 = <&pinctrl_pdm>; 774 pinctrl-names = "default"; 775 status = "okay"; 776}; 777 778&pwm1 { 779 pinctrl-0 = <&pinctrl_pwm1>; 780 pinctrl-names = "default"; 781 status = "okay"; 782}; 783 784&pwm2 { 785 pinctrl-0 = <&pinctrl_pwm2>; 786 pinctrl-names = "default"; 787 status = "okay"; 788}; 789 790&pwm4 { 791 pinctrl-0 = <&pinctrl_pwm4>; 792 pinctrl-names = "default"; 793 status = "okay"; 794}; 795 796&sai1 { 797 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>, 798 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, 799 <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, 800 <&clk IMX8MP_AUDIO_PLL2_OUT>; 801 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; 802 assigned-clocks = <&clk IMX8MP_CLK_SAI1>; 803 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 804 assigned-clock-rates = <49152000>; 805 dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; 806 #sound-dai-cells = <0>; 807 pinctrl-0 = <&pinctrl_sai1>; 808 pinctrl-names = "default"; 809 fsl,dataline = <2 0xff 0xff>; 810 fsl,sai-mclk-direction-output; 811 status = "okay"; 812}; 813 814&sai3 { 815 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, 816 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, 817 <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, 818 <&clk IMX8MP_AUDIO_PLL2_OUT>; 819 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; 820 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 821 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 822 assigned-clock-rates = <49152000>; 823 #sound-dai-cells = <0>; 824 pinctrl-0 = <&pinctrl_sai3>; 825 pinctrl-names = "default"; 826 fsl,sai-asynchronous; 827 fsl,sai-mclk-direction-output; 828 status = "okay"; 829}; 830 831&sdma2 { 832 status = "okay"; 833}; 834 835&snvs_pwrkey { 836 status = "okay"; 837}; 838 839&uart1 { 840 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 841 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 842 pinctrl-0 = <&pinctrl_uart1>; 843 pinctrl-names = "default"; 844 uart-has-rtscts; 845 status = "okay"; 846}; 847 848&uart2 { 849 pinctrl-0 = <&pinctrl_uart2>; 850 pinctrl-names = "default"; 851 status = "okay"; 852}; 853 854&uart3 { 855 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 856 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 857 pinctrl-0 = <&pinctrl_uart3>; 858 pinctrl-names = "default"; 859 uart-has-rtscts; 860 status = "okay"; 861}; 862 863&usdhc1 { 864 assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; 865 assigned-clock-rates = <400000000>; 866 bus-width = <4>; 867 non-removable; 868 pinctrl-0 = <&pinctrl_usdhc1>; 869 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 870 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 871 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 872 status = "okay"; 873}; 874 875&usdhc2 { 876 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 877 assigned-clock-rates = <400000000>; 878 bus-width = <4>; 879 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 880 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 881 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 882 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 883 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 884 vmmc-supply = <®_usdhc2_vmmc>; 885 status = "okay"; 886}; 887 888&usdhc3 { 889 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 890 assigned-clock-rates = <400000000>; 891 bus-width = <8>; 892 non-removable; 893 pinctrl-0 = <&pinctrl_usdhc3>; 894 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 895 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 896 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 897 status = "okay"; 898}; 899 900&wdog1 { 901 pinctrl-0 = <&pinctrl_wdog>; 902 pinctrl-names = "default"; 903 fsl,ext-reset-output; 904 status = "okay"; 905}; 906 907&xcvr { 908 #sound-dai-cells = <0>; 909 pinctrl-0 = <&pinctrl_xcvr>; 910 pinctrl-names = "default"; 911 status = "okay"; 912}; 913