1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Common dtsi for Variscite DART-MX8M-MINI 4 * 5 * Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-mini/dart-mx8m-mini/ 6 * 7 * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11/dts-v1/; 12 13#include "imx8mm.dtsi" 14 15/ { 16 model = "Variscite DART-MX8M-MINI Module"; 17 compatible = "variscite,var-dart-mx8mm", "fsl,imx8mm"; 18 19 memory@40000000 { 20 device_type = "memory"; 21 reg = <0x0 0x40000000 0 0x80000000>; 22 }; 23 24 reg_audio_supply: regulator-3p3v { 25 compatible = "regulator-fixed"; 26 regulator-name = "wm8904-supply"; 27 regulator-min-microvolt = <3300000>; 28 regulator-max-microvolt = <3300000>; 29 regulator-always-on; 30 }; 31 32 reg_eth_phy: regulator-eth-phy { 33 compatible = "regulator-fixed"; 34 pinctrl-names = "default"; 35 pinctrl-0 = <&pinctrl_reg_eth_phy>; 36 regulator-name = "eth_phy_pwr"; 37 regulator-min-microvolt = <3300000>; 38 regulator-max-microvolt = <3300000>; 39 regulator-enable-ramp-delay = <20000>; 40 gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; 41 }; 42 43 reg_phy_vddio: regulator-phy-vddio { 44 compatible = "regulator-fixed"; 45 regulator-name = "vddio-1v8"; 46 regulator-min-microvolt = <1800000>; 47 regulator-max-microvolt = <1800000>; 48 }; 49 50 sound-wm8904 { 51 compatible = "simple-audio-card"; 52 simple-audio-card,bitclock-master = <&codec_dai>; 53 simple-audio-card,format = "i2s"; 54 simple-audio-card,frame-master = <&codec_dai>; 55 simple-audio-card,mclk-fs = <256>; 56 simple-audio-card,name = "wm8904-audio"; 57 simple-audio-card,routing = 58 "Headphone Jack", "HPOUTL", 59 "Headphone Jack", "HPOUTR", 60 "IN2L", "Line In Jack", 61 "IN2R", "Line In Jack", 62 "IN1L", "Microphone Jack", 63 "IN1R", "Microphone Jack"; 64 simple-audio-card,widgets = 65 "Microphone", "Microphone Jack", 66 "Headphone", "Headphone Jack", 67 "Line", "Line In Jack"; 68 69 codec_dai: simple-audio-card,codec { 70 sound-dai = <&wm8904>; 71 }; 72 73 simple-audio-card,cpu { 74 sound-dai = <&sai3>; 75 }; 76 }; 77 78 wifi_pwrseq: wifi-pwrseq { 79 compatible = "mmc-pwrseq-simple"; 80 post-power-on-delay-ms = <100>; 81 power-off-delay-us = <10000>; 82 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ 83 <&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ 84 }; 85}; 86 87&A53_0 { 88 cpu-supply = <&buck2_reg>; 89}; 90 91&A53_1 { 92 cpu-supply = <&buck2_reg>; 93}; 94 95&A53_2 { 96 cpu-supply = <&buck2_reg>; 97}; 98 99&A53_3 { 100 cpu-supply = <&buck2_reg>; 101}; 102 103&fec1 { 104 pinctrl-names = "default", "sleep"; 105 pinctrl-0 = <&pinctrl_fec1>; 106 pinctrl-1 = <&pinctrl_fec1_sleep>; 107 /* 108 * The required RGMII TX and RX 2ns delays are implemented directly 109 * in hardware via passive delay elements on the SOM PCB. 110 * No delay configuration is needed in software via PHY driver. 111 */ 112 phy-mode = "rgmii"; 113 phy-handle = <ðphy0>; 114 phy-supply = <®_eth_phy>; 115 status = "okay"; 116 117 mdio { 118 #address-cells = <1>; 119 #size-cells = <0>; 120 121 ethphy0: ethernet-phy@0 { 122 compatible = "ethernet-phy-ieee802.3-c22"; 123 reg = <0>; 124 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 125 reset-assert-us = <10000>; 126 reset-deassert-us = <100000>; 127 vddio-supply = <®_phy_vddio>; 128 }; 129 }; 130}; 131 132&i2c1 { 133 clock-frequency = <100000>; 134 pinctrl-names = "default", "gpio"; 135 pinctrl-0 = <&pinctrl_i2c1>; 136 pinctrl-1 = <&pinctrl_i2c1_gpio>; 137 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 138 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 139 status = "okay"; 140 141 pmic@4b { 142 compatible = "rohm,bd71847"; 143 reg = <0x4b>; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_pmic>; 146 interrupt-parent = <&gpio2>; 147 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 148 rohm,reset-snvs-powered; 149 150 regulators { 151 buck1_reg: BUCK1 { 152 regulator-name = "buck1"; 153 regulator-min-microvolt = <700000>; 154 regulator-max-microvolt = <1300000>; 155 regulator-boot-on; 156 regulator-always-on; 157 regulator-ramp-delay = <1250>; 158 }; 159 160 buck2_reg: BUCK2 { 161 regulator-name = "buck2"; 162 regulator-min-microvolt = <700000>; 163 regulator-max-microvolt = <1300000>; 164 regulator-boot-on; 165 regulator-always-on; 166 regulator-ramp-delay = <1250>; 167 rohm,dvs-run-voltage = <1000000>; 168 rohm,dvs-idle-voltage = <900000>; 169 }; 170 171 buck3_reg: BUCK3 { 172 // BUCK5 in datasheet 173 regulator-name = "buck3"; 174 regulator-min-microvolt = <700000>; 175 regulator-max-microvolt = <1350000>; 176 regulator-boot-on; 177 regulator-always-on; 178 }; 179 180 buck4_reg: BUCK4 { 181 // BUCK6 in datasheet 182 regulator-name = "buck4"; 183 regulator-min-microvolt = <2600000>; 184 regulator-max-microvolt = <3300000>; 185 regulator-boot-on; 186 regulator-always-on; 187 }; 188 189 buck5_reg: BUCK5 { 190 // BUCK7 in datasheet 191 regulator-name = "buck5"; 192 regulator-min-microvolt = <1605000>; 193 regulator-max-microvolt = <1995000>; 194 regulator-boot-on; 195 regulator-always-on; 196 }; 197 198 buck6_reg: BUCK6 { 199 // BUCK8 in datasheet 200 regulator-name = "buck6"; 201 regulator-min-microvolt = <800000>; 202 regulator-max-microvolt = <1400000>; 203 regulator-boot-on; 204 regulator-always-on; 205 }; 206 207 ldo1_reg: LDO1 { 208 regulator-name = "ldo1"; 209 regulator-min-microvolt = <1600000>; 210 regulator-max-microvolt = <1900000>; 211 regulator-boot-on; 212 regulator-always-on; 213 }; 214 215 ldo2_reg: LDO2 { 216 regulator-name = "ldo2"; 217 regulator-min-microvolt = <800000>; 218 regulator-max-microvolt = <900000>; 219 regulator-boot-on; 220 regulator-always-on; 221 }; 222 223 ldo3_reg: LDO3 { 224 regulator-name = "ldo3"; 225 regulator-min-microvolt = <1800000>; 226 regulator-max-microvolt = <3300000>; 227 regulator-boot-on; 228 regulator-always-on; 229 }; 230 231 ldo4_reg: LDO4 { 232 regulator-name = "ldo4"; 233 regulator-min-microvolt = <900000>; 234 regulator-max-microvolt = <1800000>; 235 regulator-always-on; 236 }; 237 238 ldo5_reg: LDO5 { 239 regulator-name = "ldo5"; 240 regulator-min-microvolt = <1800000>; 241 regulator-max-microvolt = <1800000>; 242 regulator-always-on; 243 }; 244 245 ldo6_reg: LDO6 { 246 regulator-name = "ldo6"; 247 regulator-min-microvolt = <900000>; 248 regulator-max-microvolt = <1800000>; 249 regulator-boot-on; 250 regulator-always-on; 251 }; 252 }; 253 }; 254}; 255 256&i2c3 { 257 clock-frequency = <100000>; 258 pinctrl-names = "default", "gpio"; 259 pinctrl-0 = <&pinctrl_i2c3>; 260 pinctrl-1 = <&pinctrl_i2c3_gpio>; 261 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 262 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 263 status = "okay"; 264 265 wm8904: audio-codec@1a { 266 compatible = "wlf,wm8904"; 267 reg = <0x1a>; 268 #sound-dai-cells = <0>; 269 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; 270 clock-names = "mclk"; 271 AVDD-supply = <&ldo5_reg>; 272 CPVDD-supply = <&ldo5_reg>; 273 DBVDD-supply = <®_audio_supply>; 274 DCVDD-supply = <&ldo5_reg>; 275 MICVDD-supply = <&ldo5_reg>; 276 wlf,drc-cfg-names = "default", "peaklimiter", "tradition", 277 "soft", "music"; 278 /* 279 * Config registers per name, respectively: 280 * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 281 * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 282 * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 283 * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 284 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 285 */ 286 wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, 287 /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, 288 /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, 289 /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, 290 /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; 291 /* GPIO1 = DMIC_CLK, don't touch others */ 292 wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; 293 }; 294}; 295 296&mu { 297 status = "okay"; 298}; 299 300&sai3 { 301 #sound-dai-cells = <0>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pinctrl_sai3>; 304 assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 305 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 306 assigned-clock-rates = <1536000>; 307 fsl,sai-mclk-direction-output; 308 status = "okay"; 309}; 310 311/* BT module */ 312&uart4 { 313 pinctrl-names = "default"; 314 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; 315 assigned-clocks = <&clk IMX8MM_CLK_UART4>; 316 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 317 uart-has-rtscts; 318 status = "okay"; 319 320 bluetooth_iw61x: bluetooth { 321 compatible = "nxp,88w8987-bt"; 322 }; 323}; 324 325/* WIFI */ 326&usdhc1 { 327 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 328 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>; 329 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>; 330 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>; 331 bus-width = <4>; 332 keep-power-in-suspend; 333 mmc-pwrseq = <&wifi_pwrseq>; 334 non-removable; 335 status = "okay"; 336}; 337 338/* eMMC */ 339&usdhc3 { 340 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 341 pinctrl-0 = <&pinctrl_usdhc3>; 342 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 343 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 344 bus-width = <8>; 345 non-removable; 346 status = "okay"; 347}; 348 349&wdog1 { 350 pinctrl-names = "default"; 351 pinctrl-0 = <&pinctrl_wdog>; 352 fsl,ext-reset-output; 353 status = "okay"; 354}; 355 356&iomuxc { 357 pinctrl_bt: btgrp { 358 fsl,pins = < 359 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0xc1 360 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc1 361 >; 362 }; 363 364 pinctrl_fec1: fec1grp { 365 fsl,pins = < 366 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 367 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 368 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 369 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 370 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 371 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 372 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 373 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 374 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 375 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 376 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 377 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 378 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 379 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 380 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 381 >; 382 }; 383 384 pinctrl_fec1_sleep: fec1sleepgrp { 385 fsl,pins = < 386 MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x120 387 MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120 388 MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x120 389 MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x120 390 MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x120 391 MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x120 392 MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x120 393 MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x120 394 MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x120 395 MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x120 396 MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x120 397 MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x120 398 MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120 399 MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120 400 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x100 401 >; 402 }; 403 404 pinctrl_i2c1: i2c1grp { 405 fsl,pins = < 406 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 407 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 408 >; 409 }; 410 411 pinctrl_i2c1_gpio: i2c1-gpiogrp { 412 fsl,pins = < 413 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 414 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 415 >; 416 }; 417 418 pinctrl_i2c3: i2c3grp { 419 fsl,pins = < 420 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 421 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 422 >; 423 }; 424 425 pinctrl_i2c3_gpio: i2c3-gpiogrp { 426 fsl,pins = < 427 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 428 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 429 >; 430 }; 431 432 pinctrl_pmic: pmicgrp { 433 fsl,pins = < 434 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x140 435 >; 436 }; 437 438 pinctrl_reg_eth_phy: regeth-phygrp { 439 fsl,pins = < 440 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 441 >; 442 }; 443 444 pinctrl_sai3: sai3grp { 445 fsl,pins = < 446 MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6 447 MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 448 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 449 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 450 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 451 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 452 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 453 >; 454 }; 455 456 pinctrl_uart4: uart4grp { 457 fsl,pins = < 458 MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x140 459 MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x140 460 MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x140 461 MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x140 462 >; 463 }; 464 465 pinctrl_usdhc1: usdhc1grp { 466 fsl,pins = < 467 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 468 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 469 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 470 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 471 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 472 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 473 >; 474 }; 475 476 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 477 fsl,pins = < 478 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 479 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 480 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 481 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 482 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 483 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 484 >; 485 }; 486 487 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 488 fsl,pins = < 489 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 490 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 491 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 492 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 493 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 494 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 495 >; 496 }; 497 498 pinctrl_usdhc3: usdhc3grp { 499 fsl,pins = < 500 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 501 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 502 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 503 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 504 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 505 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 506 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 507 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 508 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 509 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 510 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 511 >; 512 }; 513 514 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 515 fsl,pins = < 516 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 517 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 518 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 519 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 520 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 521 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 522 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 523 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 524 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 525 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 526 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 527 >; 528 }; 529 530 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 531 fsl,pins = < 532 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 533 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 534 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 535 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 536 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 537 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 538 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 539 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 540 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 541 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 542 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 543 >; 544 }; 545 546 pinctrl_wdog: wdoggrp { 547 fsl,pins = < 548 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 549 >; 550 }; 551 552 pinctrl_wifi: wifigrp { 553 fsl,pins = < 554 MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x140 555 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0xc1 556 >; 557 }; 558}; 559