1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Variscite Sonata carrier board for DART-MX8M-MINI 4 * 5 * Link: https://variscite.com/carrier-boards/sonata-board/ 6 * 7 * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11/dts-v1/; 12 13#include <dt-bindings/leds/common.h> 14#include <dt-bindings/phy/phy-imx8-pcie.h> 15#include "imx8mm-var-dart.dtsi" 16 17/ { 18 model = "Variscite DART-MX8M-MINI on Sonata-Board"; 19 compatible = "variscite,var-dart-mx8mm-sonata", 20 "variscite,var-dart-mx8mm", 21 "fsl,imx8mm"; 22 23 chosen { 24 stdout-path = &uart1; 25 }; 26 27 gpio-keys { 28 compatible = "gpio-keys"; 29 30 button-home { 31 label = "Home"; 32 linux,code = <KEY_HOME>; 33 gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; 34 wakeup-source; 35 }; 36 37 button-up { 38 label = "Up"; 39 linux,code = <KEY_UP>; 40 gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; 41 wakeup-source; 42 }; 43 44 button-down { 45 label = "Down"; 46 linux,code = <KEY_DOWN>; 47 gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; 48 wakeup-source; 49 }; 50 51 button-back { 52 label = "Back"; 53 linux,code = <KEY_BACK>; 54 gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; 55 wakeup-source; 56 }; 57 }; 58 59 gpio-leds { 60 compatible = "gpio-leds"; 61 pinctrl-names = "default"; 62 pinctrl-0 = <&pinctrl_gpio_leds>; 63 64 led-emmc { 65 gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; 66 label = "eMMC"; 67 linux,default-trigger = "mmc2"; 68 }; 69 }; 70 71 clk40m: oscillator { 72 compatible = "fixed-clock"; 73 #clock-cells = <0>; 74 clock-frequency = <40000000>; 75 clock-output-names = "can_osc"; 76 }; 77 78 pcie0_refclk: pcie0-refclk { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <100000000>; 82 }; 83 84 reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { 85 compatible = "regulator-fixed"; 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_vmmc_usdhc2>; 88 regulator-name = "VSD_3V3"; 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 92 enable-active-high; 93 startup-delay-us = <100>; 94 off-on-delay-us = <12000>; 95 }; 96}; 97 98&ecspi1 { 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_ecspi1>; 101 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, 102 <&gpio1 12 GPIO_ACTIVE_LOW>; 103 status = "okay"; 104 105 /* Resistive touch controller */ 106 ads7846: touchscreen@0 { 107 compatible = "ti,ads7846"; 108 reg = <0>; 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_restouch>; 111 interrupt-parent = <&gpio1>; 112 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 113 spi-max-frequency = <1500000>; 114 pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; 115 ti,x-min = /bits/ 16 <125>; 116 ti,x-max = /bits/ 16 <4008>; 117 ti,y-min = /bits/ 16 <282>; 118 ti,y-max = /bits/ 16 <3864>; 119 ti,x-plate-ohms = /bits/ 16 <180>; 120 ti,pressure-max = /bits/ 16 <255>; 121 ti,debounce-max = /bits/ 16 <10>; 122 ti,debounce-tol = /bits/ 16 <3>; 123 ti,debounce-rep = /bits/ 16 <1>; 124 ti,settle-delay-usec = /bits/ 16 <150>; 125 ti,keep-vref-on; 126 wakeup-source; 127 }; 128 129 can0: can@1 { 130 compatible = "microchip,mcp251xfd"; 131 reg = <1>; 132 pinctrl-names = "default"; 133 pinctrl-0 = <&pinctrl_can>; 134 clocks = <&clk40m>; 135 interrupt-parent = <&gpio1>; 136 interrupts = <6 IRQ_TYPE_LEVEL_LOW>; 137 microchip,rx-int-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; 138 spi-max-frequency = <20000000>; 139 }; 140}; 141 142ðphy0 { 143 leds { 144 #address-cells = <1>; 145 #size-cells = <0>; 146 147 led@0 { 148 reg = <0>; 149 color = <LED_COLOR_ID_YELLOW>; 150 function = LED_FUNCTION_LAN; 151 linux,default-trigger = "netdev"; 152 }; 153 154 led@1 { 155 reg = <1>; 156 color = <LED_COLOR_ID_GREEN>; 157 function = LED_FUNCTION_LAN; 158 linux,default-trigger = "netdev"; 159 }; 160 }; 161}; 162 163&i2c2 { 164 clock-frequency = <100000>; 165 pinctrl-names = "default", "gpio"; 166 pinctrl-0 = <&pinctrl_i2c2>; 167 pinctrl-1 = <&pinctrl_i2c2_gpio>; 168 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 169 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 170 status = "okay"; 171 172 pca9534: gpio@22 { 173 compatible = "nxp,pca9534"; 174 reg = <0x22>; 175 gpio-controller; 176 #gpio-cells = <2>; 177 178 /* RGB_SEL */ 179 lvds-brg-enable-hog { 180 gpio-hog; 181 gpios = <7 GPIO_ACTIVE_HIGH>; 182 output-low; 183 line-name = "rgb_sel"; 184 }; 185 }; 186 187 /* Capacitive touch controller */ 188 ft5x06_ts: touchscreen@38 { 189 compatible = "edt,edt-ft5206"; 190 reg = <0x38>; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_captouch>; 193 reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; 194 interrupt-parent = <&gpio1>; 195 interrupts = <14 IRQ_TYPE_EDGE_FALLING>; 196 touchscreen-size-x = <800>; 197 touchscreen-size-y = <480>; 198 touchscreen-inverted-x; 199 touchscreen-inverted-y; 200 wakeup-source; 201 }; 202 203 extcon_ptn5150: typec@3d { 204 compatible = "nxp,ptn5150"; 205 reg = <0x3d>; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_extcon>; 208 interrupt-parent = <&gpio1>; 209 interrupts = <10 IRQ_TYPE_EDGE_FALLING>; 210 211 port { 212 typec1_dr_sw: endpoint { 213 remote-endpoint = <&usb1_drd_sw>; 214 }; 215 }; 216 }; 217 218 rtc@68 { 219 compatible = "dallas,ds1337"; 220 reg = <0x68>; 221 pinctrl-names = "default"; 222 pinctrl-0 = <&pinctrl_rtc>; 223 interrupt-parent = <&gpio1>; 224 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 225 wakeup-source; 226 }; 227}; 228 229&i2c4 { 230 clock-frequency = <100000>; 231 pinctrl-names = "default", "gpio"; 232 pinctrl-0 = <&pinctrl_i2c4>; 233 pinctrl-1 = <&pinctrl_i2c4_gpio>; 234 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 235 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 236 status = "okay"; 237 238 pca6408_1: gpio@20 { 239 compatible = "nxp,pcal6408"; 240 reg = <0x20>; 241 gpio-controller; 242 #gpio-cells = <2>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_pca6408>; 245 interrupt-parent = <&gpio1>; 246 interrupts = <5 IRQ_TYPE_LEVEL_LOW>; 247 }; 248 249 pca6408_2: gpio@21 { 250 compatible = "nxp,pcal6408"; 251 reg = <0x21>; 252 gpio-controller; 253 #gpio-cells = <2>; 254 interrupt-parent = <&gpio1>; 255 interrupts = <5 IRQ_TYPE_LEVEL_LOW>; 256 }; 257 258 st33ktpm2xi2c: tpm@2e { 259 compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; 260 reg = <0x2e>; 261 label = "tpm"; 262 reset-gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; 263 }; 264}; 265 266&pcie_phy { 267 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 268 fsl,tx-deemph-gen1 = <0x2d>; 269 fsl,tx-deemph-gen2 = <0xf>; 270 clocks = <&pcie0_refclk>; 271 status = "okay"; 272}; 273 274&pcie0 { 275 reset-gpios = <&pca6408_2 3 GPIO_ACTIVE_LOW>; 276 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, 277 <&clk IMX8MM_CLK_PCIE1_AUX>; 278 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 279 <&clk IMX8MM_CLK_PCIE1_CTRL>; 280 assigned-clock-rates = <10000000>, <250000000>; 281 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 282 <&clk IMX8MM_SYS_PLL2_250M>; 283 status = "okay"; 284}; 285 286&pwm1 { 287 pinctrl-names = "default"; 288 pinctrl-0 = <&pinctrl_pwm>; 289 status = "okay"; 290}; 291 292&snvs_pwrkey { 293 status = "okay"; 294}; 295 296&snvs_rtc { 297 status = "disabled"; 298}; 299 300/* Console */ 301&uart1 { 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pinctrl_uart1>; 304 wakeup-source; 305 status = "okay"; 306}; 307 308/* Header */ 309&uart2 { 310 pinctrl-names = "default"; 311 pinctrl-0 = <&pinctrl_uart2>; 312 status = "okay"; 313}; 314 315/* Header */ 316&uart3 { 317 pinctrl-names = "default"; 318 pinctrl-0 = <&pinctrl_uart3>; 319 status = "okay"; 320}; 321 322&usbotg1 { 323 dr_mode = "otg"; 324 hnp-disable; 325 srp-disable; 326 adp-disable; 327 usb-role-switch; 328 disable-over-current; 329 samsung,picophy-pre-emp-curr-control = <3>; 330 samsung,picophy-dc-vol-level-adjust = <7>; 331 status = "okay"; 332 333 port { 334 usb1_drd_sw: endpoint { 335 remote-endpoint = <&typec1_dr_sw>; 336 }; 337 }; 338}; 339 340&usbotg2 { 341 dr_mode = "host"; 342 samsung,picophy-pre-emp-curr-control = <3>; 343 samsung,picophy-dc-vol-level-adjust = <7>; 344 disable-over-current; 345 status = "okay"; 346}; 347 348/* SD */ 349&usdhc2 { 350 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 351 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 352 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 353 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 354 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 355 bus-width = <4>; 356 vmmc-supply = <®_usdhc2_vmmc>; 357 status = "okay"; 358}; 359 360&iomuxc { 361 pinctrl_can: cangrp { 362 fsl,pins = < 363 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16 364 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16 365 >; 366 }; 367 368 pinctrl_captouch: captouchgrp { 369 fsl,pins = < 370 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 371 >; 372 }; 373 374 pinctrl_ecspi1: ecspi1grp { 375 fsl,pins = < 376 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 377 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 378 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 379 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x13 380 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x13 381 >; 382 }; 383 384 pinctrl_extcon: extcongrp { 385 fsl,pins = < 386 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 387 >; 388 }; 389 390 pinctrl_gpio_leds: ledgrp { 391 fsl,pins = < 392 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c6 393 >; 394 }; 395 396 pinctrl_i2c2: i2c2grp { 397 fsl,pins = < 398 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 399 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 400 >; 401 }; 402 403 pinctrl_i2c2_gpio: i2c2-gpiogrp { 404 fsl,pins = < 405 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 406 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 407 >; 408 }; 409 410 pinctrl_i2c4: i2c4grp { 411 fsl,pins = < 412 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 413 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 414 >; 415 }; 416 417 pinctrl_i2c4_gpio: i2c4-gpiogrp { 418 fsl,pins = < 419 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 420 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 421 >; 422 }; 423 424 pinctrl_pca6408: pca6408grp { 425 fsl,pins = < 426 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c6 427 >; 428 }; 429 430 pinctrl_pwm: pwmgrp { 431 fsl,pins = < 432 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 433 >; 434 }; 435 436 pinctrl_vmmc_usdhc2: regvmmc-usdhc2grp { 437 fsl,pins = < 438 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0xc1 439 >; 440 }; 441 442 pinctrl_restouch: restouchgrp { 443 fsl,pins = < 444 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 445 >; 446 }; 447 448 pinctrl_rtc: rtcgrp { 449 fsl,pins = < 450 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c1 451 >; 452 }; 453 454 pinctrl_uart1: uart1grp { 455 fsl,pins = < 456 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 457 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 458 >; 459 }; 460 461 pinctrl_uart2: uart2grp { 462 fsl,pins = < 463 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 464 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 465 >; 466 }; 467 468 pinctrl_uart3: uart3grp { 469 fsl,pins = < 470 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 471 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 472 >; 473 }; 474 475 pinctrl_usdhc2: usdhc2grp { 476 fsl,pins = < 477 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 478 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 479 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 480 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 481 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 482 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 483 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 484 >; 485 }; 486 487 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 488 fsl,pins = < 489 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 490 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 491 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 492 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 493 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 494 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 495 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 496 >; 497 }; 498 499 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 500 fsl,pins = < 501 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 502 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 503 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 504 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 505 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 506 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 507 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 508 >; 509 }; 510 511 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 512 fsl,pins = < 513 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0xc1 514 >; 515 }; 516}; 517