1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 Lothar Waßmann <LW@KARO-electronics.de> 4 * 2025 Maud Spierings <maudspierings@gocontroll.com> 5 */ 6 7#include "imx8mm.dtsi" 8 9/ { 10 model = "Ka-Ro Electronics TX8M-1610"; 11 compatible = "karo,tx8m-1610", "fsl,imx8mm"; 12 13 reg_3v3_etn: regulator-3v3-etn { 14 compatible = "regulator-fixed"; 15 enable-active-high; 16 gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; 17 pinctrl-0 = <&pinctrl_reg_3v3_etn>; 18 pinctrl-names = "default"; 19 regulator-boot-on; 20 regulator-max-microvolt = <3300000>; 21 regulator-min-microvolt = <3300000>; 22 regulator-name = "3v3-etn"; 23 }; 24}; 25 26&A53_0 { 27 cpu-supply = <®_vdd_arm>; 28}; 29 30&A53_1 { 31 cpu-supply = <®_vdd_arm>; 32}; 33 34&A53_2 { 35 cpu-supply = <®_vdd_arm>; 36}; 37 38&A53_3 { 39 cpu-supply = <®_vdd_arm>; 40}; 41 42&ddrc { 43 operating-points-v2 = <&ddrc_opp_table>; 44 45 ddrc_opp_table: opp-table { 46 compatible = "operating-points-v2"; 47 48 opp-400000000 { 49 opp-hz = /bits/ 64 <400000000>; 50 }; 51 }; 52}; 53 54&fec1 { 55 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, 56 <&clk IMX8MM_CLK_ENET_TIMER>, 57 <&clk IMX8MM_CLK_ENET_REF>, 58 <&clk IMX8MM_CLK_ENET_REF>; 59 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 60 <&clk IMX8MM_SYS_PLL2_100M>, 61 <&clk IMX8MM_SYS_PLL2_50M>, 62 <&clk IMX8MM_SYS_PLL2_50M>; 63 assigned-clock-rates = <0>, <100000000>, <50000000>, <50000000>; 64 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, 65 <&clk IMX8MM_CLK_ENET1_ROOT>, 66 <&clk IMX8MM_CLK_ENET_TIMER>, 67 <&clk IMX8MM_CLK_ENET_REF>; 68 phy-handle = <ðphy0>; 69 phy-mode = "rmii"; 70 phy-reset-duration = <25>; 71 phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; 72 phy-reset-post-delay = <1>; 73 phy-supply = <®_3v3_etn>; 74 pinctrl-0 = <&pinctrl_fec1>, <&pinctrl_ethphy_rst>; 75 pinctrl-names = "default"; 76 status = "okay"; 77 78 mdio { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 82 ethphy0: ethernet-phy@0 { 83 reg = <0>; 84 clocks = <&clk IMX8MM_CLK_ENET_REF>; 85 interrupt-parent = <&gpio1>; 86 interrupts = <28 IRQ_TYPE_EDGE_FALLING>; 87 pinctrl-0 = <&pinctrl_ethphy_int>; 88 pinctrl-names = "default"; 89 smsc,disable-energy-detect; 90 }; 91 }; 92}; 93 94&gpio1 { 95 gpio-line-names = "SODIMM_152", "SODIMM_42", "SODIMM_153", "PMIC_IRQ_B", 96 "SODIMM_154", "SODIMM_155", "SODIMM_156", "SODIMM_157", 97 "SODIMM_158", "SODIMM_159", "SODIMM_161", "SODIMM_162", 98 "SODIMM_34", "SODIMM_36", "SODIMM_27", "SODIMM_28", 99 "", "", "", "", 100 "", "", "", "ENET_POWER", 101 "", "", "", "", 102 "ENET_nINT", "ENET_nRST", "", ""; 103}; 104 105&gpio2 { 106 gpio-line-names = "", "", "", "", 107 "", "", "", "", 108 "", "", "", "", 109 "SODIMM_51", "SODIMM_57", "SODIMM_56", "SODIMM_52", 110 "SODIMM_53", "SODIMM_54", "SODIMM_55", "SODIMM_15", 111 "SODIMM_45", "", "", "", 112 "", "", "", "", 113 "", "", "", ""; 114}; 115 116&gpio3 { 117 gpio-line-names = "SODIMM_103", "SODIMM_104", "SODIMM_105", "SODIMM_106", 118 "SODIMM_107", "SODIMM_112", "SODIMM_108", "SODIMM_109", 119 "SODIMM_95", "SODIMM_110", "SODIMM_96", "SODIMM_97", 120 "SODIMM_98", "SODIMM_99", "SODIMM_113", "SODIMM_114", 121 "SODIMM_115", "SODIMM_101", "SODIMM_100", "SODIMM_77", 122 "SODIMM_72", "SODIMM_73", "SODIMM_74", "SODIMM_75", 123 "SODIMM_76", "SODIMM_43", "", "", 124 "", "", "", ""; 125}; 126 127&gpio4 { 128 gpio-line-names = "SODIMM_178", "SODIMM_180", "SODIMM_184", "SODIMM_185", 129 "SODIMM_186", "SODIMM_187", "SODIMM_188", "SODIMM_189", 130 "SODIMM_190", "SODIMM_191", "SODIMM_179", "SODIMM_181", 131 "SODIMM_192", "SODIMM_193", "SODIMM_194", "SODIMM_195", 132 "SODIMM_196", "SODIMM_197", "SODIMM_198", "SODIMM_199", 133 "SODIMM_182", "SODIMM_79", "SODIMM_78", "SODIMM_84", 134 "SODIMM_87", "SODIMM_86", "SODIMM_85", "SODIMM_83", 135 "SODIMM_81", "SODIMM_80", "SODIMM_90", "SODIMM_93"; 136}; 137 138&gpio5 { 139 gpio-line-names = "SODIMM_92", "SODIMM_91", "SODIMM_89", "SODIMM_144", 140 "SODIMM_143", "SODIMM_146", "SODIMM_68", "SODIMM_67", 141 "SODIMM_70", "SODIMM_69", "SODIMM_48", "SODIMM_46", 142 "SODIMM_47", "SODIMM_44", "PMIC_SCL", "PMIC_SDA", 143 "SODIMM_41", "SODIMM_40", "SODIMM_148", "SODIMM_149", 144 "SODIMM_150", "SODIMM_151", "SODIMM_60", "SODIMM_59", 145 "SODIMM_64", "SODIMM_63", "SODIMM_62", "SODIMM_61", 146 "SODIMM_66", "SODIMM_65", "", ""; 147}; 148 149&i2c1 { 150 clock-frequency = <400000>; 151 pinctrl-0 = <&pinctrl_i2c1>; 152 pinctrl-1 = <&pinctrl_i2c1_gpio>; 153 pinctrl-names = "default", "gpio"; 154 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 155 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 156 status = "okay"; 157 158 pmic: pmic@4b { 159 compatible = "rohm,bd71847"; 160 reg = <0x4b>; 161 interrupt-parent = <&gpio1>; 162 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 163 pinctrl-0 = <&pinctrl_pmic>; 164 pinctrl-names = "default"; 165 rohm,reset-snvs-powered; 166 167 regulators { 168 BUCK1 { 169 regulator-always-on; 170 regulator-boot-on; 171 regulator-max-microvolt = <900000>; 172 regulator-min-microvolt = <780000>; 173 regulator-name = "buck1"; 174 regulator-ramp-delay = <1250>; 175 }; 176 177 reg_vdd_arm: BUCK2 { 178 regulator-always-on; 179 regulator-boot-on; 180 regulator-max-microvolt = <950000>; 181 regulator-min-microvolt = <805000>; 182 regulator-name = "buck2"; 183 regulator-ramp-delay = <1250>; 184 rohm,dvs-run-voltage = <950000>; 185 rohm,dvs-idle-voltage = <810000>; 186 }; 187 188 BUCK3 { 189 regulator-always-on; 190 regulator-boot-on; 191 regulator-max-microvolt = <900000>; 192 regulator-min-microvolt = <805000>; 193 regulator-name = "buck3"; 194 }; 195 196 reg_vdd_3v3: BUCK4 { 197 regulator-always-on; 198 regulator-boot-on; 199 regulator-max-microvolt = <3300000>; 200 regulator-min-microvolt = <3300000>; 201 regulator-name = "buck4"; 202 }; 203 204 reg_vdd_1v8: BUCK5 { 205 regulator-always-on; 206 regulator-boot-on; 207 regulator-max-microvolt = <1950000>; 208 regulator-min-microvolt = <1700000>; 209 regulator-name = "buck5"; 210 }; 211 212 BUCK6 { 213 regulator-always-on; 214 regulator-boot-on; 215 regulator-max-microvolt = <(1350000 + 100000)>; 216 regulator-min-microvolt = <(1350000 - 67000)>; 217 regulator-name = "buck6"; 218 rohm,fb-pull-up-microvolt = <0>; 219 rohm,feedback-pull-up-r1-ohms = <2200>; 220 rohm,feedback-pull-up-r2-ohms = <499>; 221 }; 222 223 LDO1 { 224 regulator-always-on; 225 regulator-boot-on; 226 regulator-max-microvolt = <1980000>; 227 regulator-min-microvolt = <1620000>; 228 regulator-name = "ldo1"; 229 }; 230 231 LDO2 { 232 regulator-always-on; 233 regulator-boot-on; 234 regulator-max-microvolt = <900000>; 235 regulator-min-microvolt = <760000>; 236 regulator-name = "ldo2"; 237 }; 238 239 LDO3 { 240 regulator-always-on; 241 regulator-boot-on; 242 regulator-max-microvolt = <1890000>; 243 regulator-min-microvolt = <1710000>; 244 regulator-name = "ldo3"; 245 }; 246 247 LDO4 { 248 regulator-always-on; 249 regulator-boot-on; 250 regulator-max-microvolt = <1000000>; 251 regulator-min-microvolt = <855000>; 252 regulator-name = "ldo4"; 253 }; 254 255 LDO5 { 256 regulator-max-microvolt = <3300000>; 257 regulator-min-microvolt = <1800000>; 258 regulator-name = "ldo5"; 259 }; 260 261 LDO6 { 262 regulator-always-on; 263 regulator-boot-on; 264 regulator-max-microvolt = <1260000>; 265 regulator-min-microvolt = <1140000>; 266 regulator-name = "ldo6"; 267 }; 268 }; 269 }; 270}; 271 272&iomuxc { 273 pinctrl_ethphy_int: etnphy-intgrp { 274 fsl,pins = < 275 MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 276 (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) 277 >; 278 }; 279 280 pinctrl_ethphy_rst: etnphy-rstgrp { 281 fsl,pins = < 282 MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 283 (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) 284 >; 285 }; 286 287 pinctrl_fec1: fec1grp { 288 fsl,pins = < 289 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 290 (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) 291 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 292 (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) 293 MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 294 (MX8MM_FSEL_FAST | MX8MM_SION) 295 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 296 (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) 297 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 298 (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) 299 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 300 (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) 301 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 302 (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) 303 MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 304 MX8MM_FSEL_FAST 305 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 306 MX8MM_FSEL_FAST 307 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 308 (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) 309 >; 310 }; 311 312 pinctrl_i2c1: i2c1grp { 313 fsl,pins = < 314 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 315 MX8MM_I2C_DEFAULT 316 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 317 MX8MM_I2C_DEFAULT 318 >; 319 }; 320 321 pinctrl_i2c1_gpio: i2c1-gpiogrp { 322 fsl,pins = < 323 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 324 MX8MM_I2C_DEFAULT 325 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 326 MX8MM_I2C_DEFAULT 327 >; 328 }; 329 330 pinctrl_pmic: pmicgrp { 331 fsl,pins = < 332 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 333 (MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) 334 >; 335 }; 336 337 pinctrl_reg_3v3_etn: reg-3v3-etngrp { 338 fsl,pins = < 339 MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 340 (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) 341 >; 342 }; 343 344 pinctrl_usdhc1: usdhc1grp { 345 fsl,pins = < 346 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 347 (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) 348 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 349 MX8MM_USDHC_DATA_DEFAULT 350 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 351 MX8MM_USDHC_DATA_DEFAULT 352 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 353 MX8MM_USDHC_DATA_DEFAULT 354 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 355 MX8MM_USDHC_DATA_DEFAULT 356 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 357 MX8MM_USDHC_DATA_DEFAULT 358 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 359 MX8MM_USDHC_DATA_DEFAULT 360 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 361 MX8MM_USDHC_DATA_DEFAULT 362 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 363 MX8MM_USDHC_DATA_DEFAULT 364 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 365 MX8MM_USDHC_DATA_DEFAULT 366 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 367 (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) 368 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 369 (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) 370 >; 371 }; 372 373 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 374 fsl,pins = < 375 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 376 (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) 377 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 378 (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) 379 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 380 (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) 381 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 382 (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) 383 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 384 (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) 385 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 386 (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) 387 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 388 (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) 389 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 390 (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) 391 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 392 (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) 393 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 394 (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) 395 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 396 (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) 397 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 398 (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) 399 >; 400 }; 401 402 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 403 fsl,pins = < 404 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 405 (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) 406 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 407 (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) 408 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 409 (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) 410 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 411 (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) 412 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 413 (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) 414 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 415 (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) 416 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 417 (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) 418 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 419 (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) 420 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 421 (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) 422 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 423 (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) 424 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 425 (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) 426 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 427 (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) 428 >; 429 }; 430}; 431 432&usdhc1 { 433 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; 434 assigned-clock-rates = <400000000>; 435 bus-width = <8>; 436 non-removable; 437 pinctrl-0 = <&pinctrl_usdhc1>; 438 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 439 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 440 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 441 vmmc-supply = <®_vdd_3v3>; 442 vqmmc-supply = <®_vdd_1v8>; 443 status = "okay"; 444}; 445