1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (C) 2025 PHYTEC Messtechnik GmbH 4 */ 5 6#include <dt-bindings/clock/imx8mm-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include "imx8mm-pinfunc.h" 9 10&{/} { 11 backlight: backlight { 12 compatible = "pwm-backlight"; 13 pinctrl-names = "default"; 14 pinctrl-0 = <&pinctrl_lcd>; 15 power-supply = <®_vdd_3v3_s>; 16 status = "disabled"; 17 }; 18 19 panel: panel { 20 backlight = <&backlight>; 21 power-supply = <®_vcc_3v3>; 22 status = "disabled"; 23 24 port { 25 panel_in: endpoint { 26 remote-endpoint = <&bridge_out>; 27 }; 28 }; 29 }; 30 31 reg_sound_1v8: regulator-1v8 { 32 compatible = "regulator-fixed"; 33 regulator-name = "VCC_1V8_Audio"; 34 regulator-min-microvolt = <1800000>; 35 regulator-max-microvolt = <1800000>; 36 }; 37 38 reg_sound_3v3: regulator-3v3 { 39 compatible = "regulator-fixed"; 40 regulator-name = "VCC_3V3_Analog"; 41 regulator-min-microvolt = <3300000>; 42 regulator-max-microvolt = <3300000>; 43 }; 44 45 sound-peb-av-10 { 46 compatible = "simple-audio-card"; 47 simple-audio-card,name = "snd-peb-av-10"; 48 simple-audio-card,format = "i2s"; 49 simple-audio-card,bitclock-master = <&dailink_master>; 50 simple-audio-card,frame-master = <&dailink_master>; 51 simple-audio-card,mclk-fs = <32>; 52 simple-audio-card,widgets = 53 "Line", "Line In", 54 "Speaker", "Speaker", 55 "Microphone", "Microphone Jack", 56 "Headphone", "Headphone Jack"; 57 simple-audio-card,routing = 58 "Speaker", "SPOP", 59 "Speaker", "SPOM", 60 "Headphone Jack", "HPLOUT", 61 "Headphone Jack", "HPROUT", 62 "LINE1L", "Line In", 63 "LINE1R", "Line In", 64 "MIC3R", "Microphone Jack", 65 "Microphone Jack", "Mic Bias"; 66 67 simple-audio-card,cpu { 68 sound-dai = <&sai5>; 69 }; 70 71 dailink_master: simple-audio-card,codec { 72 sound-dai = <&codec>; 73 clocks = <&clk IMX8MM_CLK_SAI5>; 74 }; 75 }; 76}; 77 78&bridge_out { 79 remote-endpoint = <&panel_in>; 80}; 81 82&i2c3 { 83 clock-frequency = <400000>; 84 pinctrl-names = "default", "gpio"; 85 pinctrl-0 = <&pinctrl_i2c3>; 86 pinctrl-1 = <&pinctrl_i2c3_gpio>; 87 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 88 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 89 #address-cells = <1>; 90 #size-cells = <0>; 91 status = "okay"; 92 93 codec: codec@18 { 94 compatible = "ti,tlv320aic3007"; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_tlv320>; 97 #sound-dai-cells = <0>; 98 reg = <0x18>; 99 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 100 ai3x-gpio-func = <0xd 0x0>; 101 ai3x-micbias-vg = <2>; 102 AVDD-supply = <®_sound_3v3>; 103 IOVDD-supply = <®_sound_3v3>; 104 DRVDD-supply = <®_sound_3v3>; 105 DVDD-supply = <®_sound_1v8>; 106 }; 107 108 eeprom@57 { 109 compatible = "atmel,24c32"; 110 pagesize = <32>; 111 reg = <0x57>; 112 vcc-supply = <®_vdd_3v3_s>; 113 }; 114 115 eeprom@5f { 116 compatible = "atmel,24c32"; 117 pagesize = <32>; 118 reg = <0x5f>; 119 size = <32>; 120 vcc-supply = <®_vdd_3v3_s>; 121 }; 122}; 123 124&pwm4 { 125 pinctrl-names = "default"; 126 pinctrl-0 = <&pinctrl_pwm4>; 127}; 128 129&sai5 { 130 assigned-clocks = <&clk IMX8MM_CLK_SAI5>; 131 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; 132 assigned-clock-rates = <11289600>; 133 clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, 134 <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, 135 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, 136 <&clk IMX8MM_AUDIO_PLL2_OUT>; 137 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", 138 "pll11k"; 139 fsl,sai-mclk-direction-output; 140 pinctrl-names = "default"; 141 pinctrl-0 = <&pinctrl_sai5>; 142 #sound-dai-cells = <0>; 143 status = "okay"; 144}; 145 146&iomuxc { 147 148 pinctrl_i2c3: i2c3grp { 149 fsl,pins = < 150 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 151 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 152 >; 153 }; 154 155 pinctrl_i2c3_gpio: i2c3gpiogrp { 156 fsl,pins = < 157 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e2 158 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e2 159 >; 160 }; 161 pinctrl_lcd: lcd0grp { 162 fsl,pins = < 163 MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x12 164 >; 165 }; 166 167 pinctrl_pwm4: pwm4grp { 168 fsl,pins = < 169 MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x12 170 >; 171 }; 172 173 pinctrl_sai5: sai5grp { 174 fsl,pins = < 175 MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 176 MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 177 MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 178 MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 179 MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 180 >; 181 }; 182 183 pinctrl_tlv320: tlv320grp { 184 fsl,pins = < 185 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x116 186 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16 187 >; 188 }; 189}; 190