xref: /linux/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright 2021-2022 Marek Vasut <marex@denx.de>
4 */
5
6/dts-v1/;
7
8#include "imx8mm-verdin.dtsi"
9
10/ {
11	model = "MENLO MX8MM EMBEDDED DEVICE";
12	compatible = "menlo,mx8menlo",
13		     "toradex,verdin-imx8mm-nonwifi",
14		     "toradex,verdin-imx8mm",
15		     "fsl,imx8mm";
16
17	/delete-node/ gpio-keys;
18
19	leds {
20		compatible = "gpio-leds";
21		pinctrl-names = "default";
22		pinctrl-0 = <&pinctrl_led>;
23
24		led-1 {
25			label = "TestLed601";
26			gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
27			linux,default-trigger = "mmc0";
28		};
29
30		led-2 {
31			label = "TestLed602";
32			gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
33			linux,default-trigger = "heartbeat";
34		};
35	};
36
37	beeper {
38		compatible = "gpio-beeper";
39		pinctrl-names = "default";
40		pinctrl-0 = <&pinctrl_beeper>;
41		gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
42	};
43
44	/* Fixed clock dedicated to SPI CAN on carrier board */
45	clk_xtal20: clk-xtal20 {
46		compatible = "fixed-clock";
47		#clock-cells = <0>;
48		clock-frequency = <20000000>;
49	};
50};
51
52&ecspi1 {
53	#address-cells = <1>;
54	#size-cells = <0>;
55	pinctrl-names = "default";
56	pinctrl-0 = <&pinctrl_ecspi1>;
57	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
58	status = "okay";
59
60	/* CAN controller on the baseboard */
61	canfd: can@0 {
62		compatible = "microchip,mcp2518fd";
63		clocks = <&clk_xtal20>;
64		interrupt-parent = <&gpio1>;
65		interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
66		reg = <0>;
67		spi-max-frequency = <2000000>;
68	};
69
70};
71
72&ecspi2 {
73	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
74	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>;
75	status = "okay";
76
77	spidev@0 {
78		compatible = "menlo,m53cpld";
79		reg = <0>;
80		spi-max-frequency = <25000000>;
81	};
82
83	spidev@1 {
84		compatible = "menlo,m53cpld";
85		reg = <1>;
86		spi-max-frequency = <25000000>;
87	};
88
89};
90
91&ethphy0 {
92	max-speed = <100>;
93};
94
95&fec1 {
96	status = "okay";
97};
98
99&flexspi {
100	status = "okay";
101
102	flash@0 {
103		reg = <0>;
104		#address-cells = <1>;
105		#size-cells = <1>;
106		compatible = "jedec,spi-nor";
107		spi-max-frequency = <66000000>;
108		spi-rx-bus-width = <4>;
109		spi-tx-bus-width = <4>;
110	};
111};
112
113&gpio1 {
114	gpio-line-names =
115		"", "", "", "",
116		"", "", "", "",
117		"", "", "", "",
118		"", "", "", "",
119		"", "", "", "",
120		"", "", "", "",
121		"", "", "", "",
122		"", "", "", "";
123};
124
125&gpio2 {
126	gpio-line-names =
127		"", "", "", "",
128		"", "", "", "",
129		"", "", "", "",
130		"", "", "", "",
131		"", "", "", "",
132		"", "", "", "",
133		"", "", "", "",
134		"", "", "", "";
135};
136
137&gpio3 {
138	gpio-line-names =
139		"", "", "", "",
140		"", "", "", "",
141		"", "", "", "",
142		"", "", "", "",
143		"", "", "", "",
144		"", "", "DISP_reset", "KBD_intI",
145		"", "", "", "",
146		"", "", "", "";
147};
148
149&gpio4 {
150	/*
151	 * CPLD_D[n] is ARM_CPLD[n] in schematic
152	 * CPLD_int is SA_INTERRUPT in schematic
153	 * CPLD_reset is RESET_SOFT in schematic
154	 */
155	gpio-line-names =
156		"CPLD_D[6]", "CPLD_int", "CPLD_reset", "",
157		"", "CPLD_D[7]", "", "",
158		"", "", "", "CPLD_D[5]",
159		"CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]",
160		"CPLD_D[0]", "", "", "",
161		"", "", "", "",
162		"", "", "", "KBD_intK",
163		"", "", "", "";
164};
165
166&gpio5 {
167	gpio-line-names =
168		"", "", "", "",
169		"", "", "", "",
170		"", "", "", "",
171		"", "", "", "",
172		"", "", "", "",
173		"", "", "", "",
174		"", "", "", "",
175		"", "", "", "";
176};
177
178&gpio_expander_21 {
179	status = "okay";
180};
181
182&hwmon {
183	status = "okay";
184};
185
186&i2c3 {
187	status = "okay";
188};
189
190&i2c4 {
191	/* None of this is present on the SoM. */
192	/delete-node/ bridge@2c;
193	/delete-node/ hdmi@48;
194	/delete-node/ touch@4a;
195	/delete-node/ sensor@4f;
196	/delete-node/ eeprom@50;
197	/delete-node/ eeprom@57;
198};
199
200&iomuxc {
201	pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>,
202		    <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
203
204	pinctrl_beeper: beepergrp {
205		fsl,pins = <
206			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3			0x1c4
207		>;
208	};
209
210	pinctrl_ecspi1: ecspi1grp {
211		fsl,pins = <
212			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x4
213			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x4
214			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x1c4
215			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x1c4
216		>;
217	};
218
219	pinctrl_led: ledgrp {
220		fsl,pins = <
221			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x1c4
222			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10		0x1c4
223		>;
224	};
225
226	pinctrl_uart4_rts: uart4rtsgrp {
227		fsl,pins = <
228			/* SODIMM 222 */
229			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x184
230		>;
231	};
232};
233
234&pinctrl_gpio1 {
235	fsl,pins = <
236		/* SODIMM 206 */
237		MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4			0x1c4
238	>;
239};
240
241&pinctrl_gpio_hog1 {
242	fsl,pins = <
243		/* SODIMM 88 */
244		MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20			0x1c4
245		/* CPLD_int */
246		MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1				0x1c4
247		/* CPLD_reset */
248		MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2			0x1c4
249		/* SODIMM 94 */
250		MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3			0x1c4
251		/* SODIMM 96 */
252		MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4			0x1c4
253		/* CPLD_D[7] */
254		MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5			0x184
255		/* CPLD_D[6] */
256		MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0			0x184
257		/* CPLD_D[5] */
258		MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11			0x184
259		/* CPLD_D[4] */
260		MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12			0x184
261		/* CPLD_D[3] */
262		MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13			0x184
263		/* CPLD_D[2] */
264		MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14			0x184
265		/* CPLD_D[1] */
266		MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15			0x184
267		/* CPLD_D[0] */
268		MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16			0x184
269		/* KBD_intK */
270		MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27			0x1c4
271		/* DISP_reset */
272		MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22			0x1c4
273		/* KBD_intI */
274		MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23			0x1c4
275		/* SODIMM 46 */
276		MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24			0x1c4
277	>;
278};
279
280&pinctrl_uart1 {
281	fsl,pins = <
282		/* SODIMM 149 */
283		MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX			0x1c4
284		/* SODIMM 147 */
285		MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX			0x1c4
286		/* SODIMM 210 */
287		MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B			0x1c4
288		/* SODIMM 212 */
289		MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B			0x1c4
290	>;
291};
292
293&reg_usb_otg1_vbus {
294	/delete-property/ enable-active-high;
295	gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
296};
297
298&reg_usb_otg2_vbus {
299	/delete-property/ enable-active-high;
300	gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
301};
302
303&sai2 {
304	status = "disabled";
305};
306
307&uart1 {
308	uart-has-rtscts;
309	status = "okay";
310};
311
312&uart2 {
313	status = "okay";
314};
315
316&uart4 {
317	pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>;
318	linux,rs485-enabled-at-boot-time;
319	rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
320	status = "okay";
321};
322
323&usbotg1 {
324	dr_mode = "peripheral";
325	status = "okay";
326};
327
328&usbotg2 {
329	dr_mode = "host";
330	status = "okay";
331};
332
333&usdhc2 {
334	status = "okay";
335};
336