xref: /linux/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2019 Kontron Electronics GmbH
4 */
5
6/dts-v1/;
7
8#include "imx8mm-kontron-sl.dtsi"
9
10/ {
11	model = "Kontron BL i.MX8MM (N801X S)";
12	compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";
13
14	aliases {
15		ethernet1 = &usbnet;
16		rtc0 = &rx8900;
17		rtc1 = &snvs_rtc;
18	};
19
20	/* fixed crystal dedicated to mcp2515 */
21	osc_can: clock-osc-can {
22		compatible = "fixed-clock";
23		#clock-cells = <0>;
24		clock-frequency = <16000000>;
25		clock-output-names = "osc-can";
26	};
27
28	hdmi-out {
29		compatible = "hdmi-connector";
30		type = "a";
31
32		port {
33			hdmi_in_conn: endpoint {
34				remote-endpoint = <&bridge_out_conn>;
35			};
36		};
37	};
38
39	leds {
40		compatible = "gpio-leds";
41		pinctrl-names = "default";
42		pinctrl-0 = <&pinctrl_gpio_led>;
43
44		led1 {
45			label = "led1";
46			gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
47			linux,default-trigger = "heartbeat";
48		};
49
50		led2 {
51			label = "led2";
52			gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
53		};
54
55		led3 {
56			label = "led3";
57			gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
58		};
59
60		led4 {
61			label = "led4";
62			gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
63		};
64
65		led5 {
66			label = "led5";
67			gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
68		};
69
70		led6 {
71			label = "led6";
72			gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
73		};
74	};
75
76	pwm-beeper {
77		compatible = "pwm-beeper";
78		pwms = <&pwm2 0 5000 0>;
79	};
80
81	reg_rst_eth2: regulator-rst-eth2 {
82		compatible = "regulator-fixed";
83		regulator-name = "rst-usb-eth2";
84		pinctrl-names = "default";
85		pinctrl-0 = <&pinctrl_usb_eth2>;
86		gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
87		enable-active-high;
88		regulator-always-on;
89	};
90
91	reg_vdd_5v: regulator-5v {
92		compatible = "regulator-fixed";
93		regulator-name = "vdd-5v";
94		regulator-min-microvolt = <5000000>;
95		regulator-max-microvolt = <5000000>;
96	};
97};
98
99&ecspi2 {
100	pinctrl-names = "default";
101	pinctrl-0 = <&pinctrl_ecspi2>;
102	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
103	status = "okay";
104
105	can0: can@0 {
106		compatible = "microchip,mcp2515";
107		reg = <0>;
108		pinctrl-names = "default";
109		pinctrl-0 = <&pinctrl_can>;
110		clocks = <&osc_can>;
111		interrupt-parent = <&gpio4>;
112		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
113		spi-max-frequency = <10000000>;
114		vdd-supply = <&reg_vdd_3v3>;
115		xceiver-supply = <&reg_vdd_5v>;
116	};
117};
118
119&ecspi3 {
120	pinctrl-names = "default";
121	pinctrl-0 = <&pinctrl_ecspi3>;
122	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
123	status = "okay";
124};
125
126&fec1 {
127	pinctrl-names = "default";
128	pinctrl-0 = <&pinctrl_enet>;
129	phy-connection-type = "rgmii-rxid";
130	phy-handle = <&ethphy>;
131	status = "okay";
132
133	mdio {
134		#address-cells = <1>;
135		#size-cells = <0>;
136
137		ethphy: ethernet-phy@0 {
138			reg = <0>;
139			reset-assert-us = <1>;
140			reset-deassert-us = <15000>;
141			reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
142		};
143	};
144};
145
146&gpio4 {
147	pinctrl-names = "default";
148	pinctrl-0 = <&pinctrl_gpio4>;
149
150	dsi_mux_sel_hdmi: dsi-mux-sel-hdmi-hog {
151		gpio-hog;
152		gpios = <14 GPIO_ACTIVE_HIGH>;
153		output-high;
154		line-name = "dsi-mux-sel";
155	};
156
157	dsi_mux_sel_lvds: dsi-mux-sel-lvds-hog {
158		gpio-hog;
159		gpios = <14 GPIO_ACTIVE_HIGH>;
160		output-low;
161		line-name = "dsi-mux-sel";
162		status = "disabled";
163	};
164
165	dsi-mux-oe-hog {
166		gpio-hog;
167		gpios = <15 GPIO_ACTIVE_LOW>;
168		output-high;
169		line-name = "dsi-mux-oe";
170	};
171};
172
173&i2c3 {
174	clock-frequency = <400000>;
175	pinctrl-names = "default";
176	pinctrl-0 = <&pinctrl_i2c3>;
177	status = "okay";
178
179	lvds: bridge@2c {
180		compatible = "ti,sn65dsi84";
181		reg = <0x2c>;
182		enable-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
183		pinctrl-names = "default";
184		pinctrl-0 = <&pinctrl_sn65dsi84>;
185		status = "disabled";
186	};
187
188	hdmi: hdmi@39 {
189		compatible = "adi,adv7535";
190		reg = <0x39>;
191		pinctrl-names = "default";
192		pinctrl-0 = <&pinctrl_adv7535>;
193		adi,dsi-lanes = <4>;
194		interrupt-parent = <&gpio4>;
195		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
196		a2vdd-supply = <&reg_vdd_1v8>;
197		avdd-supply = <&reg_vdd_1v8>;
198		dvdd-supply = <&reg_vdd_1v8>;
199		pvdd-supply = <&reg_vdd_1v8>;
200		v1p2-supply = <&reg_vdd_1v8>;
201		v3p3-supply = <&reg_vdd_3v3>;
202
203		ports {
204			#address-cells = <1>;
205			#size-cells = <0>;
206
207			port@0 {
208				reg = <0>;
209
210				bridge_in_dsi_hdmi: endpoint {
211					remote-endpoint = <&mipi_dsi_out>;
212				};
213			};
214
215			port@1 {
216				reg = <1>;
217
218				bridge_out_conn: endpoint {
219					remote-endpoint = <&hdmi_in_conn>;
220				};
221			};
222		};
223	};
224};
225
226&i2c4 {
227	clock-frequency = <100000>;
228	pinctrl-names = "default";
229	pinctrl-0 = <&pinctrl_i2c4>;
230	status = "okay";
231
232	rx8900: rtc@32 {
233		compatible = "epson,rx8900";
234		reg = <0x32>;
235	};
236};
237
238&lcdif {
239	status = "okay";
240};
241
242&mipi_dsi {
243	samsung,esc-clock-frequency = <54000000>;
244	status = "okay";
245};
246
247&mipi_dsi_out {
248	remote-endpoint = <&bridge_in_dsi_hdmi>;
249};
250
251&pwm2 {
252	pinctrl-names = "default";
253	pinctrl-0 = <&pinctrl_pwm2>;
254	status = "okay";
255};
256
257&uart1 {
258	pinctrl-names = "default";
259	pinctrl-0 = <&pinctrl_uart1>;
260	uart-has-rtscts;
261	status = "okay";
262};
263
264&uart2 {
265	pinctrl-names = "default";
266	pinctrl-0 = <&pinctrl_uart2>;
267	linux,rs485-enabled-at-boot-time;
268	uart-has-rtscts;
269	status = "okay";
270};
271
272&usbotg1 {
273	dr_mode = "otg";
274	over-current-active-low;
275	status = "okay";
276};
277
278&usbotg2 {
279	dr_mode = "host";
280	disable-over-current;
281	#address-cells = <1>;
282	#size-cells = <0>;
283	status = "okay";
284
285	usb1@1 {
286		compatible = "usb424,9514";
287		reg = <1>;
288		#address-cells = <1>;
289		#size-cells = <0>;
290
291		usbnet: ethernet@1 {
292			compatible = "usb424,ec00";
293			reg = <1>;
294			local-mac-address = [ 00 00 00 00 00 00 ];
295		};
296	};
297};
298
299&usdhc2 {
300	pinctrl-names = "default", "state_100mhz", "state_200mhz";
301	pinctrl-0 = <&pinctrl_usdhc2>;
302	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
303	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
304	vmmc-supply = <&reg_vdd_3v3>;
305	vqmmc-supply = <&reg_nvcc_sd>;
306	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
307	status = "okay";
308};
309
310&iomuxc {
311	pinctrl-names = "default";
312	pinctrl-0 = <&pinctrl_gpio>;
313
314	pinctrl_adv7535: adv7535grp {
315		fsl,pins = <
316			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16		0x19
317		>;
318	};
319
320	pinctrl_can: cangrp {
321		fsl,pins = <
322			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x19
323		>;
324	};
325
326	pinctrl_ecspi2: ecspi2grp {
327		fsl,pins = <
328			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82
329			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82
330			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82
331			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x19
332		>;
333	};
334
335	pinctrl_ecspi3: ecspi3grp {
336		fsl,pins = <
337			MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO		0x82
338			MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI		0x82
339			MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK		0x82
340			MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25		0x19
341		>;
342	};
343
344	pinctrl_enet: enetgrp {
345		fsl,pins = <
346			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
347			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
348			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
349			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
350			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
351			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
352			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
353			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
354			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
355			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
356			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
357			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
358			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
359			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
360			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19 /* PHY RST */
361			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25		0x19 /* ETH IRQ */
362		>;
363	};
364
365	pinctrl_gpio_led: gpioledgrp {
366		fsl,pins = <
367			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19
368			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7		0x19
369			MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8		0x19
370			MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x19
371			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17		0x19
372			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x19
373			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x19
374		>;
375	};
376
377	pinctrl_gpio: gpiogrp {
378		fsl,pins = <
379			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x19
380			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
381			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
382			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19
383			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
384			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x19
385			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19
386			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x19
387		>;
388	};
389
390	pinctrl_gpio4: gpio4grp {
391		fsl,pins = <
392			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14		0x19
393			MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15		0x19
394		>;
395	};
396
397	pinctrl_i2c3: i2c3grp {
398		fsl,pins = <
399			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000083
400			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000083
401		>;
402	};
403
404	pinctrl_i2c4: i2c4grp {
405		fsl,pins = <
406			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000083
407			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000083
408		>;
409	};
410
411	pinctrl_pwm2: pwm2grp {
412		fsl,pins = <
413			MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT			0x19
414		>;
415	};
416
417	pinctrl_sn65dsi84: sn65dsi84grp {
418		fsl,pins = <
419			MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26		0x19
420			MX8MM_IOMUXC_SD2_WP_GPIO2_IO20			0x19
421		>;
422	};
423
424	pinctrl_uart1: uart1grp {
425		fsl,pins = <
426			MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX		0x0
427			MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX		0x0
428			MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B		0x0
429			MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B		0x0
430		>;
431	};
432
433	pinctrl_uart2: uart2grp {
434		fsl,pins = <
435			MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX		0x0
436			MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX		0x0
437			MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B		0x0
438			MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B		0x0
439		>;
440	};
441
442	pinctrl_usb_eth2: usbeth2grp {
443		fsl,pins = <
444			MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x19
445		>;
446	};
447
448	pinctrl_usdhc2: usdhc2grp {
449		fsl,pins = <
450			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x90
451			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0
452			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0
453			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0
454			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0
455			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0
456			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19
457			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xd0
458		>;
459	};
460
461	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
462		fsl,pins = <
463			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x94
464			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4
465			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4
466			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4
467			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4
468			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4
469			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19
470			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xd0
471		>;
472	};
473
474	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
475		fsl,pins = <
476			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x96
477			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6
478			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6
479			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6
480			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6
481			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6
482			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19
483			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xd0
484		>;
485	};
486};
487