1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022-2026 Josua Mayer <josua@solid-run.com> 4 */ 5 6#include "imx8dxl.dtsi" 7/ { 8 compatible = "solidrun,imx8dxl-sr-som", "fsl,imx8dxl"; 9 model = "SolidRun i.MX8DXL SoM"; 10 11 aliases { 12 i2c2 = &i2c2; 13 i2c3 = &i2c3; 14 mmc0 = &usdhc1; 15 mmc1 = &usdhc2; 16 serial0 = &lpuart0; 17 serial2 = &lpuart2; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 imx8dxl-cm4 { 25 compatible = "fsl,imx8qxp-cm4"; 26 clocks = <&clk_dummy>; 27 mboxes = <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>; 28 mbox-names = "tx", "rx", "rxdb"; 29 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 30 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 31 power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>; 32 fsl,entry-address = <0x34fe0000>; 33 fsl,resource-id = <IMX_SC_R_M4_0_PID0>; 34 }; 35 36 pps { 37 compatible = "pps-gpio"; 38 gpios = <&lsio_gpio2 6 GPIO_ACTIVE_HIGH>; 39 pinctrl-0 = <&gnss_pps_pins>; 40 pinctrl-names = "default"; 41 }; 42 43 v_1_2: regulator-1-2 { 44 compatible = "regulator-fixed"; 45 regulator-name = "1v2"; 46 pinctrl-0 = <®ulator_1_2_pins>; 47 pinctrl-names = "default"; 48 regulator-max-microvolt = <1200000>; 49 regulator-min-microvolt = <1200000>; 50 gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>; 51 enable-active-high; 52 }; 53 54 v_1_6: regulator-1-6 { 55 compatible = "regulator-fixed"; 56 regulator-name = "1v6"; 57 pinctrl-0 = <®ulator_1_6_pins>; 58 pinctrl-names = "default"; 59 regulator-max-microvolt = <1600000>; 60 regulator-min-microvolt = <1600000>; 61 vin-supply = <&v_1_8>; 62 gpio = <&lsio_gpio1 14 GPIO_ACTIVE_HIGH>; 63 enable-active-high; 64 }; 65 66 v_1_8: regulator-1-8 { 67 compatible = "regulator-fixed"; 68 regulator-name = "1v8"; 69 regulator-max-microvolt = <1800000>; 70 regulator-min-microvolt = <1800000>; 71 }; 72 73 v_1_8_se: regulator-1-8-secure-element { 74 compatible = "regulator-fixed"; 75 regulator-name = "1v8-se"; 76 pinctrl-0 = <®ulator_1_8_se_pins>; 77 pinctrl-names = "default"; 78 regulator-max-microvolt = <1800000>; 79 regulator-min-microvolt = <1800000>; 80 vin-supply = <&v_1_8>; 81 gpio = <&lsio_gpio3 18 GPIO_ACTIVE_HIGH>; 82 enable-active-high; 83 }; 84 85 v_3_3: regulator-3-3 { 86 compatible = "regulator-fixed"; 87 regulator-name = "3v3"; 88 regulator-max-microvolt = <3300000>; 89 regulator-min-microvolt = <3300000>; 90 }; 91 92 reserved-memory { 93 ranges; 94 #address-cells = <2>; 95 #size-cells = <2>; 96 97 /* global autoconfigured region for contiguous allocations */ 98 linux,cma { 99 compatible = "shared-dma-pool"; 100 alloc-ranges = <0 0x98000000 0 0x14000000>; 101 reusable; 102 size = <0 0x14000000>; 103 linux,cma-default; 104 }; 105 106 vdev0vring0: memory0@90000000 { 107 reg = <0 0x90000000 0 0x8000>; 108 no-map; 109 }; 110 111 vdev0vring1: memory@90008000 { 112 reg = <0 0x90008000 0 0x8000>; 113 no-map; 114 }; 115 116 vdev1vring0: memory@90010000 { 117 reg = <0 0x90010000 0 0x8000>; 118 no-map; 119 }; 120 121 vdev1vring1: memory@90018000 { 122 reg = <0 0x90018000 0 0x8000>; 123 no-map; 124 }; 125 126 rsc_table: memory-rsc-table@900ff000 { 127 reg = <0 0x900ff000 0 0x1000>; 128 no-map; 129 }; 130 131 vdevbuffer: memory-vdevbuffer@90400000 { 132 compatible = "shared-dma-pool"; 133 reg = <0 0x90400000 0 0x100000>; 134 no-map; 135 }; 136 137 /* 138 * Memory reserved for optee usage. Please do not use. 139 * This will be automatically added to dtb if OP-TEE is installed. 140 * optee@96000000 { 141 * reg = <0 0x96000000 0 0x2000000>; 142 * no-map; 143 * }; 144 */ 145 }; 146 147 memory@80000000 { 148 reg = <0x00000000 0x80000000 0 0x40000000>; 149 device_type = "memory"; 150 }; 151}; 152 153&i2c2 { 154 #address-cells = <1>; 155 #size-cells = <0>; 156 clock-frequency = <100000>; 157 pinctrl-0 = <&i2c2_pins>; 158 pinctrl-1 = <&i2c2_gpio_pins>; 159 pinctrl-names = "default", "gpio"; 160 scl-gpios = <&lsio_gpio3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 161 sda-gpios = <&lsio_gpio3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 162 status = "okay"; 163}; 164 165&i2c3 { 166 #address-cells = <1>; 167 #size-cells = <0>; 168 clock-frequency = <100000>; 169 pinctrl-0 = <&i2c3_pins>; 170 pinctrl-1 = <&i2c3_gpio_pins>; 171 pinctrl-names = "default", "gpio"; 172 scl-gpios = <&lsio_gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 173 sda-gpios = <&lsio_gpio3 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 174 status = "okay"; 175 176 magnetometer@1e { 177 compatible = "st,iis2mdc"; 178 reg = <0x1e>; 179 interrupt-parent = <&lsio_gpio2>; 180 interrupts = <10 IRQ_TYPE_EDGE_RISING>; 181 pinctrl-0 = <&magnetometer_pins>; 182 pinctrl-names = "default"; 183 st,drdy-int-pin = <1>; 184 }; 185 186 /* pressure-sensor@5c */ 187 188 inertial-sensor@6b { 189 compatible = "st,ism330dhcx"; 190 reg = <0x6b>; 191 interrupt-parent = <&lsio_gpio2>; 192 interrupts = <11 IRQ_TYPE_EDGE_RISING>; 193 pinctrl-0 = <&imu_pins>; 194 pinctrl-names = "default"; 195 st,drdy-int-pin = <1>; 196 }; 197}; 198 199&iomuxc { 200 pinctrl-0 = <&pinctrl_hog>; 201 pinctrl-names = "default"; 202 203 pinctrl_hog: hoggrp { 204 fsl,pins = < 205 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 206 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0 207 >; 208 }; 209 210 dsrc_pins: pinctrl-dsrc-grp { 211 fsl,pins = < 212 /* reset: io without pull */ 213 IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10 0x0000060 214 215 /* 216 * boot0: io without pull 217 * After reset, this pin selects radio boot media: 218 * - 0: flash spi 219 * - 1: slave sdio 220 * Once the firmware boots however, the radio controls 221 * this pin for flow-control to signal readiness. 222 */ 223 IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09 0x0000060 224 >; 225 }; 226 227 gnss_pins: pinctrl-gnss-grp { 228 fsl,pins = < 229 /* gps reset: input with pull-up */ 230 IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN 0x0000021 231 /* gps interrupt: io without pull-up */ 232 IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN 0x0000061 233 >; 234 }; 235 236 gnss_pps_pins: pinctrl-gnss-pps-grp { 237 fsl,pins = < 238 /* gps timepulse: input without pull-up */ 239 IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN 0x0000061 240 >; 241 }; 242 243 i2c2_gpio_pins: pinctrl-i2c2-gpio-grp { 244 fsl,pins = < 245 /* io with pull-up and weak drive */ 246 IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00 0x00000021 247 /* io with pull-up, weak drive, open-drain */ 248 IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01 0x02000021 249 >; 250 }; 251 252 i2c2_pins: pinctrl-i2c2-grp { 253 fsl,pins = < 254 /* io with pull-up and weak drive */ 255 IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 256 IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 257 >; 258 }; 259 260 i2c3_gpio_pins: pinctrl-i2c3-gpio-grp { 261 fsl,pins = < 262 /* io with pull-up and weak drive */ 263 IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 0x00000021 264 /* io with pull-up, weak drive, open-drain */ 265 IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02 0x02000021 266 >; 267 }; 268 269 i2c3_pins: pinctrl-i2c3-grp { 270 fsl,pins = < 271 /* io with pull-up and weak drive */ 272 IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 273 IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 274 >; 275 }; 276 277 imu_pins: pinctrl-imu-grp { 278 fsl,pins = < 279 /* interrupt: io with pull-down */ 280 IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN 0x0000041 281 >; 282 }; 283 284 lpspi2_pins: pinctrl-lpspi2-grp { 285 fsl,pins = < 286 IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK 0x600004c 287 IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO 0x600004c 288 IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI 0x600004c 289 IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 0x6000021 290 >; 291 }; 292 293 lpuart0_pins: pinctrl-lpuart0-grp { 294 fsl,pins = < 295 IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020 296 IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020 297 >; 298 }; 299 300 lpuart2_pins: pinctrl-lpuart2-grp { 301 fsl,pins = < 302 IMX8DXL_UART2_TX_ADMA_UART2_TX 0x06000020 303 IMX8DXL_UART2_RX_ADMA_UART2_RX 0x06000020 304 >; 305 }; 306 307 magnetometer_pins: pinctrl-magnetometer-grp { 308 fsl,pins = < 309 /* interrupt: io with pull-down */ 310 IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN 0x0000041 311 >; 312 }; 313 314 regulator_1_2_pins: pinctrl-regulator-1-2-grp { 315 fsl,pins = < 316 /* io without pull-up */ 317 /* has etxernal pull-down */ 318 IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13 0x0000061 319 >; 320 }; 321 322 regulator_1_6_pins: pinctrl-regulator-1-6-grp { 323 fsl,pins = < 324 /* io without pull-up */ 325 /* has etxernal pull-down */ 326 IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14 0x0000061 327 >; 328 }; 329 330 regulator_1_8_se_pins: pinctrl-regulator-1-8-secure-element-grp { 331 fsl,pins = < 332 /* v2x-secure-element power switch: io with pull-down */ 333 IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x0000041 334 >; 335 }; 336 337 se_pins: pinctrl-secure-element-grp { 338 fsl,pins = < 339 /* v2x-secure-element reset: io with pull-up */ 340 IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x0000021 341 342 /* 343 * v2x-secure-element gpio0: io with pull-up 344 * pulled low by sxf after boot indicating ready for commands 345 */ 346 IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x0000021 347 348 /* v2x-secure-element gpio1: io with pull-up */ 349 IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x0000021 350 >; 351 }; 352 353 usdhc1_pins: pinctrl-usdhc1-grp { 354 fsl,pins = < 355 IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 356 IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 357 IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 358 IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 359 IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 360 IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 361 IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 362 IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 363 IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 364 IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 365 IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 366 IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000061 367 >; 368 }; 369 370 usdhc2_pins: pinctrl-usdhc2-grp { 371 fsl,pins = < 372 IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000040 373 IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 374 IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 375 IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 376 IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 377 IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 378 >; 379 }; 380}; 381 382&lpspi2 { 383 cs-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; 384 num-cs = <1>; 385 pinctrl-0 = <&lpspi2_pins>, <&se_pins>; 386 pinctrl-names = "default"; 387 status = "okay"; 388}; 389 390/* console */ 391&lpuart0 { 392 pinctrl-0 = <&lpuart0_pins>; 393 pinctrl-names = "default"; 394 status = "okay"; 395}; 396 397/* gnss */ 398&lpuart2 { 399 pinctrl-0 = <&lpuart2_pins>, <&gnss_pins>; 400 pinctrl-names = "default"; 401 status = "okay"; 402}; 403 404&lsio_gpio3 { 405 gpio-line-names = "", "", "", "", "", "", "", "", 406 "", "", "", "", "", "", "", "", 407 "", "", "", "SXF_RST", "SXF_GPIO0", "SXF_GPIO1", "", "", 408 "", "", "", "", "", "", "", ""; 409}; 410 411&lsio_mu5 { 412 status = "okay"; 413}; 414 415/* OTG port for boot */ 416&usbotg1 { 417 adp-disable; 418 disable-over-current; 419 dr_mode = "peripheral"; 420 hnp-disable; 421 power-active-high; 422 srp-disable; 423 status = "okay"; 424}; 425 426&usbphy1 { 427 status = "okay"; 428}; 429 430/* eMMC */ 431&usdhc1 { 432 bus-width = <8>; 433 cap-mmc-hw-reset; 434 non-removable; 435 no-sd; 436 no-sdio; 437 pinctrl-0 = <&usdhc1_pins>; 438 pinctrl-1 = <&usdhc1_pins>; 439 pinctrl-2 = <&usdhc1_pins>; 440 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 441 vmmc-supply = <&v_3_3>; 442 vqmmc-supply = <&v_1_8>; 443 status = "okay"; 444}; 445 446/* DSRC Radio */ 447&usdhc2 { 448 bus-width = <4>; 449 keep-power-in-suspend; 450 max-frequency = <40000000>; 451 non-removable; 452 no-sd; 453 pinctrl-0 = <&usdhc2_pins>, <&dsrc_pins>; 454 pinctrl-names = "default"; 455 vmmc-supply = <&v_3_3>; 456 vqmmc-supply = <&v_1_8>; 457 status = "okay"; 458}; 459