1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree Include file for Layerscape-LX2160A family SoC. 4// 5// Copyright 2018-2020 NXP 6 7#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/memreserve/ 0x80000000 0x00010000; 13 14/ { 15 compatible = "fsl,lx2160a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 rtc1 = &ftm_alarm0; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 // 8 clusters having 2 Cortex-A72 cores each 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a72"; 32 enable-method = "psci"; 33 reg = <0x0>; 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 35 d-cache-size = <0x8000>; 36 d-cache-line-size = <64>; 37 d-cache-sets = <128>; 38 i-cache-size = <0xc000>; 39 i-cache-line-size = <64>; 40 i-cache-sets = <192>; 41 next-level-cache = <&cluster0_l2>; 42 cpu-idle-states = <&cpu_pw15>; 43 #cooling-cells = <2>; 44 }; 45 46 cpu1: cpu@1 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a72"; 49 enable-method = "psci"; 50 reg = <0x1>; 51 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 52 d-cache-size = <0x8000>; 53 d-cache-line-size = <64>; 54 d-cache-sets = <128>; 55 i-cache-size = <0xc000>; 56 i-cache-line-size = <64>; 57 i-cache-sets = <192>; 58 next-level-cache = <&cluster0_l2>; 59 cpu-idle-states = <&cpu_pw15>; 60 #cooling-cells = <2>; 61 }; 62 63 cpu100: cpu@100 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a72"; 66 enable-method = "psci"; 67 reg = <0x100>; 68 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 69 d-cache-size = <0x8000>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 i-cache-size = <0xc000>; 73 i-cache-line-size = <64>; 74 i-cache-sets = <192>; 75 next-level-cache = <&cluster1_l2>; 76 cpu-idle-states = <&cpu_pw15>; 77 #cooling-cells = <2>; 78 }; 79 80 cpu101: cpu@101 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a72"; 83 enable-method = "psci"; 84 reg = <0x101>; 85 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 86 d-cache-size = <0x8000>; 87 d-cache-line-size = <64>; 88 d-cache-sets = <128>; 89 i-cache-size = <0xc000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <192>; 92 next-level-cache = <&cluster1_l2>; 93 cpu-idle-states = <&cpu_pw15>; 94 #cooling-cells = <2>; 95 }; 96 97 cpu200: cpu@200 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a72"; 100 enable-method = "psci"; 101 reg = <0x200>; 102 clocks = <&clockgen QORIQ_CLK_CMUX 2>; 103 d-cache-size = <0x8000>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 i-cache-size = <0xc000>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <192>; 109 next-level-cache = <&cluster2_l2>; 110 cpu-idle-states = <&cpu_pw15>; 111 #cooling-cells = <2>; 112 }; 113 114 cpu201: cpu@201 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a72"; 117 enable-method = "psci"; 118 reg = <0x201>; 119 clocks = <&clockgen QORIQ_CLK_CMUX 2>; 120 d-cache-size = <0x8000>; 121 d-cache-line-size = <64>; 122 d-cache-sets = <128>; 123 i-cache-size = <0xc000>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <192>; 126 next-level-cache = <&cluster2_l2>; 127 cpu-idle-states = <&cpu_pw15>; 128 #cooling-cells = <2>; 129 }; 130 131 cpu300: cpu@300 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a72"; 134 enable-method = "psci"; 135 reg = <0x300>; 136 clocks = <&clockgen QORIQ_CLK_CMUX 3>; 137 d-cache-size = <0x8000>; 138 d-cache-line-size = <64>; 139 d-cache-sets = <128>; 140 i-cache-size = <0xc000>; 141 i-cache-line-size = <64>; 142 i-cache-sets = <192>; 143 next-level-cache = <&cluster3_l2>; 144 cpu-idle-states = <&cpu_pw15>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu301: cpu@301 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a72"; 151 enable-method = "psci"; 152 reg = <0x301>; 153 clocks = <&clockgen QORIQ_CLK_CMUX 3>; 154 d-cache-size = <0x8000>; 155 d-cache-line-size = <64>; 156 d-cache-sets = <128>; 157 i-cache-size = <0xc000>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <192>; 160 next-level-cache = <&cluster3_l2>; 161 cpu-idle-states = <&cpu_pw15>; 162 #cooling-cells = <2>; 163 }; 164 165 cpu400: cpu@400 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a72"; 168 enable-method = "psci"; 169 reg = <0x400>; 170 clocks = <&clockgen QORIQ_CLK_CMUX 4>; 171 d-cache-size = <0x8000>; 172 d-cache-line-size = <64>; 173 d-cache-sets = <128>; 174 i-cache-size = <0xc000>; 175 i-cache-line-size = <64>; 176 i-cache-sets = <192>; 177 next-level-cache = <&cluster4_l2>; 178 cpu-idle-states = <&cpu_pw15>; 179 #cooling-cells = <2>; 180 }; 181 182 cpu401: cpu@401 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a72"; 185 enable-method = "psci"; 186 reg = <0x401>; 187 clocks = <&clockgen QORIQ_CLK_CMUX 4>; 188 d-cache-size = <0x8000>; 189 d-cache-line-size = <64>; 190 d-cache-sets = <128>; 191 i-cache-size = <0xc000>; 192 i-cache-line-size = <64>; 193 i-cache-sets = <192>; 194 next-level-cache = <&cluster4_l2>; 195 cpu-idle-states = <&cpu_pw15>; 196 #cooling-cells = <2>; 197 }; 198 199 cpu500: cpu@500 { 200 device_type = "cpu"; 201 compatible = "arm,cortex-a72"; 202 enable-method = "psci"; 203 reg = <0x500>; 204 clocks = <&clockgen QORIQ_CLK_CMUX 5>; 205 d-cache-size = <0x8000>; 206 d-cache-line-size = <64>; 207 d-cache-sets = <128>; 208 i-cache-size = <0xc000>; 209 i-cache-line-size = <64>; 210 i-cache-sets = <192>; 211 next-level-cache = <&cluster5_l2>; 212 cpu-idle-states = <&cpu_pw15>; 213 #cooling-cells = <2>; 214 }; 215 216 cpu501: cpu@501 { 217 device_type = "cpu"; 218 compatible = "arm,cortex-a72"; 219 enable-method = "psci"; 220 reg = <0x501>; 221 clocks = <&clockgen QORIQ_CLK_CMUX 5>; 222 d-cache-size = <0x8000>; 223 d-cache-line-size = <64>; 224 d-cache-sets = <128>; 225 i-cache-size = <0xc000>; 226 i-cache-line-size = <64>; 227 i-cache-sets = <192>; 228 next-level-cache = <&cluster5_l2>; 229 cpu-idle-states = <&cpu_pw15>; 230 #cooling-cells = <2>; 231 }; 232 233 cpu600: cpu@600 { 234 device_type = "cpu"; 235 compatible = "arm,cortex-a72"; 236 enable-method = "psci"; 237 reg = <0x600>; 238 clocks = <&clockgen QORIQ_CLK_CMUX 6>; 239 d-cache-size = <0x8000>; 240 d-cache-line-size = <64>; 241 d-cache-sets = <128>; 242 i-cache-size = <0xc000>; 243 i-cache-line-size = <64>; 244 i-cache-sets = <192>; 245 next-level-cache = <&cluster6_l2>; 246 cpu-idle-states = <&cpu_pw15>; 247 #cooling-cells = <2>; 248 }; 249 250 cpu601: cpu@601 { 251 device_type = "cpu"; 252 compatible = "arm,cortex-a72"; 253 enable-method = "psci"; 254 reg = <0x601>; 255 clocks = <&clockgen QORIQ_CLK_CMUX 6>; 256 d-cache-size = <0x8000>; 257 d-cache-line-size = <64>; 258 d-cache-sets = <128>; 259 i-cache-size = <0xc000>; 260 i-cache-line-size = <64>; 261 i-cache-sets = <192>; 262 next-level-cache = <&cluster6_l2>; 263 cpu-idle-states = <&cpu_pw15>; 264 #cooling-cells = <2>; 265 }; 266 267 cpu700: cpu@700 { 268 device_type = "cpu"; 269 compatible = "arm,cortex-a72"; 270 enable-method = "psci"; 271 reg = <0x700>; 272 clocks = <&clockgen QORIQ_CLK_CMUX 7>; 273 d-cache-size = <0x8000>; 274 d-cache-line-size = <64>; 275 d-cache-sets = <128>; 276 i-cache-size = <0xc000>; 277 i-cache-line-size = <64>; 278 i-cache-sets = <192>; 279 next-level-cache = <&cluster7_l2>; 280 cpu-idle-states = <&cpu_pw15>; 281 #cooling-cells = <2>; 282 }; 283 284 cpu701: cpu@701 { 285 device_type = "cpu"; 286 compatible = "arm,cortex-a72"; 287 enable-method = "psci"; 288 reg = <0x701>; 289 clocks = <&clockgen QORIQ_CLK_CMUX 7>; 290 d-cache-size = <0x8000>; 291 d-cache-line-size = <64>; 292 d-cache-sets = <128>; 293 i-cache-size = <0xc000>; 294 i-cache-line-size = <64>; 295 i-cache-sets = <192>; 296 next-level-cache = <&cluster7_l2>; 297 cpu-idle-states = <&cpu_pw15>; 298 #cooling-cells = <2>; 299 }; 300 301 cluster0_l2: l2-cache0 { 302 compatible = "cache"; 303 cache-unified; 304 cache-size = <0x100000>; 305 cache-line-size = <64>; 306 cache-sets = <1024>; 307 cache-level = <2>; 308 }; 309 310 cluster1_l2: l2-cache1 { 311 compatible = "cache"; 312 cache-unified; 313 cache-size = <0x100000>; 314 cache-line-size = <64>; 315 cache-sets = <1024>; 316 cache-level = <2>; 317 }; 318 319 cluster2_l2: l2-cache2 { 320 compatible = "cache"; 321 cache-unified; 322 cache-size = <0x100000>; 323 cache-line-size = <64>; 324 cache-sets = <1024>; 325 cache-level = <2>; 326 }; 327 328 cluster3_l2: l2-cache3 { 329 compatible = "cache"; 330 cache-unified; 331 cache-size = <0x100000>; 332 cache-line-size = <64>; 333 cache-sets = <1024>; 334 cache-level = <2>; 335 }; 336 337 cluster4_l2: l2-cache4 { 338 compatible = "cache"; 339 cache-unified; 340 cache-size = <0x100000>; 341 cache-line-size = <64>; 342 cache-sets = <1024>; 343 cache-level = <2>; 344 }; 345 346 cluster5_l2: l2-cache5 { 347 compatible = "cache"; 348 cache-unified; 349 cache-size = <0x100000>; 350 cache-line-size = <64>; 351 cache-sets = <1024>; 352 cache-level = <2>; 353 }; 354 355 cluster6_l2: l2-cache6 { 356 compatible = "cache"; 357 cache-unified; 358 cache-size = <0x100000>; 359 cache-line-size = <64>; 360 cache-sets = <1024>; 361 cache-level = <2>; 362 }; 363 364 cluster7_l2: l2-cache7 { 365 compatible = "cache"; 366 cache-unified; 367 cache-size = <0x100000>; 368 cache-line-size = <64>; 369 cache-sets = <1024>; 370 cache-level = <2>; 371 }; 372 373 cpu_pw15: cpu-pw15 { 374 compatible = "arm,idle-state"; 375 idle-state-name = "PW15"; 376 arm,psci-suspend-param = <0x0>; 377 entry-latency-us = <2000>; 378 exit-latency-us = <2000>; 379 min-residency-us = <6000>; 380 }; 381 }; 382 383 gic: interrupt-controller@6000000 { 384 compatible = "arm,gic-v3"; 385 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 386 <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 387 // SGI_base) 388 <0x0 0x0c0c0000 0 0x2000>, // GICC 389 <0x0 0x0c0d0000 0 0x1000>, // GICH 390 <0x0 0x0c0e0000 0 0x20000>; // GICV 391 #interrupt-cells = <3>; 392 #address-cells = <2>; 393 #size-cells = <2>; 394 ranges; 395 interrupt-controller; 396 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 397 398 its: msi-controller@6020000 { 399 compatible = "arm,gic-v3-its"; 400 msi-controller; 401 #msi-cells = <1>; 402 reg = <0x0 0x6020000 0 0x20000>; 403 }; 404 }; 405 406 timer { 407 compatible = "arm,armv8-timer"; 408 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 412 }; 413 414 pmu { 415 compatible = "arm,cortex-a72-pmu"; 416 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 417 }; 418 419 psci { 420 compatible = "arm,psci-0.2"; 421 method = "smc"; 422 }; 423 424 memory@80000000 { 425 // DRAM space - 1, size : 2 GB DRAM 426 device_type = "memory"; 427 reg = <0x00000000 0x80000000 0 0x80000000>; 428 }; 429 430 ddr1: memory-controller@1080000 { 431 compatible = "fsl,qoriq-memory-controller"; 432 reg = <0x0 0x1080000 0x0 0x1000>; 433 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 434 little-endian; 435 }; 436 437 ddr2: memory-controller@1090000 { 438 compatible = "fsl,qoriq-memory-controller"; 439 reg = <0x0 0x1090000 0x0 0x1000>; 440 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 441 little-endian; 442 }; 443 444 // One clock unit-sysclk node which bootloader require during DT fix-up 445 sysclk: sysclk { 446 compatible = "fixed-clock"; 447 #clock-cells = <0>; 448 clock-frequency = <100000000>; // fixed up by bootloader 449 clock-output-names = "sysclk"; 450 }; 451 452 thermal-zones { 453 cluster6-7-thermal { 454 polling-delay-passive = <1000>; 455 polling-delay = <5000>; 456 thermal-sensors = <&tmu 0>; 457 458 trips { 459 cluster6_7_alert: cluster6-7-alert { 460 temperature = <85000>; 461 hysteresis = <2000>; 462 type = "passive"; 463 }; 464 465 cluster6_7_crit: cluster6-7-crit { 466 temperature = <95000>; 467 hysteresis = <2000>; 468 type = "critical"; 469 }; 470 }; 471 472 cooling-maps { 473 map0 { 474 trip = <&cluster6_7_alert>; 475 cooling-device = 476 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 477 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 478 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 479 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 480 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 481 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 482 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 483 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 484 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 485 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 486 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 487 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 488 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 489 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 490 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 491 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 492 }; 493 }; 494 }; 495 496 ddr-ctrl5-thermal { 497 polling-delay-passive = <1000>; 498 polling-delay = <5000>; 499 thermal-sensors = <&tmu 1>; 500 501 trips { 502 cluster5_alert: ddr-cluster5-alert { 503 temperature = <85000>; 504 hysteresis = <2000>; 505 type = "passive"; 506 }; 507 508 cluster5_crit: ddr-cluster5-crit { 509 temperature = <95000>; 510 hysteresis = <2000>; 511 type = "critical"; 512 }; 513 }; 514 }; 515 516 wriop-thermal { 517 polling-delay-passive = <1000>; 518 polling-delay = <5000>; 519 thermal-sensors = <&tmu 2>; 520 521 trips { 522 wriop_alert: wriop-alert { 523 temperature = <85000>; 524 hysteresis = <2000>; 525 type = "passive"; 526 }; 527 528 wriop_crit: wriop-crit { 529 temperature = <95000>; 530 hysteresis = <2000>; 531 type = "critical"; 532 }; 533 }; 534 }; 535 536 dce-thermal { 537 polling-delay-passive = <1000>; 538 polling-delay = <5000>; 539 thermal-sensors = <&tmu 3>; 540 541 trips { 542 dce_qbman_alert: dce-qbman-alert { 543 temperature = <85000>; 544 hysteresis = <2000>; 545 type = "passive"; 546 }; 547 548 dce_qbman_crit: dce-qbman-crit { 549 temperature = <95000>; 550 hysteresis = <2000>; 551 type = "critical"; 552 }; 553 }; 554 }; 555 556 ccn-thermal { 557 polling-delay-passive = <1000>; 558 polling-delay = <5000>; 559 thermal-sensors = <&tmu 4>; 560 561 trips { 562 ccn_dpaa_alert: ccn-dpaa-alert { 563 temperature = <85000>; 564 hysteresis = <2000>; 565 type = "passive"; 566 }; 567 568 ccn_dpaa_crit: ccn-dpaa-crit { 569 temperature = <95000>; 570 hysteresis = <2000>; 571 type = "critical"; 572 }; 573 }; 574 }; 575 576 cluster4-thermal { 577 polling-delay-passive = <1000>; 578 polling-delay = <5000>; 579 thermal-sensors = <&tmu 5>; 580 581 trips { 582 cluster4_alert: clust4-hsio3-alert { 583 temperature = <85000>; 584 hysteresis = <2000>; 585 type = "passive"; 586 }; 587 588 cluster4_crit: clust4-hsio3-crit { 589 temperature = <95000>; 590 hysteresis = <2000>; 591 type = "critical"; 592 }; 593 }; 594 }; 595 596 cluster2-3-thermal { 597 polling-delay-passive = <1000>; 598 polling-delay = <5000>; 599 thermal-sensors = <&tmu 6>; 600 601 trips { 602 cluster2_3_alert: cluster2-3-alert { 603 temperature = <85000>; 604 hysteresis = <2000>; 605 type = "passive"; 606 }; 607 608 cluster2_3_crit: cluster2-3-crit { 609 temperature = <95000>; 610 hysteresis = <2000>; 611 type = "critical"; 612 }; 613 }; 614 }; 615 }; 616 617 soc: soc { 618 compatible = "simple-bus"; 619 #address-cells = <2>; 620 #size-cells = <2>; 621 ranges; 622 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 623 624 crypto: crypto@8000000 { 625 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 626 fsl,sec-era = <10>; 627 #address-cells = <1>; 628 #size-cells = <1>; 629 ranges = <0x0 0x00 0x8000000 0x100000>; 630 reg = <0x00 0x8000000 0x0 0x100000>; 631 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 632 dma-coherent; 633 status = "disabled"; 634 635 sec_jr0: jr@10000 { 636 compatible = "fsl,sec-v5.0-job-ring", 637 "fsl,sec-v4.0-job-ring"; 638 reg = <0x10000 0x10000>; 639 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 640 }; 641 642 sec_jr1: jr@20000 { 643 compatible = "fsl,sec-v5.0-job-ring", 644 "fsl,sec-v4.0-job-ring"; 645 reg = <0x20000 0x10000>; 646 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 647 }; 648 649 sec_jr2: jr@30000 { 650 compatible = "fsl,sec-v5.0-job-ring", 651 "fsl,sec-v4.0-job-ring"; 652 reg = <0x30000 0x10000>; 653 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 654 }; 655 656 sec_jr3: jr@40000 { 657 compatible = "fsl,sec-v5.0-job-ring", 658 "fsl,sec-v4.0-job-ring"; 659 reg = <0x40000 0x10000>; 660 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 661 }; 662 }; 663 664 clockgen: clock-controller@1300000 { 665 compatible = "fsl,lx2160a-clockgen"; 666 reg = <0 0x1300000 0 0xa0000>; 667 #clock-cells = <2>; 668 clocks = <&sysclk>; 669 }; 670 671 dcfg: syscon@1e00000 { 672 compatible = "fsl,lx2160a-dcfg", "syscon"; 673 reg = <0x0 0x1e00000 0x0 0x10000>; 674 little-endian; 675 }; 676 677 sfp: efuse@1e80000 { 678 compatible = "fsl,ls1028a-sfp"; 679 reg = <0x0 0x1e80000 0x0 0x10000>; 680 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 681 QORIQ_CLK_PLL_DIV(4)>; 682 clock-names = "sfp"; 683 }; 684 685 isc: syscon@1f70000 { 686 compatible = "fsl,lx2160a-isc", "syscon"; 687 reg = <0x0 0x1f70000 0x0 0x10000>; 688 little-endian; 689 #address-cells = <1>; 690 #size-cells = <1>; 691 ranges = <0x0 0x0 0x1f70000 0x10000>; 692 693 extirq: interrupt-controller@14 { 694 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq"; 695 #interrupt-cells = <2>; 696 #address-cells = <0>; 697 interrupt-controller; 698 reg = <0x14 4>; 699 interrupt-map = 700 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 701 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 702 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 703 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 704 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 705 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 706 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 707 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 708 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 709 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 710 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 711 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 712 interrupt-map-mask = <0xf 0x0>; 713 }; 714 }; 715 716 tmu: tmu@1f80000 { 717 compatible = "fsl,qoriq-tmu"; 718 reg = <0x0 0x1f80000 0x0 0x10000>; 719 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 720 fsl,tmu-range = <0x800000e6 0x8001017d>; 721 fsl,tmu-calibration = 722 /* Calibration data group 1 */ 723 <0x00000000 0x00000035>, 724 /* Calibration data group 2 */ 725 <0x00000001 0x00000154>; 726 little-endian; 727 #thermal-sensor-cells = <1>; 728 }; 729 730 i2c0: i2c@2000000 { 731 compatible = "fsl,vf610-i2c"; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 reg = <0x0 0x2000000 0x0 0x10000>; 735 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 736 clock-names = "ipg"; 737 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 738 QORIQ_CLK_PLL_DIV(16)>; 739 pinctrl-names = "default", "gpio"; 740 pinctrl-0 = <&i2c0_pins>; 741 pinctrl-1 = <&gpio0_3_2_pins>; 742 scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 743 sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 744 status = "disabled"; 745 }; 746 747 i2c1: i2c@2010000 { 748 compatible = "fsl,vf610-i2c"; 749 #address-cells = <1>; 750 #size-cells = <0>; 751 reg = <0x0 0x2010000 0x0 0x10000>; 752 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 753 clock-names = "ipg"; 754 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 755 QORIQ_CLK_PLL_DIV(16)>; 756 pinctrl-names = "default", "gpio"; 757 pinctrl-0 = <&i2c1_pins>; 758 pinctrl-1 = <&gpio0_31_30_pins>; 759 scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 760 sda-gpios = <&gpio0 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 761 status = "disabled"; 762 }; 763 764 i2c2: i2c@2020000 { 765 compatible = "fsl,vf610-i2c"; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 reg = <0x0 0x2020000 0x0 0x10000>; 769 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 770 clock-names = "ipg"; 771 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 772 QORIQ_CLK_PLL_DIV(16)>; 773 pinctrl-names = "default", "gpio"; 774 pinctrl-0 = <&i2c2_pins>; 775 pinctrl-1 = <&gpio0_29_28_pins>; 776 scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 777 sda-gpios = <&gpio0 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 778 status = "disabled"; 779 }; 780 781 i2c3: i2c@2030000 { 782 compatible = "fsl,vf610-i2c"; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 reg = <0x0 0x2030000 0x0 0x10000>; 786 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 787 clock-names = "ipg"; 788 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 789 QORIQ_CLK_PLL_DIV(16)>; 790 pinctrl-names = "default", "gpio"; 791 pinctrl-0 = <&i2c3_pins>; 792 pinctrl-1 = <&gpio0_27_26_pins>; 793 scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 794 sda-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 795 status = "disabled"; 796 }; 797 798 i2c4: i2c@2040000 { 799 compatible = "fsl,vf610-i2c"; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 reg = <0x0 0x2040000 0x0 0x10000>; 803 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 804 clock-names = "ipg"; 805 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 806 QORIQ_CLK_PLL_DIV(16)>; 807 pinctrl-names = "default", "gpio"; 808 pinctrl-0 = <&i2c4_pins>; 809 pinctrl-1 = <&gpio0_25_24_pins>; 810 scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 811 sda-gpios = <&gpio0 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 812 status = "disabled"; 813 }; 814 815 i2c5: i2c@2050000 { 816 compatible = "fsl,vf610-i2c"; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 reg = <0x0 0x2050000 0x0 0x10000>; 820 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 821 clock-names = "ipg"; 822 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 823 QORIQ_CLK_PLL_DIV(16)>; 824 pinctrl-names = "default", "gpio"; 825 pinctrl-0 = <&i2c5_pins>; 826 pinctrl-1 = <&gpio0_23_22_pins>; 827 scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 828 sda-gpios = <&gpio0 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 829 status = "disabled"; 830 }; 831 832 i2c6: i2c@2060000 { 833 compatible = "fsl,vf610-i2c"; 834 #address-cells = <1>; 835 #size-cells = <0>; 836 reg = <0x0 0x2060000 0x0 0x10000>; 837 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 838 clock-names = "ipg"; 839 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 840 QORIQ_CLK_PLL_DIV(16)>; 841 pinctrl-names = "default", "gpio"; 842 pinctrl-0 = <&i2c6_i2c7_pins>; 843 pinctrl-1 = <&gpio1_18_15_pins>; 844 scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 845 sda-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 846 status = "disabled"; 847 }; 848 849 i2c7: i2c@2070000 { 850 compatible = "fsl,vf610-i2c"; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 reg = <0x0 0x2070000 0x0 0x10000>; 854 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 855 clock-names = "ipg"; 856 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 857 QORIQ_CLK_PLL_DIV(16)>; 858 pinctrl-names = "default", "gpio"; 859 pinctrl-0 = <&i2c6_i2c7_pins>; 860 pinctrl-1 = <&gpio1_18_15_pins>; 861 scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 862 sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 863 status = "disabled"; 864 }; 865 866 fspi: spi@20c0000 { 867 compatible = "nxp,lx2160a-fspi"; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 reg = <0x0 0x20c0000 0x0 0x10000>, 871 <0x0 0x20000000 0x0 0x10000000>; 872 reg-names = "fspi_base", "fspi_mmap"; 873 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 875 QORIQ_CLK_PLL_DIV(4)>, 876 <&clockgen QORIQ_CLK_PLATFORM_PLL 877 QORIQ_CLK_PLL_DIV(4)>; 878 clock-names = "fspi_en", "fspi"; 879 status = "disabled"; 880 }; 881 882 dspi0: spi@2100000 { 883 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 reg = <0x0 0x2100000 0x0 0x10000>; 887 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 889 QORIQ_CLK_PLL_DIV(8)>; 890 clock-names = "dspi"; 891 spi-num-chipselects = <5>; 892 bus-num = <0>; 893 status = "disabled"; 894 }; 895 896 dspi1: spi@2110000 { 897 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 898 #address-cells = <1>; 899 #size-cells = <0>; 900 reg = <0x0 0x2110000 0x0 0x10000>; 901 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 903 QORIQ_CLK_PLL_DIV(8)>; 904 clock-names = "dspi"; 905 spi-num-chipselects = <5>; 906 bus-num = <1>; 907 status = "disabled"; 908 }; 909 910 dspi2: spi@2120000 { 911 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 reg = <0x0 0x2120000 0x0 0x10000>; 915 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 917 QORIQ_CLK_PLL_DIV(8)>; 918 clock-names = "dspi"; 919 spi-num-chipselects = <5>; 920 bus-num = <2>; 921 status = "disabled"; 922 }; 923 924 esdhc0: mmc@2140000 { 925 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 926 reg = <0x0 0x2140000 0x0 0x10000>; 927 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 929 QORIQ_CLK_PLL_DIV(2)>; 930 dma-coherent; 931 voltage-ranges = <1800 1800 3300 3300>; 932 sdhci,auto-cmd12; 933 little-endian; 934 bus-width = <4>; 935 status = "disabled"; 936 }; 937 938 esdhc1: mmc@2150000 { 939 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 940 reg = <0x0 0x2150000 0x0 0x10000>; 941 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 942 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 943 QORIQ_CLK_PLL_DIV(2)>; 944 dma-coherent; 945 voltage-ranges = <1800 1800 3300 3300>; 946 sdhci,auto-cmd12; 947 broken-cd; 948 little-endian; 949 bus-width = <4>; 950 status = "disabled"; 951 }; 952 953 can0: can@2180000 { 954 compatible = "fsl,lx2160ar1-flexcan"; 955 reg = <0x0 0x2180000 0x0 0x10000>; 956 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 958 QORIQ_CLK_PLL_DIV(8)>, 959 <&clockgen QORIQ_CLK_SYSCLK 0>; 960 clock-names = "ipg", "per"; 961 fsl,clk-source = /bits/ 8 <0>; 962 status = "disabled"; 963 }; 964 965 can1: can@2190000 { 966 compatible = "fsl,lx2160ar1-flexcan"; 967 reg = <0x0 0x2190000 0x0 0x10000>; 968 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 970 QORIQ_CLK_PLL_DIV(8)>, 971 <&clockgen QORIQ_CLK_SYSCLK 0>; 972 clock-names = "ipg", "per"; 973 fsl,clk-source = /bits/ 8 <0>; 974 status = "disabled"; 975 }; 976 977 uart0: serial@21c0000 { 978 compatible = "arm,pl011", "arm,primecell"; 979 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 980 QORIQ_CLK_PLL_DIV(8)>, 981 <&clockgen QORIQ_CLK_PLATFORM_PLL 982 QORIQ_CLK_PLL_DIV(8)>; 983 clock-names = "uartclk", "apb_pclk"; 984 reg = <0x0 0x21c0000 0x0 0x1000>; 985 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 986 status = "disabled"; 987 }; 988 989 uart1: serial@21d0000 { 990 compatible = "arm,pl011", "arm,primecell"; 991 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 992 QORIQ_CLK_PLL_DIV(8)>, 993 <&clockgen QORIQ_CLK_PLATFORM_PLL 994 QORIQ_CLK_PLL_DIV(8)>; 995 clock-names = "uartclk", "apb_pclk"; 996 reg = <0x0 0x21d0000 0x0 0x1000>; 997 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 998 status = "disabled"; 999 }; 1000 1001 uart2: serial@21e0000 { 1002 compatible = "arm,pl011", "arm,primecell"; 1003 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1004 QORIQ_CLK_PLL_DIV(8)>, 1005 <&clockgen QORIQ_CLK_PLATFORM_PLL 1006 QORIQ_CLK_PLL_DIV(8)>; 1007 clock-names = "uartclk", "apb_pclk"; 1008 reg = <0x0 0x21e0000 0x0 0x1000>; 1009 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1010 status = "disabled"; 1011 }; 1012 1013 uart3: serial@21f0000 { 1014 compatible = "arm,pl011", "arm,primecell"; 1015 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1016 QORIQ_CLK_PLL_DIV(8)>, 1017 <&clockgen QORIQ_CLK_PLATFORM_PLL 1018 QORIQ_CLK_PLL_DIV(8)>; 1019 clock-names = "uartclk", "apb_pclk"; 1020 reg = <0x0 0x21f0000 0x0 0x1000>; 1021 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1022 status = "disabled"; 1023 }; 1024 1025 gpio0: gpio@2300000 { 1026 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1027 reg = <0x0 0x2300000 0x0 0x10000>; 1028 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1029 gpio-controller; 1030 little-endian; 1031 #gpio-cells = <2>; 1032 interrupt-controller; 1033 #interrupt-cells = <2>; 1034 }; 1035 1036 gpio1: gpio@2310000 { 1037 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1038 reg = <0x0 0x2310000 0x0 0x10000>; 1039 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1040 gpio-controller; 1041 little-endian; 1042 #gpio-cells = <2>; 1043 interrupt-controller; 1044 #interrupt-cells = <2>; 1045 }; 1046 1047 gpio2: gpio@2320000 { 1048 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1049 reg = <0x0 0x2320000 0x0 0x10000>; 1050 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1051 gpio-controller; 1052 little-endian; 1053 #gpio-cells = <2>; 1054 interrupt-controller; 1055 #interrupt-cells = <2>; 1056 }; 1057 1058 gpio3: gpio@2330000 { 1059 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1060 reg = <0x0 0x2330000 0x0 0x10000>; 1061 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1062 gpio-controller; 1063 little-endian; 1064 #gpio-cells = <2>; 1065 interrupt-controller; 1066 #interrupt-cells = <2>; 1067 }; 1068 1069 watchdog@23a0000 { 1070 compatible = "arm,sbsa-gwdt"; 1071 reg = <0x0 0x23a0000 0 0x1000>, 1072 <0x0 0x2390000 0 0x1000>; 1073 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1074 timeout-sec = <30>; 1075 }; 1076 1077 rcpm: wakeup-controller@1e34040 { 1078 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1079 reg = <0x0 0x1e34040 0x0 0x1c>; 1080 #fsl,rcpm-wakeup-cells = <7>; 1081 little-endian; 1082 }; 1083 1084 ftm_alarm0: rtc@2800000 { 1085 compatible = "fsl,lx2160a-ftm-alarm"; 1086 reg = <0x0 0x2800000 0x0 0x10000>; 1087 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1088 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1089 }; 1090 1091 usb0: usb@3100000 { 1092 compatible = "fsl,lx2160a-dwc3", "fsl,ls1028a-dwc3"; 1093 reg = <0x0 0x3100000 0x0 0x10000>; 1094 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1095 dr_mode = "host"; 1096 snps,quirk-frame-length-adjustment = <0x20>; 1097 usb3-lpm-capable; 1098 iommus = <&smmu 1>; 1099 dma-coherent; 1100 snps,dis_rxdet_inp3_quirk; 1101 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1102 status = "disabled"; 1103 }; 1104 1105 usb1: usb@3110000 { 1106 compatible = "fsl,lx2160a-dwc3", "fsl,ls1028a-dwc3"; 1107 reg = <0x0 0x3110000 0x0 0x10000>; 1108 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1109 dr_mode = "host"; 1110 snps,quirk-frame-length-adjustment = <0x20>; 1111 usb3-lpm-capable; 1112 iommus = <&smmu 2>; 1113 dma-coherent; 1114 snps,dis_rxdet_inp3_quirk; 1115 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1116 status = "disabled"; 1117 }; 1118 1119 sata0: sata@3200000 { 1120 compatible = "fsl,lx2160a-ahci"; 1121 reg = <0x0 0x3200000 0x0 0x10000>, 1122 <0x7 0x100520 0x0 0x4>; 1123 reg-names = "ahci", "sata-ecc"; 1124 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1126 QORIQ_CLK_PLL_DIV(4)>; 1127 dma-coherent; 1128 status = "disabled"; 1129 }; 1130 1131 sata1: sata@3210000 { 1132 compatible = "fsl,lx2160a-ahci"; 1133 reg = <0x0 0x3210000 0x0 0x10000>, 1134 <0x7 0x100520 0x0 0x4>; 1135 reg-names = "ahci", "sata-ecc"; 1136 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1138 QORIQ_CLK_PLL_DIV(4)>; 1139 dma-coherent; 1140 status = "disabled"; 1141 }; 1142 1143 sata2: sata@3220000 { 1144 compatible = "fsl,lx2160a-ahci"; 1145 reg = <0x0 0x3220000 0x0 0x10000>, 1146 <0x7 0x100520 0x0 0x4>; 1147 reg-names = "ahci", "sata-ecc"; 1148 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1150 QORIQ_CLK_PLL_DIV(4)>; 1151 dma-coherent; 1152 status = "disabled"; 1153 }; 1154 1155 sata3: sata@3230000 { 1156 compatible = "fsl,lx2160a-ahci"; 1157 reg = <0x0 0x3230000 0x0 0x10000>, 1158 <0x7 0x100520 0x0 0x4>; 1159 reg-names = "ahci", "sata-ecc"; 1160 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1162 QORIQ_CLK_PLL_DIV(4)>; 1163 dma-coherent; 1164 status = "disabled"; 1165 }; 1166 1167 smmu: iommu@5000000 { 1168 compatible = "arm,mmu-500"; 1169 reg = <0 0x5000000 0 0x800000>; 1170 #iommu-cells = <1>; 1171 #global-interrupts = <14>; 1172 // global secure fault 1173 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1174 // combined secure 1175 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1176 // global non-secure fault 1177 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1178 // combined non-secure 1179 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1180 // performance counter interrupts 0-9 1181 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1191 // per context interrupt, 64 interrupts 1192 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1256 dma-coherent; 1257 }; 1258 1259 console@8340020 { 1260 compatible = "fsl,dpaa2-console"; 1261 reg = <0x00000000 0x08340020 0 0x2>; 1262 }; 1263 1264 ptp-timer@8b95000 { 1265 compatible = "fsl,dpaa2-ptp"; 1266 reg = <0x0 0x8b95000 0x0 0x100>; 1267 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1268 QORIQ_CLK_PLL_DIV(2)>; 1269 little-endian; 1270 fsl,extts-fifo; 1271 }; 1272 1273 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ 1274 emdio1: mdio@8b96000 { 1275 compatible = "fsl,fman-memac-mdio"; 1276 reg = <0x0 0x8b96000 0x0 0x1000>; 1277 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 little-endian; 1281 clock-frequency = <2500000>; 1282 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1283 QORIQ_CLK_PLL_DIV(2)>; 1284 status = "disabled"; 1285 }; 1286 1287 emdio2: mdio@8b97000 { 1288 compatible = "fsl,fman-memac-mdio"; 1289 reg = <0x0 0x8b97000 0x0 0x1000>; 1290 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1291 little-endian; 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 clock-frequency = <2500000>; 1295 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1296 QORIQ_CLK_PLL_DIV(2)>; 1297 status = "disabled"; 1298 }; 1299 1300 pcs_mdio1: mdio@8c07000 { 1301 compatible = "fsl,fman-memac-mdio"; 1302 reg = <0x0 0x8c07000 0x0 0x1000>; 1303 little-endian; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 status = "disabled"; 1307 1308 pcs1: ethernet-phy@0 { 1309 reg = <0>; 1310 }; 1311 }; 1312 1313 pcs_mdio2: mdio@8c0b000 { 1314 compatible = "fsl,fman-memac-mdio"; 1315 reg = <0x0 0x8c0b000 0x0 0x1000>; 1316 little-endian; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 status = "disabled"; 1320 1321 pcs2: ethernet-phy@0 { 1322 reg = <0>; 1323 }; 1324 }; 1325 1326 pcs_mdio3: mdio@8c0f000 { 1327 compatible = "fsl,fman-memac-mdio"; 1328 reg = <0x0 0x8c0f000 0x0 0x1000>; 1329 little-endian; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 status = "disabled"; 1333 1334 pcs3: ethernet-phy@0 { 1335 reg = <0>; 1336 }; 1337 }; 1338 1339 pcs_mdio4: mdio@8c13000 { 1340 compatible = "fsl,fman-memac-mdio"; 1341 reg = <0x0 0x8c13000 0x0 0x1000>; 1342 little-endian; 1343 #address-cells = <1>; 1344 #size-cells = <0>; 1345 status = "disabled"; 1346 1347 pcs4: ethernet-phy@0 { 1348 reg = <0>; 1349 }; 1350 }; 1351 1352 pcs_mdio5: mdio@8c17000 { 1353 compatible = "fsl,fman-memac-mdio"; 1354 reg = <0x0 0x8c17000 0x0 0x1000>; 1355 little-endian; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 status = "disabled"; 1359 1360 pcs5: ethernet-phy@0 { 1361 reg = <0>; 1362 }; 1363 }; 1364 1365 pcs_mdio6: mdio@8c1b000 { 1366 compatible = "fsl,fman-memac-mdio"; 1367 reg = <0x0 0x8c1b000 0x0 0x1000>; 1368 little-endian; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 status = "disabled"; 1372 1373 pcs6: ethernet-phy@0 { 1374 reg = <0>; 1375 }; 1376 }; 1377 1378 pcs_mdio7: mdio@8c1f000 { 1379 compatible = "fsl,fman-memac-mdio"; 1380 reg = <0x0 0x8c1f000 0x0 0x1000>; 1381 little-endian; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 status = "disabled"; 1385 1386 pcs7: ethernet-phy@0 { 1387 reg = <0>; 1388 }; 1389 }; 1390 1391 pcs_mdio8: mdio@8c23000 { 1392 compatible = "fsl,fman-memac-mdio"; 1393 reg = <0x0 0x8c23000 0x0 0x1000>; 1394 little-endian; 1395 #address-cells = <1>; 1396 #size-cells = <0>; 1397 status = "disabled"; 1398 1399 pcs8: ethernet-phy@0 { 1400 reg = <0>; 1401 }; 1402 }; 1403 1404 pcs_mdio9: mdio@8c27000 { 1405 compatible = "fsl,fman-memac-mdio"; 1406 reg = <0x0 0x8c27000 0x0 0x1000>; 1407 little-endian; 1408 #address-cells = <1>; 1409 #size-cells = <0>; 1410 status = "disabled"; 1411 1412 pcs9: ethernet-phy@0 { 1413 reg = <0>; 1414 }; 1415 }; 1416 1417 pcs_mdio10: mdio@8c2b000 { 1418 compatible = "fsl,fman-memac-mdio"; 1419 reg = <0x0 0x8c2b000 0x0 0x1000>; 1420 little-endian; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 status = "disabled"; 1424 1425 pcs10: ethernet-phy@0 { 1426 reg = <0>; 1427 }; 1428 }; 1429 1430 pcs_mdio11: mdio@8c2f000 { 1431 compatible = "fsl,fman-memac-mdio"; 1432 reg = <0x0 0x8c2f000 0x0 0x1000>; 1433 little-endian; 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 status = "disabled"; 1437 1438 pcs11: ethernet-phy@0 { 1439 reg = <0>; 1440 }; 1441 }; 1442 1443 pcs_mdio12: mdio@8c33000 { 1444 compatible = "fsl,fman-memac-mdio"; 1445 reg = <0x0 0x8c33000 0x0 0x1000>; 1446 little-endian; 1447 #address-cells = <1>; 1448 #size-cells = <0>; 1449 status = "disabled"; 1450 1451 pcs12: ethernet-phy@0 { 1452 reg = <0>; 1453 }; 1454 }; 1455 1456 pcs_mdio13: mdio@8c37000 { 1457 compatible = "fsl,fman-memac-mdio"; 1458 reg = <0x0 0x8c37000 0x0 0x1000>; 1459 little-endian; 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 status = "disabled"; 1463 1464 pcs13: ethernet-phy@0 { 1465 reg = <0>; 1466 }; 1467 }; 1468 1469 pcs_mdio14: mdio@8c3b000 { 1470 compatible = "fsl,fman-memac-mdio"; 1471 reg = <0x0 0x8c3b000 0x0 0x1000>; 1472 little-endian; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 status = "disabled"; 1476 1477 pcs14: ethernet-phy@0 { 1478 reg = <0>; 1479 }; 1480 }; 1481 1482 pcs_mdio15: mdio@8c3f000 { 1483 compatible = "fsl,fman-memac-mdio"; 1484 reg = <0x0 0x8c3f000 0x0 0x1000>; 1485 little-endian; 1486 #address-cells = <1>; 1487 #size-cells = <0>; 1488 status = "disabled"; 1489 1490 pcs15: ethernet-phy@0 { 1491 reg = <0>; 1492 }; 1493 }; 1494 1495 pcs_mdio16: mdio@8c43000 { 1496 compatible = "fsl,fman-memac-mdio"; 1497 reg = <0x0 0x8c43000 0x0 0x1000>; 1498 little-endian; 1499 #address-cells = <1>; 1500 #size-cells = <0>; 1501 status = "disabled"; 1502 1503 pcs16: ethernet-phy@0 { 1504 reg = <0>; 1505 }; 1506 }; 1507 1508 pcs_mdio17: mdio@8c47000 { 1509 compatible = "fsl,fman-memac-mdio"; 1510 reg = <0x0 0x8c47000 0x0 0x1000>; 1511 little-endian; 1512 #address-cells = <1>; 1513 #size-cells = <0>; 1514 status = "disabled"; 1515 1516 pcs17: ethernet-phy@0 { 1517 reg = <0>; 1518 }; 1519 }; 1520 1521 pcs_mdio18: mdio@8c4b000 { 1522 compatible = "fsl,fman-memac-mdio"; 1523 reg = <0x0 0x8c4b000 0x0 0x1000>; 1524 little-endian; 1525 #address-cells = <1>; 1526 #size-cells = <0>; 1527 status = "disabled"; 1528 1529 pcs18: ethernet-phy@0 { 1530 reg = <0>; 1531 }; 1532 }; 1533 1534 pinmux_i2crv: pinmux@70010012c { 1535 compatible = "pinctrl-single"; 1536 reg = <0x00000007 0x0010012c 0x0 0xc>; 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 pinctrl-single,bit-per-mux; 1540 pinctrl-single,register-width = <32>; 1541 pinctrl-single,function-mask = <0x7>; 1542 1543 /* RCWSR12 */ 1544 i2c1_pins: iic2-i2c-pins { 1545 pinctrl-single,bits = <0x0 0x0 0x7>; 1546 }; 1547 1548 gpio0_31_30_pins: iic2-gpio-pins { 1549 pinctrl-single,bits = <0x0 0x1 0x7>; 1550 }; 1551 1552 ftm0_ch10_pins: iic2-ftm-pins { 1553 pinctrl-single,bits = <0x0 0x2 0x7>; 1554 }; 1555 1556 esdhc0_cd_wp_pins: iic2-sdhc-pins { 1557 pinctrl-single,bits = <0x0 0x6 0x7>; 1558 }; 1559 1560 i2c2_pins: iic3-i2c-pins { 1561 pinctrl-single,bits = <0x0 0x0 (0x7 << 3)>; 1562 }; 1563 1564 gpio0_29_28_pins: iic3-gpio-pins { 1565 pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>; 1566 }; 1567 1568 can0_pins: iic3-can-pins { 1569 pinctrl-single,bits = <0x0 (0x2 << 3) (0x7 << 3)>; 1570 }; 1571 1572 event65_pins: iic3-event-pins { 1573 pinctrl-single,bits = <0x0 (0x6 << 3) (0x7 << 3)>; 1574 }; 1575 1576 i2c3_pins: iic4-i2c-pins { 1577 pinctrl-single,bits = <0x0 0x0 (0x7 << 6)>; 1578 }; 1579 1580 gpio0_27_26_pins: iic4-gpio-pins { 1581 pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>; 1582 }; 1583 1584 can1_pins: iic4-can-pins { 1585 pinctrl-single,bits = <0x0 (0x2 << 6) (0x7 << 6)>; 1586 }; 1587 1588 event87_pins: iic4-event-pins { 1589 pinctrl-single,bits = <0x0 (0x6 << 6) (0x7 << 6)>; 1590 }; 1591 1592 i2c4_pins: iic5-i2c-pins { 1593 pinctrl-single,bits = <0x0 0x0 (0x7 << 9)>; 1594 }; 1595 1596 gpio0_25_24_pins: iic5-gpio-pins { 1597 pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>; 1598 }; 1599 1600 esdhc0_clksync_pins: iic5-sdhc-clk-pins { 1601 pinctrl-single,bits = <0x0 (0x2 << 9) (0x7 << 9)>; 1602 }; 1603 1604 dspi2_miso_mosi_pins: iic5-spi3-pins { 1605 pinctrl-single,bits = <0x3 (0x2 << 9) (0x7 << 9)>; 1606 }; 1607 1608 i2c5_pins: iic6-i2c-pins { 1609 pinctrl-single,bits = <0x0 0x0 (0x7 << 12)>; 1610 }; 1611 1612 gpio0_23_22_pins: iic6-gpio-pins { 1613 pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>; 1614 }; 1615 1616 esdhc1_clksync_pins: iic6-sdhc-clk-pins { 1617 pinctrl-single,bits = <0x0 (0x2 << 12) (0x7 << 12)>; 1618 }; 1619 1620 fspi_data74_pins: xspi1-data74-pins { 1621 pinctrl-single,bits = <0x0 0x0 (0x7 << 15)>; 1622 }; 1623 1624 gpio1_31_28_pins: xspi1-data74-gpio-pins { 1625 pinctrl-single,bits = <0x0 0x1 (0x7 << 15)>; 1626 }; 1627 1628 fspi_data30_pins: xspi1-data30-pins { 1629 pinctrl-single,bits = <0x0 0x0 (0x7 << 18)>; 1630 }; 1631 1632 gpio1_27_24_pins: xspi1-data30-gpio-pins { 1633 pinctrl-single,bits = <0x0 0x1 (0x7 << 18)>; 1634 }; 1635 1636 fspi_dqs_sck_cs10_pins: xspi1-base-pins { 1637 pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>; 1638 }; 1639 1640 gpio1_23_20_pins: xspi1-base-gpio-pins { 1641 pinctrl-single,bits = <0x0 0x1 (0x7 << 21)>; 1642 }; 1643 1644 esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins { 1645 pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>; 1646 }; 1647 1648 gpio0_21_15_pins: sdhc1-base-gpio-pins { 1649 pinctrl-single,bits = <0x0 (0x1 << 24) (0x7 << 24)>; 1650 }; 1651 1652 dspi0_pins: sdhc1-base-spi1-pins { 1653 pinctrl-single,bits = <0x0 (0x2 << 24) (0x7 << 24)>; 1654 }; 1655 1656 esdhc0_cmd_data30_clk_dspi2_cs0_pins: sdhc1-base-sdhc-spi3-pins { 1657 pinctrl-single,bits = <0x0 (0x3 << 24) (0x7 << 24)>; 1658 }; 1659 1660 esdhc0_cmd_data30_clk_data4_pins: sdhc1-base-sdhc-data4-pins { 1661 pinctrl-single,bits = <0x0 (0x4 << 24) (0x7 << 24)>; 1662 }; 1663 1664 esdhc0_dir_pins: sdhc1-dir-pins { 1665 pinctrl-single,bits = <0x0 0x0 (0x7 << 27)>; 1666 }; 1667 1668 gpio0_14_12_pins: sdhc1-dir-gpio-pins { 1669 pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>; 1670 }; 1671 1672 dspi2_cs31_pins: sdhc1-dir-spi3-pins { 1673 pinctrl-single,bits = <0x0 (0x3 << 27) (0x7 << 27)>; 1674 }; 1675 1676 esdhc0_data75_pins: sdhc1-dir-sdhc-pins { 1677 pinctrl-single,bits = <0x0 (0x4 << 27) (0x7 << 27)>; 1678 }; 1679 1680 /* RCWSR13 */ 1681 gpio1_18_15_pins: iic8-iic7-gpio-pins { 1682 pinctrl-single,bits = <0x4 0x1 0x7>; 1683 }; 1684 1685 i2c6_i2c7_pins: iic8-iic7-i2c-pins { 1686 pinctrl-single,bits = <0x4 0x2 0x7>; 1687 }; 1688 1689 /* RCWSR14 */ 1690 i2c0_pins: iic1-i2c-pins { 1691 pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>; 1692 }; 1693 1694 gpio0_3_2_pins: iic1-gpio-pins { 1695 pinctrl-single,bits = <0x8 (0x1 << 10) (0x1 << 10)>; 1696 }; 1697 }; 1698 1699 fsl_mc: fsl-mc@80c000000 { 1700 compatible = "fsl,qoriq-mc"; 1701 reg = <0x00000008 0x0c000000 0 0x40>, 1702 <0x00000000 0x08340000 0 0x40000>; 1703 msi-parent = <&its 0>; 1704 /* iommu-map property is fixed up by u-boot */ 1705 iommu-map = <0 &smmu 0 0>; 1706 dma-coherent; 1707 #address-cells = <3>; 1708 #size-cells = <1>; 1709 1710 /* 1711 * Region type 0x0 - MC portals 1712 * Region type 0x1 - QBMAN portals 1713 */ 1714 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 1715 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 1716 1717 /* 1718 * Define the maximum number of MACs present on the SoC. 1719 */ 1720 dpmacs { 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 1724 dpmac1: ethernet@1 { 1725 compatible = "fsl,qoriq-mc-dpmac"; 1726 reg = <0x1>; 1727 pcs-handle = <&pcs1>; 1728 }; 1729 1730 dpmac2: ethernet@2 { 1731 compatible = "fsl,qoriq-mc-dpmac"; 1732 reg = <0x2>; 1733 pcs-handle = <&pcs2>; 1734 }; 1735 1736 dpmac3: ethernet@3 { 1737 compatible = "fsl,qoriq-mc-dpmac"; 1738 reg = <0x3>; 1739 pcs-handle = <&pcs3>; 1740 }; 1741 1742 dpmac4: ethernet@4 { 1743 compatible = "fsl,qoriq-mc-dpmac"; 1744 reg = <0x4>; 1745 pcs-handle = <&pcs4>; 1746 }; 1747 1748 dpmac5: ethernet@5 { 1749 compatible = "fsl,qoriq-mc-dpmac"; 1750 reg = <0x5>; 1751 pcs-handle = <&pcs5>; 1752 }; 1753 1754 dpmac6: ethernet@6 { 1755 compatible = "fsl,qoriq-mc-dpmac"; 1756 reg = <0x6>; 1757 pcs-handle = <&pcs6>; 1758 }; 1759 1760 dpmac7: ethernet@7 { 1761 compatible = "fsl,qoriq-mc-dpmac"; 1762 reg = <0x7>; 1763 pcs-handle = <&pcs7>; 1764 }; 1765 1766 dpmac8: ethernet@8 { 1767 compatible = "fsl,qoriq-mc-dpmac"; 1768 reg = <0x8>; 1769 pcs-handle = <&pcs8>; 1770 }; 1771 1772 dpmac9: ethernet@9 { 1773 compatible = "fsl,qoriq-mc-dpmac"; 1774 reg = <0x9>; 1775 pcs-handle = <&pcs9>; 1776 }; 1777 1778 dpmac10: ethernet@a { 1779 compatible = "fsl,qoriq-mc-dpmac"; 1780 reg = <0xa>; 1781 pcs-handle = <&pcs10>; 1782 }; 1783 1784 dpmac11: ethernet@b { 1785 compatible = "fsl,qoriq-mc-dpmac"; 1786 reg = <0xb>; 1787 pcs-handle = <&pcs11>; 1788 }; 1789 1790 dpmac12: ethernet@c { 1791 compatible = "fsl,qoriq-mc-dpmac"; 1792 reg = <0xc>; 1793 pcs-handle = <&pcs12>; 1794 }; 1795 1796 dpmac13: ethernet@d { 1797 compatible = "fsl,qoriq-mc-dpmac"; 1798 reg = <0xd>; 1799 pcs-handle = <&pcs13>; 1800 }; 1801 1802 dpmac14: ethernet@e { 1803 compatible = "fsl,qoriq-mc-dpmac"; 1804 reg = <0xe>; 1805 pcs-handle = <&pcs14>; 1806 }; 1807 1808 dpmac15: ethernet@f { 1809 compatible = "fsl,qoriq-mc-dpmac"; 1810 reg = <0xf>; 1811 pcs-handle = <&pcs15>; 1812 }; 1813 1814 dpmac16: ethernet@10 { 1815 compatible = "fsl,qoriq-mc-dpmac"; 1816 reg = <0x10>; 1817 pcs-handle = <&pcs16>; 1818 }; 1819 1820 dpmac17: ethernet@11 { 1821 compatible = "fsl,qoriq-mc-dpmac"; 1822 reg = <0x11>; 1823 pcs-handle = <&pcs17>; 1824 }; 1825 1826 dpmac18: ethernet@12 { 1827 compatible = "fsl,qoriq-mc-dpmac"; 1828 reg = <0x12>; 1829 pcs-handle = <&pcs18>; 1830 }; 1831 }; 1832 }; 1833 }; 1834 1835 firmware { 1836 optee: optee { 1837 compatible = "linaro,optee-tz"; 1838 method = "smc"; 1839 status = "disabled"; 1840 }; 1841 }; 1842}; 1843