1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree file describing the Lynx 28G SerDes blocks found on the LX2162A 4// SoC 5// 6// Copyright 2026 NXP 7 8&soc { 9 serdes_1: phy@1ea0000 { 10 compatible = "fsl,lx2162a-serdes1", "fsl,lynx-28g"; 11 reg = <0x0 0x1ea0000 0x0 0x1e30>; 12 #address-cells = <1>; 13 #size-cells = <0>; 14 #phy-cells = <1>; 15 status = "disabled"; 16 17 serdes_1_lane_e: phy@4 { 18 reg = <4>; 19 #phy-cells = <0>; 20 }; 21 22 serdes_1_lane_f: phy@5 { 23 reg = <5>; 24 #phy-cells = <0>; 25 }; 26 27 serdes_1_lane_g: phy@6 { 28 reg = <6>; 29 #phy-cells = <0>; 30 }; 31 32 serdes_1_lane_h: phy@7 { 33 reg = <7>; 34 #phy-cells = <0>; 35 }; 36 }; 37 38 serdes_2: phy@1eb0000 { 39 compatible = "fsl,lx2162a-serdes2", "fsl,lynx-28g"; 40 reg = <0x0 0x1eb0000 0x0 0x1e30>; 41 #address-cells = <1>; 42 #size-cells = <0>; 43 #phy-cells = <1>; 44 status = "disabled"; 45 46 serdes_2_lane_a: phy@0 { 47 reg = <0>; 48 #phy-cells = <0>; 49 }; 50 51 serdes_2_lane_b: phy@1 { 52 reg = <1>; 53 #phy-cells = <0>; 54 }; 55 56 serdes_2_lane_c: phy@2 { 57 reg = <2>; 58 #phy-cells = <0>; 59 }; 60 61 serdes_2_lane_d: phy@3 { 62 reg = <3>; 63 #phy-cells = <0>; 64 }; 65 66 serdes_2_lane_e: phy@4 { 67 reg = <4>; 68 #phy-cells = <0>; 69 }; 70 71 serdes_2_lane_f: phy@5 { 72 reg = <5>; 73 #phy-cells = <0>; 74 }; 75 76 serdes_2_lane_g: phy@6 { 77 reg = <6>; 78 #phy-cells = <0>; 79 }; 80 81 serdes_2_lane_h: phy@7 { 82 reg = <7>; 83 #phy-cells = <0>; 84 }; 85 }; 86}; 87