1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree file describing the Lynx 28G SerDes blocks found on the LX2160A 4// Rev1 and Rev2 5// 6// Copyright 2026 NXP 7 8&soc { 9 /* Note on the interpretation of SerDes lane numbering from 10 * LX2160ARM lane mappings for RCW[SRDS_PRTCL_S1]: 11 * The letters (A-H) correspond to logical lane numbers in the 12 * SerDes register map (lane A's registers start with LNAGCR0), 13 * while the numbers (0-7) correspond to physical lanes as 14 * routed to pins. SerDes block #1 is flipped in the LX2160A 15 * floorplan (logical lane A goes to physical lane 7's pins), 16 * while SerDes blocks #2 and #3 are not. The lanes below are 17 * listed right to left when looking at that table. 18 * Both the numbers and the letters are according to the logical 19 * numbering scheme, and do not account for the flipping. 20 */ 21 serdes_1: phy@1ea0000 { 22 compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g"; 23 reg = <0x0 0x1ea0000 0x0 0x1e30>; 24 #address-cells = <1>; 25 #size-cells = <0>; 26 #phy-cells = <1>; 27 status = "disabled"; 28 29 serdes_1_lane_a: phy@0 { 30 reg = <0>; 31 #phy-cells = <0>; 32 }; 33 34 serdes_1_lane_b: phy@1 { 35 reg = <1>; 36 #phy-cells = <0>; 37 }; 38 39 serdes_1_lane_c: phy@2 { 40 reg = <2>; 41 #phy-cells = <0>; 42 }; 43 44 serdes_1_lane_d: phy@3 { 45 reg = <3>; 46 #phy-cells = <0>; 47 }; 48 49 serdes_1_lane_e: phy@4 { 50 reg = <4>; 51 #phy-cells = <0>; 52 }; 53 54 serdes_1_lane_f: phy@5 { 55 reg = <5>; 56 #phy-cells = <0>; 57 }; 58 59 serdes_1_lane_g: phy@6 { 60 reg = <6>; 61 #phy-cells = <0>; 62 }; 63 64 serdes_1_lane_h: phy@7 { 65 reg = <7>; 66 #phy-cells = <0>; 67 }; 68 }; 69 70 serdes_2: phy@1eb0000 { 71 compatible = "fsl,lx2160a-serdes2", "fsl,lynx-28g"; 72 reg = <0x0 0x1eb0000 0x0 0x1e30>; 73 #address-cells = <1>; 74 #size-cells = <0>; 75 #phy-cells = <1>; 76 status = "disabled"; 77 78 serdes_2_lane_a: phy@0 { 79 reg = <0>; 80 #phy-cells = <0>; 81 }; 82 83 serdes_2_lane_b: phy@1 { 84 reg = <1>; 85 #phy-cells = <0>; 86 }; 87 88 serdes_2_lane_c: phy@2 { 89 reg = <2>; 90 #phy-cells = <0>; 91 }; 92 93 serdes_2_lane_d: phy@3 { 94 reg = <3>; 95 #phy-cells = <0>; 96 }; 97 98 serdes_2_lane_e: phy@4 { 99 reg = <4>; 100 #phy-cells = <0>; 101 }; 102 103 serdes_2_lane_f: phy@5 { 104 reg = <5>; 105 #phy-cells = <0>; 106 }; 107 108 serdes_2_lane_g: phy@6 { 109 reg = <6>; 110 #phy-cells = <0>; 111 }; 112 113 serdes_2_lane_h: phy@7 { 114 reg = <7>; 115 #phy-cells = <0>; 116 }; 117 }; 118 119 serdes_3: phy@1ec0000 { 120 compatible = "fsl,lx2160a-serdes3"; 121 reg = <0x0 0x1ec0000 0x0 0x1e30>; 122 #address-cells = <1>; 123 #size-cells = <0>; 124 #phy-cells = <1>; 125 status = "disabled"; 126 127 serdes_3_lane_a: phy@0 { 128 reg = <0>; 129 #phy-cells = <0>; 130 }; 131 132 serdes_3_lane_b: phy@1 { 133 reg = <1>; 134 #phy-cells = <0>; 135 }; 136 137 serdes_3_lane_c: phy@2 { 138 reg = <2>; 139 #phy-cells = <0>; 140 }; 141 142 serdes_3_lane_d: phy@3 { 143 reg = <3>; 144 #phy-cells = <0>; 145 }; 146 147 serdes_3_lane_e: phy@4 { 148 reg = <4>; 149 #phy-cells = <0>; 150 }; 151 152 serdes_3_lane_f: phy@5 { 153 reg = <5>; 154 #phy-cells = <0>; 155 }; 156 157 serdes_3_lane_g: phy@6 { 158 reg = <6>; 159 #phy-cells = <0>; 160 }; 161 162 serdes_3_lane_h: phy@7 { 163 reg = <7>; 164 #phy-cells = <0>; 165 }; 166 }; 167}; 168