xref: /linux/arch/arm64/boot/dts/exynos/exynosautov920.dtsi (revision 55d0969c451159cff86949b38c39171cab962069) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's ExynosAutov920 SoC device tree source
4 *
5 * Copyright (c) 2023 Samsung Electronics Co., Ltd.
6 *
7 */
8
9#include <dt-bindings/clock/samsung,exynosautov920.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/soc/samsung,exynos-usi.h>
12
13/ {
14	compatible = "samsung,exynosautov920";
15	#address-cells = <2>;
16	#size-cells = <1>;
17
18	interrupt-parent = <&gic>;
19
20	aliases {
21		pinctrl0 = &pinctrl_alive;
22		pinctrl1 = &pinctrl_aud;
23		pinctrl2 = &pinctrl_hsi0;
24		pinctrl3 = &pinctrl_hsi1;
25		pinctrl4 = &pinctrl_hsi2;
26		pinctrl5 = &pinctrl_hsi2ufs;
27		pinctrl6 = &pinctrl_peric0;
28		pinctrl7 = &pinctrl_peric1;
29	};
30
31	arm-pmu {
32		compatible = "arm,cortex-a78-pmu";
33		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
34	};
35
36	xtcxo: clock {
37		compatible = "fixed-clock";
38		#clock-cells = <0>;
39		clock-output-names = "oscclk";
40	};
41
42	cpus: cpus {
43		#address-cells = <2>;
44		#size-cells = <0>;
45
46		cpu-map {
47			cluster0 {
48				core0 {
49					cpu = <&cpu0>;
50				};
51				core1 {
52					cpu = <&cpu1>;
53				};
54				core2 {
55					cpu = <&cpu2>;
56				};
57				core3 {
58					cpu = <&cpu3>;
59				};
60			};
61
62			cluster1 {
63				core0 {
64					cpu = <&cpu4>;
65				};
66				core1 {
67					cpu = <&cpu5>;
68				};
69				core2 {
70					cpu = <&cpu6>;
71				};
72				core3 {
73					cpu = <&cpu7>;
74				};
75			};
76
77			cluster2 {
78				core0 {
79					cpu = <&cpu8>;
80				};
81				core1 {
82					cpu = <&cpu9>;
83				};
84			};
85		};
86
87		cpu0: cpu@0 {
88			device_type = "cpu";
89			compatible = "arm,cortex-a78ae";
90			reg = <0x0 0x0>;
91			enable-method = "psci";
92		};
93
94		cpu1: cpu@100 {
95			device_type = "cpu";
96			compatible = "arm,cortex-a78ae";
97			reg = <0x0 0x100>;
98			enable-method = "psci";
99		};
100
101		cpu2: cpu@200 {
102			device_type = "cpu";
103			compatible = "arm,cortex-a78ae";
104			reg = <0x0 0x200>;
105			enable-method = "psci";
106		};
107
108		cpu3: cpu@300 {
109			device_type = "cpu";
110			compatible = "arm,cortex-a78ae";
111			reg = <0x0 0x300>;
112			enable-method = "psci";
113		};
114
115		cpu4: cpu@10000 {
116			device_type = "cpu";
117			compatible = "arm,cortex-a78ae";
118			reg = <0x0 0x10000>;
119			enable-method = "psci";
120		};
121
122		cpu5: cpu@10100 {
123			device_type = "cpu";
124			compatible = "arm,cortex-a78ae";
125			reg = <0x0 0x10100>;
126			enable-method = "psci";
127		};
128
129		cpu6: cpu@10200 {
130			device_type = "cpu";
131			compatible = "arm,cortex-a78ae";
132			reg = <0x0 0x10200>;
133			enable-method = "psci";
134		};
135
136		cpu7: cpu@10300 {
137			device_type = "cpu";
138			compatible = "arm,cortex-a78ae";
139			reg = <0x0 0x10300>;
140			enable-method = "psci";
141		};
142
143		cpu8: cpu@20000 {
144			device_type = "cpu";
145			compatible = "arm,cortex-a78ae";
146			reg = <0x0 0x20000>;
147			enable-method = "psci";
148		};
149
150		cpu9: cpu@20100 {
151			device_type = "cpu";
152			compatible = "arm,cortex-a78ae";
153			reg = <0x0 0x20100>;
154			enable-method = "psci";
155		};
156	};
157
158	psci {
159		compatible = "arm,psci-1.0";
160		method = "smc";
161	};
162
163	soc: soc@0 {
164		compatible = "simple-bus";
165		#address-cells = <1>;
166		#size-cells = <1>;
167		ranges = <0x0 0x0 0x0 0x20000000>;
168
169		chipid@10000000 {
170			compatible = "samsung,exynosautov920-chipid",
171				     "samsung,exynos850-chipid";
172			reg = <0x10000000 0x24>;
173		};
174
175		cmu_misc: clock-controller@10020000 {
176			compatible = "samsung,exynosautov920-cmu-misc";
177			reg = <0x10020000 0x8000>;
178			#clock-cells = <1>;
179
180			clocks = <&xtcxo>,
181				 <&cmu_top DOUT_CLKCMU_MISC_NOC>;
182			clock-names = "oscclk",
183				      "noc";
184		};
185
186		gic: interrupt-controller@10400000 {
187			compatible = "arm,gic-v3";
188			#interrupt-cells = <3>;
189			#address-cells = <0>;
190			interrupt-controller;
191			reg = <0x10400000 0x10000>,
192			      <0x10460000 0x140000>;
193			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
194		};
195
196		cmu_peric0: clock-controller@10800000 {
197			compatible = "samsung,exynosautov920-cmu-peric0";
198			reg = <0x10800000 0x8000>;
199			#clock-cells = <1>;
200
201			clocks = <&xtcxo>,
202				 <&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
203				 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
204			clock-names = "oscclk",
205				      "noc",
206				      "ip";
207		};
208
209		syscon_peric0: syscon@10820000 {
210			compatible = "samsung,exynosautov920-peric0-sysreg",
211				     "syscon";
212			reg = <0x10820000 0x2000>;
213		};
214
215		pinctrl_peric0: pinctrl@10830000 {
216			compatible = "samsung,exynosautov920-pinctrl";
217			reg = <0x10830000 0x10000>;
218			interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>;
219		};
220
221		usi_0: usi@108800c0 {
222			compatible = "samsung,exynosautov920-usi",
223				     "samsung,exynos850-usi";
224			reg = <0x108800c0 0x20>;
225			samsung,sysreg = <&syscon_peric0 0x1000>;
226			samsung,mode = <USI_V2_UART>;
227			#address-cells = <1>;
228			#size-cells = <1>;
229			ranges;
230			clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
231				 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
232			clock-names = "pclk", "ipclk";
233			status = "disabled";
234
235			serial_0: serial@10880000 {
236				compatible = "samsung,exynosautov920-uart",
237					     "samsung,exynos850-uart";
238				reg = <0x10880000 0xc0>;
239				interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
240				pinctrl-names = "default";
241				pinctrl-0 = <&uart0_bus>;
242				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
243					 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
244				clock-names = "uart", "clk_uart_baud0";
245				samsung,uart-fifosize = <256>;
246				status = "disabled";
247			};
248		};
249
250		pwm: pwm@109b0000 {
251			compatible = "samsung,exynosautov920-pwm",
252				     "samsung,exynos4210-pwm";
253			reg = <0x109b0000 0x100>;
254			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
255			#pwm-cells = <3>;
256			clocks = <&xtcxo>;
257			clock-names = "timers";
258			status = "disabled";
259		};
260
261		cmu_peric1: clock-controller@10c00000 {
262			compatible = "samsung,exynosautov920-cmu-peric1";
263			reg = <0x10c00000 0x8000>;
264			#clock-cells = <1>;
265
266			clocks = <&xtcxo>,
267				 <&cmu_top DOUT_CLKCMU_PERIC1_NOC>,
268				 <&cmu_top DOUT_CLKCMU_PERIC1_IP>;
269			clock-names = "oscclk",
270				      "noc",
271				      "ip";
272		};
273
274		syscon_peric1: syscon@10c20000 {
275			compatible = "samsung,exynosautov920-peric1-sysreg",
276				     "syscon";
277			reg = <0x10c20000 0x2000>;
278		};
279
280		pinctrl_peric1: pinctrl@10c30000 {
281			compatible = "samsung,exynosautov920-pinctrl";
282			reg = <0x10c30000 0x10000>;
283			interrupts = <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
284		};
285
286		cmu_top: clock-controller@11000000 {
287			compatible = "samsung,exynosautov920-cmu-top";
288			reg = <0x11000000 0x8000>;
289			#clock-cells = <1>;
290
291			clocks = <&xtcxo>;
292			clock-names = "oscclk";
293		};
294
295		pinctrl_alive: pinctrl@11850000 {
296			compatible = "samsung,exynosautov920-pinctrl";
297			reg = <0x11850000 0x10000>;
298
299			wakeup-interrupt-controller {
300				compatible = "samsung,exynosautov920-wakeup-eint";
301			};
302		};
303
304		pmu_system_controller: system-controller@11860000 {
305			compatible = "samsung,exynosautov920-pmu",
306				     "samsung,exynos7-pmu","syscon";
307			reg = <0x11860000 0x10000>;
308		};
309
310		cmu_hsi0: clock-controller@16000000 {
311			compatible = "samsung,exynosautov920-cmu-hsi0";
312			reg = <0x16000000 0x8000>;
313			#clock-cells = <1>;
314
315			clocks = <&xtcxo>,
316				 <&cmu_top DOUT_CLKCMU_HSI0_NOC>;
317			clock-names = "oscclk",
318				      "noc";
319		};
320
321		pinctrl_hsi0: pinctrl@16040000 {
322			compatible = "samsung,exynosautov920-pinctrl";
323			reg = <0x16040000 0x10000>;
324			interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
325		};
326
327		cmu_hsi1: clock-controller@16400000 {
328			compatible = "samsung,exynosautov920-cmu-hsi1";
329			reg = <0x16400000 0x8000>;
330			#clock-cells = <1>;
331
332			clocks = <&xtcxo>,
333				 <&cmu_top DOUT_CLKCMU_HSI1_NOC>,
334				 <&cmu_top DOUT_CLKCMU_HSI1_USBDRD>,
335				 <&cmu_top DOUT_CLKCMU_HSI1_MMC_CARD>;
336			clock-names = "oscclk",
337				      "noc",
338				      "usbdrd",
339				      "mmc_card";
340		};
341
342		pinctrl_hsi1: pinctrl@16450000 {
343			compatible = "samsung,exynosautov920-pinctrl";
344			reg = <0x16450000 0x10000>;
345			interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
346		};
347
348		pinctrl_hsi2: pinctrl@16c10000 {
349			compatible = "samsung,exynosautov920-pinctrl";
350			reg = <0x16c10000 0x10000>;
351			interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
352		};
353
354		pinctrl_hsi2ufs: pinctrl@16d20000 {
355			compatible = "samsung,exynosautov920-pinctrl";
356			reg = <0x16d20000 0x10000>;
357			interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
358		};
359
360		pinctrl_aud: pinctrl@1a460000 {
361			compatible = "samsung,exynosautov920-pinctrl";
362			reg = <0x1a460000 0x10000>;
363		};
364	};
365
366	timer {
367		compatible = "arm,armv8-timer";
368		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
369			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
370			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
371			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
372			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
373	};
374};
375
376#include "exynosautov920-pinctrl.dtsi"
377