// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's ExynosAutov920 SoC device tree source
 *
 * Copyright (c) 2023 Samsung Electronics Co., Ltd.
 *
 */

#include <dt-bindings/clock/samsung,exynosautov920.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/samsung,exynos-usi.h>

/ {
	compatible = "samsung,exynosautov920";
	#address-cells = <2>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	aliases {
		pinctrl0 = &pinctrl_alive;
		pinctrl1 = &pinctrl_aud;
		pinctrl2 = &pinctrl_hsi0;
		pinctrl3 = &pinctrl_hsi1;
		pinctrl4 = &pinctrl_hsi2;
		pinctrl5 = &pinctrl_hsi2ufs;
		pinctrl6 = &pinctrl_peric0;
		pinctrl7 = &pinctrl_peric1;
	};

	arm-pmu {
		compatible = "arm,cortex-a78-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	xtcxo: clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-output-names = "oscclk";
	};

	cpus: cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};

			cluster2 {
				core0 {
					cpu = <&cpu8>;
				};
				core1 {
					cpu = <&cpu9>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a78ae";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a78ae";
			reg = <0x0 0x100>;
			enable-method = "psci";
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a78ae";
			reg = <0x0 0x200>;
			enable-method = "psci";
		};

		cpu3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a78ae";
			reg = <0x0 0x300>;
			enable-method = "psci";
		};

		cpu4: cpu@10000 {
			device_type = "cpu";
			compatible = "arm,cortex-a78ae";
			reg = <0x0 0x10000>;
			enable-method = "psci";
		};

		cpu5: cpu@10100 {
			device_type = "cpu";
			compatible = "arm,cortex-a78ae";
			reg = <0x0 0x10100>;
			enable-method = "psci";
		};

		cpu6: cpu@10200 {
			device_type = "cpu";
			compatible = "arm,cortex-a78ae";
			reg = <0x0 0x10200>;
			enable-method = "psci";
		};

		cpu7: cpu@10300 {
			device_type = "cpu";
			compatible = "arm,cortex-a78ae";
			reg = <0x0 0x10300>;
			enable-method = "psci";
		};

		cpu8: cpu@20000 {
			device_type = "cpu";
			compatible = "arm,cortex-a78ae";
			reg = <0x0 0x20000>;
			enable-method = "psci";
		};

		cpu9: cpu@20100 {
			device_type = "cpu";
			compatible = "arm,cortex-a78ae";
			reg = <0x0 0x20100>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	soc: soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0x20000000>;

		chipid@10000000 {
			compatible = "samsung,exynosautov920-chipid",
				     "samsung,exynos850-chipid";
			reg = <0x10000000 0x24>;
		};

		cmu_misc: clock-controller@10020000 {
			compatible = "samsung,exynosautov920-cmu-misc";
			reg = <0x10020000 0x8000>;
			#clock-cells = <1>;

			clocks = <&xtcxo>,
				 <&cmu_top DOUT_CLKCMU_MISC_NOC>;
			clock-names = "oscclk",
				      "noc";
		};

		gic: interrupt-controller@10400000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x10400000 0x10000>,
			      <0x10460000 0x140000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		cmu_peric0: clock-controller@10800000 {
			compatible = "samsung,exynosautov920-cmu-peric0";
			reg = <0x10800000 0x8000>;
			#clock-cells = <1>;

			clocks = <&xtcxo>,
				 <&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
				 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
			clock-names = "oscclk",
				      "noc",
				      "ip";
		};

		syscon_peric0: syscon@10820000 {
			compatible = "samsung,exynosautov920-peric0-sysreg",
				     "syscon";
			reg = <0x10820000 0x2000>;
		};

		pinctrl_peric0: pinctrl@10830000 {
			compatible = "samsung,exynosautov920-pinctrl";
			reg = <0x10830000 0x10000>;
			interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>;
		};

		usi_0: usi@108800c0 {
			compatible = "samsung,exynosautov920-usi",
				     "samsung,exynos850-usi";
			reg = <0x108800c0 0x20>;
			samsung,sysreg = <&syscon_peric0 0x1000>;
			samsung,mode = <USI_V2_UART>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
				 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
			clock-names = "pclk", "ipclk";
			status = "disabled";

			serial_0: serial@10880000 {
				compatible = "samsung,exynosautov920-uart",
					     "samsung,exynos850-uart";
				reg = <0x10880000 0xc0>;
				interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&uart0_bus>;
				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
					 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
				clock-names = "uart", "clk_uart_baud0";
				samsung,uart-fifosize = <256>;
				status = "disabled";
			};
		};

		pwm: pwm@109b0000 {
			compatible = "samsung,exynosautov920-pwm",
				     "samsung,exynos4210-pwm";
			reg = <0x109b0000 0x100>;
			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
			#pwm-cells = <3>;
			clocks = <&xtcxo>;
			clock-names = "timers";
			status = "disabled";
		};

		cmu_peric1: clock-controller@10c00000 {
			compatible = "samsung,exynosautov920-cmu-peric1";
			reg = <0x10c00000 0x8000>;
			#clock-cells = <1>;

			clocks = <&xtcxo>,
				 <&cmu_top DOUT_CLKCMU_PERIC1_NOC>,
				 <&cmu_top DOUT_CLKCMU_PERIC1_IP>;
			clock-names = "oscclk",
				      "noc",
				      "ip";
		};

		syscon_peric1: syscon@10c20000 {
			compatible = "samsung,exynosautov920-peric1-sysreg",
				     "syscon";
			reg = <0x10c20000 0x2000>;
		};

		pinctrl_peric1: pinctrl@10c30000 {
			compatible = "samsung,exynosautov920-pinctrl";
			reg = <0x10c30000 0x10000>;
			interrupts = <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
		};

		cmu_top: clock-controller@11000000 {
			compatible = "samsung,exynosautov920-cmu-top";
			reg = <0x11000000 0x8000>;
			#clock-cells = <1>;

			clocks = <&xtcxo>;
			clock-names = "oscclk";
		};

		pinctrl_alive: pinctrl@11850000 {
			compatible = "samsung,exynosautov920-pinctrl";
			reg = <0x11850000 0x10000>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynosautov920-wakeup-eint";
			};
		};

		pmu_system_controller: system-controller@11860000 {
			compatible = "samsung,exynosautov920-pmu",
				     "samsung,exynos7-pmu","syscon";
			reg = <0x11860000 0x10000>;
		};

		cmu_hsi0: clock-controller@16000000 {
			compatible = "samsung,exynosautov920-cmu-hsi0";
			reg = <0x16000000 0x8000>;
			#clock-cells = <1>;

			clocks = <&xtcxo>,
				 <&cmu_top DOUT_CLKCMU_HSI0_NOC>;
			clock-names = "oscclk",
				      "noc";
		};

		pinctrl_hsi0: pinctrl@16040000 {
			compatible = "samsung,exynosautov920-pinctrl";
			reg = <0x16040000 0x10000>;
			interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
		};

		cmu_hsi1: clock-controller@16400000 {
			compatible = "samsung,exynosautov920-cmu-hsi1";
			reg = <0x16400000 0x8000>;
			#clock-cells = <1>;

			clocks = <&xtcxo>,
				 <&cmu_top DOUT_CLKCMU_HSI1_NOC>,
				 <&cmu_top DOUT_CLKCMU_HSI1_USBDRD>,
				 <&cmu_top DOUT_CLKCMU_HSI1_MMC_CARD>;
			clock-names = "oscclk",
				      "noc",
				      "usbdrd",
				      "mmc_card";
		};

		pinctrl_hsi1: pinctrl@16450000 {
			compatible = "samsung,exynosautov920-pinctrl";
			reg = <0x16450000 0x10000>;
			interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_hsi2: pinctrl@16c10000 {
			compatible = "samsung,exynosautov920-pinctrl";
			reg = <0x16c10000 0x10000>;
			interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_hsi2ufs: pinctrl@16d20000 {
			compatible = "samsung,exynosautov920-pinctrl";
			reg = <0x16d20000 0x10000>;
			interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_aud: pinctrl@1a460000 {
			compatible = "samsung,exynosautov920-pinctrl";
			reg = <0x1a460000 0x10000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
	};
};

#include "exynosautov920-pinctrl.dtsi"