1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos8855 SoC device tree source 4 * 5 * Copyright (C) 2023 Samsung Electronics Co., Ltd. 6 * 7 * Samsung Exynos8855 SoC device nodes are listed in this file. 8 * Exynos8855 based board files can include this file and provide 9 * values for board specific bindings. 10 */ 11 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 compatible = "samsung,exynos8855"; 16 #address-cells = <2>; 17 #size-cells = <1>; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 pinctrl0 = &pinctrl_alive; 23 pinctrl1 = &pinctrl_cmgp; 24 pinctrl2 = &pinctrl_hsi_ufs; 25 pinctrl3 = &pinctrl_peric; 26 pinctrl4 = &pinctrl_pericmmc; 27 pinctrl5 = &pinctrl_usi; 28 }; 29 30 oscclk: clock-oscclk { 31 compatible = "fixed-clock"; 32 clock-output-names = "oscclk"; 33 #clock-cells = <0>; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cpu-map { 41 cluster0 { 42 core0 { 43 cpu = <&cpu0>; 44 }; 45 46 core1 { 47 cpu = <&cpu1>; 48 }; 49 50 core2 { 51 cpu = <&cpu2>; 52 }; 53 54 core3 { 55 cpu = <&cpu3>; 56 }; 57 }; 58 59 cluster1 { 60 core0 { 61 cpu = <&cpu4>; 62 }; 63 64 core1 { 65 cpu = <&cpu5>; 66 }; 67 68 core2 { 69 cpu = <&cpu6>; 70 }; 71 }; 72 73 cluster2 { 74 core0 { 75 cpu = <&cpu7>; 76 }; 77 }; 78 }; 79 80 cpu0: cpu@0 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a520"; 83 reg = <0x0>; 84 enable-method = "psci"; 85 }; 86 87 cpu1: cpu@100 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a520"; 90 reg = <0x100>; 91 enable-method = "psci"; 92 }; 93 94 cpu2: cpu@200 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a520"; 97 reg = <0x200>; 98 enable-method = "psci"; 99 }; 100 101 cpu3: cpu@300 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a520"; 104 reg = <0x300>; 105 enable-method = "psci"; 106 }; 107 108 cpu4: cpu@400 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a720"; 111 reg = <0x400>; 112 enable-method = "psci"; 113 }; 114 115 cpu5: cpu@500 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a720"; 118 reg = <0x500>; 119 enable-method = "psci"; 120 }; 121 122 cpu6: cpu@600 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a720"; 125 reg = <0x600>; 126 enable-method = "psci"; 127 }; 128 129 cpu7: cpu@700 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a720"; 132 reg = <0x700>; 133 enable-method = "psci"; 134 }; 135 }; 136 137 psci { 138 compatible = "arm,psci-1.0"; 139 method = "smc"; 140 }; 141 142 soc: soc@0 { 143 compatible = "simple-bus"; 144 #address-cells = <1>; 145 #size-cells = <1>; 146 ranges = <0x0 0x0 0x0 0x20000000>; 147 148 gic: interrupt-controller@10200000 { 149 compatible = "arm,gic-v3"; 150 #interrupt-cells = <3>; 151 interrupt-controller; 152 reg = <0x10200000 0x10000>, 153 <0x10240000 0x140000>; 154 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 155 }; 156 157 pinctrl_alive: pinctrl@11850000 { 158 compatible = "samsung,exynos8855-pinctrl"; 159 reg = <0x11850000 0x1000>; 160 161 wakeup-interrupt-controller { 162 compatible = "samsung,exynos8855-wakeup-eint", 163 "samsung,exynos7-wakeup-eint"; 164 }; 165 }; 166 167 pinctrl_cmgp: pinctrl@12030000 { 168 compatible = "samsung,exynos8855-pinctrl"; 169 reg = <0x12030000 0x1000>; 170 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 171 }; 172 173 pinctrl_usi: pinctrl@15030000 { 174 compatible = "samsung,exynos8855-pinctrl"; 175 reg = <0x15030000 0x1000>; 176 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 177 }; 178 179 pinctrl_peric: pinctrl@15440000 { 180 compatible = "samsung,exynos8855-pinctrl"; 181 reg = <0x15440000 0x1000>; 182 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 183 }; 184 185 pinctrl_pericmmc: pinctrl@154f0000 { 186 compatible = "samsung,exynos8855-pinctrl"; 187 reg = <0x154f0000 0x1000>; 188 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; 189 }; 190 191 pinctrl_hsi_ufs: pinctrl@17040000 { 192 compatible = "samsung,exynos8855-pinctrl"; 193 reg = <0x17040000 0x1000>; 194 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 195 }; 196 }; 197 198 timer { 199 compatible = "arm,armv8-timer"; 200 /* Hypervisor Virtual Timer interrupt is not wired to GIC */ 201 interrupts = 202 <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 203 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 204 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 205 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 206 }; 207}; 208 209#include "exynos8855-pinctrl.dtsi" 210