1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Axis ARTPEC-9 SoC device tree source 4 * 5 * Copyright (c) 2025 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * Copyright (c) 2025 Axis Communications AB. 8 * https://www.axis.com 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/clock/axis,artpec9-clk.h> 13 14/ { 15 compatible = "axis,artpec9"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 pinctrl0 = &pinctrl_fsys0; 22 pinctrl1 = &pinctrl_fsys1; 23 pinctrl2 = &pinctrl_peric; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu0: cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a55"; 33 reg = <0x0>; 34 enable-method = "psci"; 35 cpu-idle-states = <&cpu_sleep>; 36 clocks = <&cmu_cpucl CLK_GOUT_CPUCL_CLUSTER_CPU>; 37 clock-names = "cpu"; 38 }; 39 40 cpu1: cpu@100 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a55"; 43 reg = <0x100>; 44 enable-method = "psci"; 45 cpu-idle-states = <&cpu_sleep>; 46 }; 47 48 cpu2: cpu@200 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a55"; 51 reg = <0x200>; 52 enable-method = "psci"; 53 cpu-idle-states = <&cpu_sleep>; 54 }; 55 56 cpu3: cpu@300 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a55"; 59 reg = <0x300>; 60 enable-method = "psci"; 61 cpu-idle-states = <&cpu_sleep>; 62 }; 63 64 cpu4: cpu@400 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a55"; 67 reg = <0x400>; 68 enable-method = "psci"; 69 cpu-idle-states = <&cpu_sleep>; 70 }; 71 72 cpu5: cpu@500 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x500>; 76 enable-method = "psci"; 77 cpu-idle-states = <&cpu_sleep>; 78 }; 79 80 idle-states { 81 entry-method = "psci"; 82 83 cpu_sleep: cpu-sleep { 84 compatible = "arm,idle-state"; 85 arm,psci-suspend-param = <0x0010000>; 86 local-timer-stop; 87 entry-latency-us = <300>; 88 exit-latency-us = <1200>; 89 min-residency-us = <2000>; 90 }; 91 }; 92 }; 93 94 fin_pll: clock-finpll { 95 compatible = "fixed-factor-clock"; 96 clocks = <&osc_clk>; 97 #clock-cells = <0>; 98 clock-div = <2>; 99 clock-mult = <1>; 100 clock-output-names = "fin_pll"; 101 }; 102 103 osc_clk: clock-osc { 104 /* XXTI */ 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-output-names = "osc_clk"; 108 }; 109 110 pmu { 111 compatible = "arm,cortex-a55-pmu"; 112 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 113 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>; 114 }; 115 116 psci { 117 compatible = "arm,psci-0.2"; 118 method = "smc"; 119 }; 120 121 soc: soc@0 { 122 compatible = "simple-bus"; 123 ranges = <0x0 0x0 0x0 0x0 0x0 0x17000000>; 124 #address-cells = <2>; 125 #size-cells = <2>; 126 127 cmu_imem: clock-controller@10010000 { 128 compatible = "axis,artpec9-cmu-imem"; 129 reg = <0x0 0x10010000 0x0 0x4000>; 130 #clock-cells = <1>; 131 clocks = <&fin_pll>, 132 <&cmu_cmu CLK_DOUT_CMU_IMEM_ACLK>, 133 <&cmu_cmu CLK_DOUT_CMU_IMEM_CA5>, 134 <&cmu_cmu CLK_DOUT_CMU_IMEM_JPEG>, 135 <&cmu_cmu CLK_DOUT_CMU_IMEM_SSS>; 136 clock-names = "fin_pll", "aclk", "ca5", "jpeg", "sss"; 137 }; 138 139 timer@10040000 { 140 compatible = "axis,artpec9-mct", "samsung,exynos4210-mct"; 141 reg = <0x0 0x10040000 0x0 0x1000>; 142 clocks = <&fin_pll>, <&cmu_imem CLK_GOUT_IMEM_MCT0_PCLK>; 143 clock-names = "fin_pll", "mct"; 144 interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 156 }; 157 158 gic: interrupt-controller@10400000 { 159 compatible = "arm,gic-v3"; 160 reg = <0x0 0x10400000 0x0 0x00040000>, 161 <0x0 0x10440000 0x0 0x000c0000>; 162 #interrupt-cells = <3>; 163 interrupt-controller; 164 redistributor-stride = <0x0 0x20000>; 165 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 166 }; 167 168 cmu_cpucl: clock-controller@12810000 { 169 compatible = "axis,artpec9-cmu-cpucl"; 170 reg = <0x0 0x12810000 0x0 0x4000>; 171 #clock-cells = <1>; 172 clocks = <&fin_pll>, 173 <&cmu_cmu CLK_DOUT_CMU_CPUCL_SWITCH>; 174 clock-names = "fin_pll", "switch"; 175 }; 176 177 cmu_cmu: clock-controller@12c00000 { 178 compatible = "axis,artpec9-cmu-cmu"; 179 reg = <0x0 0x12c00000 0x0 0x4000>; 180 #clock-cells = <1>; 181 clocks = <&fin_pll>; 182 clock-names = "fin_pll"; 183 }; 184 185 cmu_core: clock-controller@12c10000 { 186 compatible = "axis,artpec9-cmu-core"; 187 reg = <0x0 0x12c10000 0x0 0x4000>; 188 #clock-cells = <1>; 189 clocks = <&fin_pll>, 190 <&cmu_cmu CLK_DOUT_CMU_CORE_MAIN>; 191 clock-names = "fin_pll", "main"; 192 }; 193 194 cmu_bus: clock-controller@13410000 { 195 compatible = "axis,artpec9-cmu-bus"; 196 reg = <0x0 0x13410000 0x0 0x4000>; 197 #clock-cells = <1>; 198 clocks = <&fin_pll>, 199 <&cmu_cmu CLK_DOUT_CMU_BUS>; 200 clock-names = "fin_pll", "bus"; 201 }; 202 203 cmu_peri: clock-controller@14010000 { 204 compatible = "axis,artpec9-cmu-peri"; 205 reg = <0x0 0x14010000 0x0 0x4000>; 206 #clock-cells = <1>; 207 clocks = <&fin_pll>, 208 <&cmu_cmu CLK_DOUT_CMU_PERI_IP>, 209 <&cmu_cmu CLK_DOUT_CMU_PERI_DISP>; 210 clock-names = "fin_pll", "ip", "disp"; 211 }; 212 213 pinctrl_peric: pinctrl@141f0000 { 214 compatible = "axis,artpec9-pinctrl"; 215 reg = <0x0 0x141f0000 0x0 0x1000>; 216 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 217 }; 218 219 cmu_fsys0: clock-controller@14410000 { 220 compatible = "axis,artpec9-cmu-fsys0"; 221 reg = <0x0 0x14410000 0x0 0x4000>; 222 #clock-cells = <1>; 223 clocks = <&fin_pll>, 224 <&cmu_cmu CLK_DOUT_CMU_FSYS0_BUS>, 225 <&cmu_cmu CLK_DOUT_CMU_FSYS0_IP>; 226 clock-names = "fin_pll", "bus", "ip"; 227 }; 228 229 pinctrl_fsys0: pinctrl@14430000 { 230 compatible = "axis,artpec9-pinctrl"; 231 reg = <0x0 0x14430000 0x0 0x1000>; 232 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 233 }; 234 235 cmu_fsys1: clock-controller@14c10000 { 236 compatible = "axis,artpec9-cmu-fsys1"; 237 reg = <0x0 0x14c10000 0x0 0x4000>; 238 #clock-cells = <1>; 239 clocks = <&fin_pll>, 240 <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN0>, 241 <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN1>, 242 <&cmu_cmu CLK_DOUT_CMU_FSYS1_BUS>; 243 clock-names = "fin_pll", "scan0", "scan1", "bus"; 244 }; 245 246 pinctrl_fsys1: pinctrl@14c30000 { 247 compatible = "axis,artpec9-pinctrl"; 248 reg = <0x0 0x14c30000 0x0 0x1000>; 249 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 250 }; 251 252 pmu_system_controller: system-controller@14c40000 { 253 compatible = "axis,artpec9-pmu", "samsung,exynos7-pmu", "syscon"; 254 reg = <0x0 0x14c40000 0x0 0x10000>; 255 }; 256 257 serial_0: serial@14c70000 { 258 compatible = "axis,artpec9-uart", "samsung,exynos8895-uart"; 259 reg = <0x0 0x14c70000 0x0 0x100>; 260 clocks = <&cmu_fsys1 CLK_GOUT_FSYS1_UART0_PCLK>, 261 <&cmu_fsys1 CLK_GOUT_FSYS1_UART0_SCLK_UART>; 262 clock-names = "uart", "clk_uart_baud0"; 263 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 264 pinctrl-names = "default"; 265 pinctrl-0 = <&serial0_bus>; 266 samsung,uart-fifosize = <64>; 267 }; 268 }; 269 270 timer { 271 compatible = "arm,armv8-timer"; 272 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 273 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 274 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 275 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 276 }; 277}; 278