1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AST27xx SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2026 ASPEED Technology Inc. 6 */ 7 8#include <dt-bindings/clock/aspeed,ast2700-scu.h> 9#include <dt-bindings/reset/aspeed,ast2700-scu.h> 10#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h> 11 12&soc1 { 13 fmc: spi@14000000 { 14 reg = <0x0 0x14000000 0x0 0xc4>, <0x1 0x00000000 0x0 0x80000000>; 15 #address-cells = <1>; 16 #size-cells = <0>; 17 compatible = "aspeed,ast2700-fmc"; 18 status = "disabled"; 19 clocks = <&syscon1 SCU1_CLK_AHB>; 20 interrupts-extended = <&intc1 121>; 21 num-cs = <3>; 22 23 flash@0 { 24 reg = < 0 >; 25 compatible = "jedec,spi-nor"; 26 spi-max-frequency = <50000000>; 27 spi-rx-bus-width = <2>; 28 status = "disabled"; 29 }; 30 31 flash@1 { 32 reg = < 1 >; 33 compatible = "jedec,spi-nor"; 34 spi-max-frequency = <50000000>; 35 spi-rx-bus-width = <2>; 36 status = "disabled"; 37 }; 38 39 flash@2 { 40 reg = < 2 >; 41 compatible = "jedec,spi-nor"; 42 spi-max-frequency = <50000000>; 43 spi-rx-bus-width = <2>; 44 status = "disabled"; 45 }; 46 }; 47 48 spi0: spi@14010000 { 49 reg = <0x0 0x14010000 0x0 0xc4>, <0x1 0x80000000 0x0 0x80000000>; 50 #address-cells = <1>; 51 #size-cells = <0>; 52 compatible = "aspeed,ast2700-spi"; 53 clocks = <&syscon1 SCU1_CLK_AHB>; 54 interrupts-extended = <&intc1 122>; 55 status = "disabled"; 56 num-cs = <2>; 57 58 flash@0 { 59 reg = < 0 >; 60 compatible = "jedec,spi-nor"; 61 spi-max-frequency = <50000000>; 62 spi-rx-bus-width = <2>; 63 status = "disabled"; 64 }; 65 66 flash@1 { 67 reg = < 1 >; 68 compatible = "jedec,spi-nor"; 69 spi-max-frequency = <50000000>; 70 spi-rx-bus-width = <2>; 71 status = "disabled"; 72 }; 73 }; 74 75 spi1: spi@14020000 { 76 reg = <0x0 0x14020000 0x0 0xc4>, <0x2 0x00000000 0x0 0x80000000>; 77 #address-cells = <1>; 78 #size-cells = <0>; 79 compatible = "aspeed,ast2700-spi"; 80 clocks = <&syscon1 SCU1_CLK_AHB>; 81 interrupts-extended = <&intc1 123>; 82 status = "disabled"; 83 num-cs = <2>; 84 85 flash@0 { 86 reg = < 0 >; 87 compatible = "jedec,spi-nor"; 88 spi-max-frequency = <50000000>; 89 spi-rx-bus-width = <2>; 90 status = "disabled"; 91 }; 92 93 flash@1 { 94 reg = < 1 >; 95 compatible = "jedec,spi-nor"; 96 spi-max-frequency = <50000000>; 97 spi-rx-bus-width = <2>; 98 status = "disabled"; 99 }; 100 }; 101 102 spi2: spi@14030000 { 103 reg = <0x0 0x14030000 0x0 0x1f0>, <0x2 0x80000000 0x0 0x80000000>; 104 #address-cells = <1>; 105 #size-cells = <0>; 106 compatible = "aspeed,ast2700-spi"; 107 clocks = <&syscon1 SCU1_CLK_AHB>; 108 resets = <&syscon1 SCU1_RESET_SPI2>; 109 interrupts-extended = <&intc1 124>; 110 num-cs = <2>; 111 status = "disabled"; 112 }; 113 114 mdio0: mdio@14040000 { 115 compatible = "aspeed,ast2700-mdio", "aspeed,ast2600-mdio"; 116 reg = <0 0x14040000 0 0x8>; 117 resets = <&syscon1 SCU1_RESET_MII>; 118 pinctrl-names = "default"; 119 pinctrl-0 = <&pinctrl_mdio0_default>; 120 status = "disabled"; 121 }; 122 123 mdio1: mdio@14040008 { 124 compatible = "aspeed,ast2700-mdio", "aspeed,ast2600-mdio"; 125 reg = <0 0x14040008 0 0x8>; 126 resets = <&syscon1 SCU1_RESET_MII>; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_mdio1_default>; 129 status = "disabled"; 130 }; 131 132 mdio2: mdio@14040010 { 133 compatible = "aspeed,ast2700-mdio", "aspeed,ast2600-mdio"; 134 reg = <0 0x14040010 0 0x8>; 135 resets = <&syscon1 SCU1_RESET_MII>; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_mdio2_default>; 138 status = "disabled"; 139 }; 140 141 sdio_controller: sdc@14080000 { 142 compatible = "aspeed,ast2700-sd-controller", "aspeed,ast2600-sd-controller"; 143 reg = <0 0x14080000 0 0x100>; 144 #address-cells = <1>; 145 #size-cells = <1>; 146 ranges = <0x0 0x0 0x14080000 0x10000>; 147 clocks = <&syscon1 SCU1_CLK_GATE_SDCLK>; 148 resets = <&syscon1 SCU1_RESET_SD>; 149 status = "disabled"; 150 151 sdhci: sdhci@100 { 152 compatible = "aspeed,ast2700-sdhci", "aspeed,ast2600-sdhci"; 153 reg = <0x100 0x100>; 154 sdhci,auto-cmd12; 155 interrupts-extended = <&intc1 161>; 156 clocks = <&syscon1 SCU1_CLK_GATE_SDCLK>; 157 pinctrl-names = "default"; 158 pinctrl-0 = <&pinctrl_sd_default>; 159 status = "disabled"; 160 }; 161 }; 162 163 pwm_tach: pwm-tach-controller@140c0000 { 164 compatible = "aspeed,ast2700-pwm-tach", "aspeed,ast2600-pwm-tach"; 165 reg = <0x0 0x140c0000 0 0x100>; 166 clocks = <&syscon1 SCU1_CLK_AHB>; 167 resets = <&syscon1 SCU1_RESET_PWM>; 168 #pwm-cells = <3>; 169 status = "disabled"; 170 }; 171 172 uhci1: usb@14110000 { 173 compatible = "aspeed,ast2700-uhci", "generic-uhci"; 174 reg = <0x0 0x14110000 0x0 0x100>; 175 interrupts-extended = <&intc1 155>; 176 #ports = <2>; 177 clocks = <&syscon1 SCU1_CLK_GATE_UHCICLK>; 178 resets = <&syscon1 SCU1_RESET_UHCI>; 179 status = "disabled"; 180 }; 181 182 vhubc: usb-vhub@14120000 { 183 compatible = "aspeed,ast2700-usb-vhub"; 184 reg = <0x0 0x14120000 0x0 0x820>; 185 interrupts-extended = <&intc1 156>; 186 clocks = <&syscon1 SCU1_CLK_GATE_PORTCUSB2CLK>; 187 resets = <&syscon1 SCU1_RESET_PORTC_VHUB_EHCI>; 188 aspeed,vhub-downstream-ports = <7>; 189 aspeed,vhub-generic-endpoints = <21>; 190 pinctrl-names = "default"; 191 pinctrl-0 = <&pinctrl_usb2cd_default>; 192 status = "disabled"; 193 }; 194 195 ehci2: usb@14121000 { 196 compatible = "aspeed,ast2700-ehci", "generic-ehci"; 197 reg = <0x0 0x14121000 0x0 0x100>; 198 interrupts-extended = <&intc1 156>; 199 clocks = <&syscon1 SCU1_CLK_GATE_PORTCUSB2CLK>; 200 resets = <&syscon1 SCU1_RESET_PORTC_VHUB_EHCI>; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_usb2ch_default>; 203 status = "disabled"; 204 }; 205 206 vhubd: usb-vhub@14122000 { 207 compatible = "aspeed,ast2700-usb-vhub"; 208 reg = <0x0 0x14122000 0x0 0x820>; 209 interrupts-extended = <&intc1 157>; 210 clocks = <&syscon1 SCU1_CLK_GATE_PORTDUSB2CLK>; 211 resets = <&syscon1 SCU1_RESET_PORTD_VHUB_EHCI>; 212 aspeed,vhub-downstream-ports = <7>; 213 aspeed,vhub-generic-endpoints = <21>; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_usb2dd_default>; 216 status = "disabled"; 217 }; 218 219 ehci3: usb@14123000 { 220 compatible = "aspeed,ast2700-ehci", "generic-ehci"; 221 reg = <0x0 0x14123000 0x0 0x100>; 222 interrupts-extended = <&intc1 157>; 223 clocks = <&syscon1 SCU1_CLK_GATE_PORTDUSB2CLK>; 224 resets = <&syscon1 SCU1_RESET_PORTD_VHUB_EHCI>; 225 pinctrl-names = "default"; 226 pinctrl-0 = <&pinctrl_usb2dh_default>; 227 status = "disabled"; 228 }; 229 230 sram1: sram@14b80000 { 231 compatible = "mmio-sram"; 232 reg = <0x0 0x14b80000 0x0 0x40000>; 233 ranges = <0x0 0x0 0x14b80000 0x40000>; 234 #address-cells = <1>; 235 #size-cells = <1>; 236 237 soc1-sram@0 { 238 reg = <0x0 0x40000>; 239 export; 240 }; 241 }; 242 243 adc0: adc@14c00000 { 244 compatible = "aspeed,ast2700-adc0"; 245 reg = <0x0 0x14c00000 0 0x100>; 246 clocks = <&syscon1 SCU1_CLK_AHB>; 247 resets = <&syscon1 SCU1_RESET_ADC>; 248 interrupts-extended = <&intc1 80>; 249 #io-channel-cells = <1>; 250 status = "disabled"; 251 }; 252 253 adc1: adc@14c00100 { 254 compatible = "aspeed,ast2700-adc1"; 255 reg = <0x0 0x14c00100 0x0 0x100>; 256 clocks = <&syscon1 SCU1_CLK_AHB>; 257 resets = <&syscon1 SCU1_RESET_ADC>; 258 interrupts-extended = <&intc1 80>; 259 #io-channel-cells = <1>; 260 status = "disabled"; 261 }; 262 263 syscon1: syscon@14c02000 { 264 compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd"; 265 reg = <0x0 0x14c02000 0x0 0x1000>; 266 ranges = <0x0 0x0 0x14c02000 0x1000>; 267 #address-cells = <1>; 268 #size-cells = <1>; 269 #clock-cells = <1>; 270 #reset-cells = <1>; 271 272 scu_ic2: interrupt-controller@100 { 273 compatible = "aspeed,ast2700-scu-ic2"; 274 reg = <0x100 0x8>; 275 interrupts-extended = <&intc1 160>; 276 #interrupt-cells = <1>; 277 interrupt-controller; 278 }; 279 280 scu_ic3: interrupt-controller@108 { 281 compatible = "aspeed,ast2700-scu-ic3"; 282 reg = <0x108 0x8>; 283 interrupts-extended = <&intc1 186>; 284 #interrupt-cells = <1>; 285 interrupt-controller; 286 }; 287 288 pinctrl1: pinctrl@400 { 289 compatible = "aspeed,ast2700-soc1-pinctrl"; 290 reg = <0x400 0x2a0>; 291 }; 292 }; 293 294 gpio1: gpio@14c0b000 { 295 #gpio-cells = <2>; 296 gpio-controller; 297 compatible = "aspeed,ast2700-gpio"; 298 reg = <0x0 0x14c0b000 0x0 0x1000>; 299 interrupts-extended = <&intc1 82>; 300 gpio-ranges = <&pinctrl1 0 0 216>; 301 ngpios = <216>; 302 clocks = <&syscon1 SCU1_CLK_AHB>; 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 }; 306 307 sgpiom0: sgpiom@14c0c000 { 308 #gpio-cells = <2>; 309 gpio-controller; 310 compatible = "aspeed,ast2700-sgpiom"; 311 reg = <0x0 0x14c0c000 0x0 0x100>; 312 interrupts-extended = <&intc1 85>; 313 ngpios = <256>; 314 clocks = <&syscon1 SCU1_CLK_APB>; 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 bus-frequency = <12000000>; 318 status = "disabled"; 319 }; 320 321 sgpiom1: sgpiom@14c0d000 { 322 #gpio-cells = <2>; 323 gpio-controller; 324 compatible = "aspeed,ast2700-sgpiom"; 325 reg = <0x0 0x14c0d000 0x0 0x100>; 326 interrupts-extended = <&intc1 88>; 327 ngpios = <256>; 328 clocks = <&syscon1 SCU1_CLK_APB>; 329 interrupt-controller; 330 #interrupt-cells = <2>; 331 bus-frequency = <12000000>; 332 status = "disabled"; 333 }; 334 335 intc1: interrupt-controller@14c18000 { 336 compatible = "aspeed,ast2700-intc1"; 337 reg = <0 0x14c18000 0 0x400>; 338 interrupt-controller; 339 interrupt-parent = <&intc0>; 340 #interrupt-cells = <1>; 341 aspeed,interrupt-ranges = 342 <0 6 &intc0 480>, /* M0 ~ M5 */ 343 <10 6 &intc0 490>, /* M10 ~ M15 */ 344 <20 6 &intc0 500>, /* M20 ~ M25 */ 345 <30 6 &intc0 510>, /* M30 ~ M35 */ 346 <40 6 &intc0 520>, /* M40 ~ M45 */ 347 <50 1 &bootmcu_hlic 11>; /* only 1 pin to BootMCU */ 348 }; 349 350 uart0: serial@14c33000 { 351 compatible = "ns16550a"; 352 reg = <0x0 0x14c33000 0x0 0x100>; 353 reg-shift = <2>; 354 reg-io-width = <4>; 355 clocks = <&syscon1 SCU1_CLK_GATE_UART0CLK>; 356 interrupts-extended = <&intc1 135>; 357 no-loopback-test; 358 status = "disabled"; 359 }; 360 361 uart1: serial@14c33100 { 362 compatible = "ns16550a"; 363 reg = <0x0 0x14c33100 0x0 0x100>; 364 reg-shift = <2>; 365 reg-io-width = <4>; 366 clocks = <&syscon1 SCU1_CLK_GATE_UART1CLK>; 367 interrupts-extended = <&intc1 136>; 368 no-loopback-test; 369 status = "disabled"; 370 }; 371 372 uart2: serial@14c33200 { 373 compatible = "ns16550a"; 374 reg = <0x0 0x14c33200 0x0 0x100>; 375 reg-shift = <2>; 376 reg-io-width = <4>; 377 clocks = <&syscon1 SCU1_CLK_GATE_UART2CLK>; 378 interrupts-extended = <&intc1 137>; 379 no-loopback-test; 380 status = "disabled"; 381 }; 382 383 uart3: serial@14c33300 { 384 compatible = "ns16550a"; 385 reg = <0x0 0x14c33300 0x0 0x100>; 386 reg-shift = <2>; 387 reg-io-width = <4>; 388 clocks = <&syscon1 SCU1_CLK_GATE_UART3CLK>; 389 interrupts-extended = <&intc1 138>; 390 no-loopback-test; 391 status = "disabled"; 392 }; 393 394 uart5: serial@14c33400 { 395 compatible = "ns16550a"; 396 reg = <0x0 0x14c33400 0x0 0x100>; 397 reg-shift = <2>; 398 reg-io-width = <4>; 399 clocks = <&syscon1 SCU1_CLK_GATE_UART5CLK>; 400 interrupts-extended = <&intc1 139>; 401 no-loopback-test; 402 status = "disabled"; 403 }; 404 405 uart6: serial@14c33500 { 406 compatible = "ns16550a"; 407 reg = <0x0 0x14c33500 0x0 0x100>; 408 reg-shift = <2>; 409 reg-io-width = <4>; 410 clocks = <&syscon1 SCU1_CLK_GATE_UART6CLK>; 411 interrupts-extended = <&intc1 140>; 412 no-loopback-test; 413 status = "disabled"; 414 }; 415 416 uart7: serial@14c33600 { 417 compatible = "ns16550a"; 418 reg = <0x0 0x14c33600 0x0 0x100>; 419 reg-shift = <2>; 420 reg-io-width = <4>; 421 clocks = <&syscon1 SCU1_CLK_GATE_UART7CLK>; 422 interrupts-extended = <&intc1 141>; 423 no-loopback-test; 424 status = "disabled"; 425 }; 426 427 uart8: serial@14c33700 { 428 compatible = "ns16550a"; 429 reg = <0x0 0x14c33700 0x0 0x100>; 430 reg-shift = <2>; 431 reg-io-width = <4>; 432 clocks = <&syscon1 SCU1_CLK_GATE_UART8CLK>; 433 interrupts-extended = <&intc1 142>; 434 no-loopback-test; 435 status = "disabled"; 436 }; 437 438 uart9: serial@14c33800 { 439 compatible = "ns16550a"; 440 reg = <0x0 0x14c33800 0x0 0x100>; 441 reg-shift = <2>; 442 reg-io-width = <4>; 443 clocks = <&syscon1 SCU1_CLK_GATE_UART9CLK>; 444 interrupts-extended = <&intc1 143>; 445 no-loopback-test; 446 status = "disabled"; 447 }; 448 449 uart10: serial@14c33900 { 450 compatible = "ns16550a"; 451 reg = <0x0 0x14c33900 0x0 0x100>; 452 reg-shift = <2>; 453 reg-io-width = <4>; 454 clocks = <&syscon1 SCU1_CLK_GATE_UART10CLK>; 455 interrupts-extended = <&intc1 144>; 456 no-loopback-test; 457 status = "disabled"; 458 }; 459 460 uart11: serial@14c33a00 { 461 compatible = "ns16550a"; 462 reg = <0x0 0x14c33a00 0x0 0x100>; 463 reg-shift = <2>; 464 reg-io-width = <4>; 465 clocks = <&syscon1 SCU1_CLK_GATE_UART11CLK>; 466 interrupts-extended = <&intc1 145>; 467 no-loopback-test; 468 status = "disabled"; 469 }; 470 471 uart12: serial@14c33b00 { 472 compatible = "ns16550a"; 473 reg = <0x0 0x14c33b00 0x0 0x100>; 474 reg-shift = <2>; 475 reg-io-width = <4>; 476 clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>; 477 interrupts-extended = <&intc1 146>; 478 no-loopback-test; 479 status = "disabled"; 480 }; 481 482 uart13: serial@14c33c00 { 483 compatible = "ns16550a"; 484 reg = <0x0 0x14c33c00 0x0 0x100>; 485 reg-shift = <2>; 486 reg-io-width = <4>; 487 clocks = <&syscon1 SCU1_CLK_UART13>; 488 interrupts-extended = <&intc1 23>; 489 no-loopback-test; 490 status = "disabled"; 491 }; 492 493 uart14: serial@14c33d00 { 494 compatible = "ns16550a"; 495 reg = <0x0 0x14c33d00 0x0 0x100>; 496 reg-shift = <2>; 497 reg-io-width = <4>; 498 clocks = <&syscon1 SCU1_CLK_UART14>; 499 interrupts-extended = <&intc1 55>; 500 no-loopback-test; 501 status = "disabled"; 502 }; 503 504 wdt0: watchdog@14c37000 { 505 compatible = "aspeed,ast2700-wdt"; 506 reg = <0x0 0x14c37000 0x0 0x80>; 507 }; 508 509 wdt1: watchdog@14c37080 { 510 compatible = "aspeed,ast2700-wdt"; 511 reg = <0x0 0x14c37080 0x0 0x80>; 512 }; 513 514 wdt2: watchdog@14c37100 { 515 compatible = "aspeed,ast2700-wdt"; 516 reg = <0x0 0x14c37100 0x0 0x80>; 517 status = "disabled"; 518 }; 519 520 wdt3: watchdog@14c37180 { 521 compatible = "aspeed,ast2700-wdt"; 522 reg = <0x0 0x14c37180 0x0 0x80>; 523 status = "disabled"; 524 }; 525 526 mbox2: mbox@14c39200 { 527 compatible = "aspeed,ast2700-mailbox"; 528 reg = <0x0 0x14c39200 0x0 0x100>, <0x0 0x14c39300 0x0 0x100>; 529 reg-names = "tx", "rx"; 530 interrupts-extended = <&intc1 177>; 531 #mbox-cells = <1>; 532 }; 533 534 fsim0: fsi@21800000 { 535 compatible = "aspeed,ast2700-fsi-master"; 536 reg = <0x0 0x21800000 0x0 0x94>; 537 interrupts-extended = <&intc1 166>; 538 pinctrl-names = "default"; 539 pinctrl-0 = <&pinctrl_fsi0_default>; 540 clocks = <&syscon1 SCU1_CLK_GATE_FSICLK>; 541 resets = <&syscon1 SCU1_RESET_FSI>; 542 status = "disabled"; 543 }; 544 545 fsim1: fsi@23800000 { 546 compatible = "aspeed,ast2700-fsi-master"; 547 reg = <0x0 0x23800000 0x0 0x94>; 548 interrupts-extended = <&intc1 167>; 549 pinctrl-names = "default"; 550 pinctrl-0 = <&pinctrl_fsi2_default>; 551 clocks = <&syscon1 SCU1_CLK_GATE_FSICLK>; 552 resets = <&syscon1 SCU1_RESET_FSI>; 553 status = "disabled"; 554 }; 555}; 556 557#include "aspeed-g7-soc1-pinctrl.dtsi" 558