1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2/* 3 * Copyright (c) 2025, Arm Limited. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7 8/ { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 interrupt-parent = <&gic>; 12 13 soc_clk24mhz: clock-24000000 { 14 compatible = "fixed-clock"; 15 #clock-cells = <0>; 16 clock-frequency = <24000000>; 17 clock-output-names = "refclk24mhz"; 18 }; 19 20 cpus { 21 #address-cells = <2>; 22 #size-cells = <0>; 23 24 /* 25 * The latency and residency numbers below are for illustrative 26 * purposes only and may vary on actual silicon. These values are 27 * considered just to demonstrate that the cpuidle governor logic 28 * works. 29 */ 30 idle-states { 31 entry-method = "psci"; 32 33 cpu_sleep: cpu-sleep { 34 compatible = "arm,idle-state"; 35 arm,psci-suspend-param = <0x10000>; 36 entry-latency-us = <800>; 37 exit-latency-us = <3200>; 38 local-timer-stop; 39 min-residency-us = <4200>; 40 }; 41 42 cluster_sleep: cluster-sleep { 43 compatible = "arm,idle-state"; 44 arm,psci-suspend-param = <0x1010000>; 45 entry-latency-us = <1000>; 46 exit-latency-us = <3200>; 47 local-timer-stop; 48 min-residency-us = <4500>; 49 }; 50 }; 51 52 cpu-map { 53 cluster0 { 54 core0 { cpu = <&cpu0>; }; 55 core1 { cpu = <&cpu1>; }; 56 core2 { cpu = <&cpu2>; }; 57 core3 { cpu = <&cpu3>; }; 58 }; 59 60 cluster1 { 61 core0 { cpu = <&cpu4>; }; 62 core1 { cpu = <&cpu5>; }; 63 core2 { cpu = <&cpu6>; }; 64 core3 { cpu = <&cpu7>; }; 65 }; 66 67 cluster2 { 68 core0 { cpu = <&cpu8>; }; 69 core1 { cpu = <&cpu9>; }; 70 core2 { cpu = <&cpu10>; }; 71 core3 { cpu = <&cpu11>; }; 72 }; 73 74 cluster3 { 75 core0 { cpu = <&cpu12>; }; 76 core1 { cpu = <&cpu13>; }; 77 core2 { cpu = <&cpu14>; }; 78 core3 { cpu = <&cpu15>; }; 79 }; 80 }; 81 82 cpu0: cpu@0 { 83 compatible = "arm,cortex-a720ae"; 84 device_type = "cpu"; 85 reg = <0x00 0x0000>; 86 enable-method = "psci"; 87 88 clocks = <&scmi_dvfs 0>; 89 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 90 next-level-cache = <&cl0_l2_0>; 91 92 i-cache-line-size = <64>; 93 i-cache-sets = <256>; 94 i-cache-size = <0x10000>; 95 96 d-cache-line-size = <64>; 97 d-cache-sets = <256>; 98 d-cache-size = <0x10000>; 99 100 cl0_l2_0: l2-cache { 101 compatible = "cache"; 102 cache-level = <2>; 103 cache-line-size = <64>; 104 cache-sets = <0x400>; /* 8-way set */ 105 cache-size = <0x80000>; /* 512KB */ 106 cache-unified; 107 next-level-cache = <&cl0_l3>; 108 }; 109 }; 110 111 cpu1: cpu@100 { 112 compatible = "arm,cortex-a720ae"; 113 device_type = "cpu"; 114 reg = <0x00 0x0100>; 115 enable-method = "psci"; 116 117 clocks = <&scmi_dvfs 0>; 118 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 119 next-level-cache = <&cl0_l2_1>; 120 121 i-cache-line-size = <64>; 122 i-cache-sets = <256>; 123 i-cache-size = <0x10000>; 124 125 d-cache-line-size = <64>; 126 d-cache-sets = <256>; 127 d-cache-size = <0x10000>; 128 129 cl0_l2_1: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-line-size = <64>; 133 cache-sets = <0x400>; /* 8-way set */ 134 cache-size = <0x80000>; /* 512KB */ 135 cache-unified; 136 next-level-cache = <&cl0_l3>; 137 }; 138 }; 139 140 cpu2: cpu@200 { 141 compatible = "arm,cortex-a720ae"; 142 device_type = "cpu"; 143 reg = <0x00 0x0200>; 144 enable-method = "psci"; 145 146 clocks = <&scmi_dvfs 0>; 147 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 148 next-level-cache = <&cl0_l2_2>; 149 150 i-cache-line-size = <64>; 151 i-cache-sets = <256>; 152 i-cache-size = <0x10000>; 153 154 d-cache-line-size = <64>; 155 d-cache-sets = <256>; 156 d-cache-size = <0x10000>; 157 158 cl0_l2_2: l2-cache { 159 compatible = "cache"; 160 cache-level = <2>; 161 cache-line-size = <64>; 162 cache-sets = <0x400>; /* 8-way set */ 163 cache-size = <0x80000>; /* 512KB */ 164 cache-unified; 165 next-level-cache = <&cl0_l3>; 166 }; 167 }; 168 169 cpu3: cpu@300 { 170 compatible = "arm,cortex-a720ae"; 171 device_type = "cpu"; 172 reg = <0x00 0x0300>; 173 enable-method = "psci"; 174 175 clocks = <&scmi_dvfs 0>; 176 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 177 next-level-cache = <&cl0_l2_3>; 178 179 i-cache-line-size = <64>; 180 i-cache-sets = <256>; 181 i-cache-size = <0x10000>; 182 183 d-cache-line-size = <64>; 184 d-cache-sets = <256>; 185 d-cache-size = <0x10000>; 186 187 cl0_l2_3: l2-cache { 188 compatible = "cache"; 189 cache-level = <2>; 190 cache-line-size = <64>; 191 cache-sets = <0x400>; /* 8-way set */ 192 cache-size = <0x80000>; /* 512KB */ 193 cache-unified; 194 next-level-cache = <&cl0_l3>; 195 }; 196 }; 197 198 cpu4: cpu@10000 { 199 compatible = "arm,cortex-a720ae"; 200 device_type = "cpu"; 201 reg = <0x00 0x10000>; 202 enable-method = "psci"; 203 204 clocks = <&scmi_dvfs 0>; 205 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 206 next-level-cache = <&cl1_l2_0>; 207 208 i-cache-line-size = <64>; 209 i-cache-sets = <256>; 210 i-cache-size = <0x10000>; 211 212 d-cache-line-size = <64>; 213 d-cache-sets = <256>; 214 d-cache-size = <0x10000>; 215 216 cl1_l2_0: l2-cache { 217 compatible = "cache"; 218 cache-level = <2>; 219 cache-line-size = <64>; 220 cache-sets = <0x400>; /* 8-way set */ 221 cache-size = <0x80000>; /* 512KB */ 222 cache-unified; 223 next-level-cache = <&cl1_l3>; 224 }; 225 }; 226 227 cpu5: cpu@10100 { 228 compatible = "arm,cortex-a720ae"; 229 device_type = "cpu"; 230 reg = <0x00 0x10100>; 231 enable-method = "psci"; 232 233 clocks = <&scmi_dvfs 0>; 234 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 235 next-level-cache = <&cl1_l2_1>; 236 237 i-cache-line-size = <64>; 238 i-cache-sets = <256>; 239 i-cache-size = <0x10000>; 240 241 d-cache-line-size = <64>; 242 d-cache-sets = <256>; 243 d-cache-size = <0x10000>; 244 245 cl1_l2_1: l2-cache { 246 compatible = "cache"; 247 cache-level = <2>; 248 cache-line-size = <64>; 249 cache-sets = <0x400>; /* 8-way set */ 250 cache-size = <0x80000>; /* 512KB */ 251 cache-unified; 252 next-level-cache = <&cl1_l3>; 253 }; 254 }; 255 256 cpu6: cpu@10200 { 257 compatible = "arm,cortex-a720ae"; 258 device_type = "cpu"; 259 reg = <0x00 0x10200>; 260 enable-method = "psci"; 261 262 clocks = <&scmi_dvfs 0>; 263 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 264 next-level-cache = <&cl1_l2_2>; 265 266 i-cache-line-size = <64>; 267 i-cache-sets = <256>; 268 i-cache-size = <0x10000>; 269 270 d-cache-line-size = <64>; 271 d-cache-sets = <256>; 272 d-cache-size = <0x10000>; 273 274 cl1_l2_2: l2-cache { 275 compatible = "cache"; 276 cache-level = <2>; 277 cache-line-size = <64>; 278 cache-sets = <0x400>; /* 8-way set */ 279 cache-size = <0x80000>; /* 512KB */ 280 cache-unified; 281 next-level-cache = <&cl1_l3>; 282 }; 283 }; 284 285 cpu7: cpu@10300 { 286 compatible = "arm,cortex-a720ae"; 287 device_type = "cpu"; 288 reg = <0x00 0x10300>; 289 enable-method = "psci"; 290 291 clocks = <&scmi_dvfs 0>; 292 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 293 next-level-cache = <&cl1_l2_3>; 294 295 i-cache-line-size = <64>; 296 i-cache-sets = <256>; 297 i-cache-size = <0x10000>; 298 299 d-cache-line-size = <64>; 300 d-cache-sets = <256>; 301 d-cache-size = <0x10000>; 302 303 cl1_l2_3: l2-cache { 304 compatible = "cache"; 305 cache-level = <2>; 306 cache-line-size = <64>; 307 cache-sets = <0x400>; /* 8-way set */ 308 cache-size = <0x80000>; /* 512KB */ 309 cache-unified; 310 next-level-cache = <&cl1_l3>; 311 }; 312 }; 313 314 cpu8: cpu@20000 { 315 compatible = "arm,cortex-a720ae"; 316 device_type = "cpu"; 317 reg = <0x00 0x20000>; 318 enable-method = "psci"; 319 320 clocks = <&scmi_dvfs 0>; 321 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 322 next-level-cache = <&cl2_l2_0>; 323 324 i-cache-line-size = <64>; 325 i-cache-sets = <256>; 326 i-cache-size = <0x10000>; 327 328 d-cache-line-size = <64>; 329 d-cache-sets = <256>; 330 d-cache-size = <0x10000>; 331 332 cl2_l2_0: l2-cache { 333 compatible = "cache"; 334 cache-level = <2>; 335 cache-line-size = <64>; 336 cache-sets = <0x400>; /* 8-way set */ 337 cache-size = <0x80000>; /* 512KB */ 338 cache-unified; 339 next-level-cache = <&cl2_l3>; 340 }; 341 }; 342 343 cpu9: cpu@20100 { 344 compatible = "arm,cortex-a720ae"; 345 device_type = "cpu"; 346 reg = <0x00 0x20100>; 347 enable-method = "psci"; 348 349 clocks = <&scmi_dvfs 0>; 350 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 351 next-level-cache = <&cl2_l2_1>; 352 353 i-cache-line-size = <64>; 354 i-cache-sets = <256>; 355 i-cache-size = <0x10000>; 356 357 d-cache-line-size = <64>; 358 d-cache-sets = <256>; 359 d-cache-size = <0x10000>; 360 361 cl2_l2_1: l2-cache { 362 compatible = "cache"; 363 cache-level = <2>; 364 cache-line-size = <64>; 365 cache-sets = <0x400>; /* 8-way set */ 366 cache-size = <0x80000>; /* 512KB */ 367 cache-unified; 368 next-level-cache = <&cl2_l3>; 369 }; 370 }; 371 372 cpu10: cpu@20200 { 373 compatible = "arm,cortex-a720ae"; 374 device_type = "cpu"; 375 reg = <0x00 0x20200>; 376 enable-method = "psci"; 377 378 clocks = <&scmi_dvfs 0>; 379 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 380 next-level-cache = <&cl2_l2_2>; 381 382 i-cache-line-size = <64>; 383 i-cache-sets = <256>; 384 i-cache-size = <0x10000>; 385 386 d-cache-line-size = <64>; 387 d-cache-sets = <256>; 388 d-cache-size = <0x10000>; 389 390 cl2_l2_2: l2-cache { 391 compatible = "cache"; 392 cache-level = <2>; 393 cache-line-size = <64>; 394 cache-sets = <0x400>; /* 8-way set */ 395 cache-size = <0x80000>; /* 512KB */ 396 cache-unified; 397 next-level-cache = <&cl2_l3>; 398 }; 399 }; 400 401 cpu11: cpu@20300 { 402 compatible = "arm,cortex-a720ae"; 403 device_type = "cpu"; 404 reg = <0x00 0x20300>; 405 enable-method = "psci"; 406 407 clocks = <&scmi_dvfs 0>; 408 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 409 next-level-cache = <&cl2_l2_3>; 410 411 i-cache-line-size = <64>; 412 i-cache-sets = <256>; 413 i-cache-size = <0x10000>; 414 415 d-cache-line-size = <64>; 416 d-cache-sets = <256>; 417 d-cache-size = <0x10000>; 418 419 cl2_l2_3: l2-cache { 420 compatible = "cache"; 421 cache-level = <2>; 422 cache-line-size = <64>; 423 cache-sets = <0x400>; /* 8-way set */ 424 cache-size = <0x80000>; /* 512KB */ 425 cache-unified; 426 next-level-cache = <&cl2_l3>; 427 }; 428 }; 429 430 cpu12: cpu@30000 { 431 compatible = "arm,cortex-a720ae"; 432 device_type = "cpu"; 433 reg = <0x00 0x30000>; 434 enable-method = "psci"; 435 436 clocks = <&scmi_dvfs 0>; 437 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 438 next-level-cache = <&cl3_l2_0>; 439 440 i-cache-line-size = <64>; 441 i-cache-sets = <256>; 442 i-cache-size = <0x10000>; 443 444 d-cache-line-size = <64>; 445 d-cache-sets = <256>; 446 d-cache-size = <0x10000>; 447 448 cl3_l2_0: l2-cache { 449 compatible = "cache"; 450 cache-level = <2>; 451 cache-line-size = <64>; 452 cache-sets = <0x400>; /* 8-way set */ 453 cache-size = <0x80000>; /* 512KB */ 454 cache-unified; 455 next-level-cache = <&cl3_l3>; 456 }; 457 }; 458 459 cpu13: cpu@30100 { 460 compatible = "arm,cortex-a720ae"; 461 device_type = "cpu"; 462 reg = <0x00 0x30100>; 463 enable-method = "psci"; 464 465 clocks = <&scmi_dvfs 0>; 466 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 467 next-level-cache = <&cl3_l2_1>; 468 469 i-cache-line-size = <64>; 470 i-cache-sets = <256>; 471 i-cache-size = <0x10000>; 472 473 d-cache-line-size = <64>; 474 d-cache-sets = <256>; 475 d-cache-size = <0x10000>; 476 477 cl3_l2_1: l2-cache { 478 compatible = "cache"; 479 cache-level = <2>; 480 cache-line-size = <64>; 481 cache-sets = <0x400>; /* 8-way set */ 482 cache-size = <0x80000>; /* 512KB */ 483 cache-unified; 484 next-level-cache = <&cl3_l3>; 485 }; 486 }; 487 488 cpu14: cpu@30200 { 489 compatible = "arm,cortex-a720ae"; 490 device_type = "cpu"; 491 reg = <0x00 0x30200>; 492 enable-method = "psci"; 493 494 clocks = <&scmi_dvfs 0>; 495 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 496 next-level-cache = <&cl3_l2_2>; 497 498 i-cache-line-size = <64>; 499 i-cache-sets = <256>; 500 i-cache-size = <0x10000>; 501 502 d-cache-line-size = <64>; 503 d-cache-sets = <256>; 504 d-cache-size = <0x10000>; 505 506 cl3_l2_2: l2-cache { 507 compatible = "cache"; 508 cache-level = <2>; 509 cache-line-size = <64>; 510 cache-sets = <0x400>; /* 8-way set */ 511 cache-size = <0x80000>; /* 512KB */ 512 cache-unified; 513 next-level-cache = <&cl3_l3>; 514 }; 515 }; 516 517 cpu15: cpu@30300 { 518 compatible = "arm,cortex-a720ae"; 519 device_type = "cpu"; 520 reg = <0x00 0x30300>; 521 enable-method = "psci"; 522 523 clocks = <&scmi_dvfs 0>; 524 cpu-idle-states = <&cpu_sleep &cluster_sleep>; 525 next-level-cache = <&cl3_l2_3>; 526 527 i-cache-line-size = <64>; 528 i-cache-sets = <256>; 529 i-cache-size = <0x10000>; 530 531 d-cache-line-size = <64>; 532 d-cache-sets = <256>; 533 d-cache-size = <0x10000>; 534 535 cl3_l2_3: l2-cache { 536 compatible = "cache"; 537 cache-level = <2>; 538 cache-line-size = <64>; 539 cache-sets = <0x400>; /* 8-way set */ 540 cache-size = <0x80000>; /* 512KB */ 541 cache-unified; 542 next-level-cache = <&cl3_l3>; 543 }; 544 }; 545 546 cl0_l3: l3-cache0 { 547 compatible = "cache"; 548 cache-level = <3>; 549 cache-line-size = <64>; 550 cache-sets = <0x1000>; /* 16-way set */ 551 cache-size = <0x400000>; /* 4MB */ 552 cache-unified; 553 }; 554 555 cl1_l3: l3-cache1 { 556 compatible = "cache"; 557 cache-level = <3>; 558 cache-line-size = <64>; 559 cache-sets = <0x1000>; /* 16-way set */ 560 cache-size = <0x400000>; /* 4MB */ 561 cache-unified; 562 }; 563 564 cl2_l3: l3-cache2 { 565 compatible = "cache"; 566 cache-level = <3>; 567 cache-line-size = <64>; 568 cache-sets = <0x1000>; /* 16-way set */ 569 cache-size = <0x400000>; /* 4MB */ 570 cache-unified; 571 }; 572 573 cl3_l3: l3-cache3 { 574 compatible = "cache"; 575 cache-level = <3>; 576 cache-line-size = <64>; 577 cache-sets = <0x1000>; /* 16-way set */ 578 cache-size = <0x400000>; /* 4MB */ 579 cache-unified; 580 }; 581 }; 582 583 firmware { 584 scmi { 585 compatible = "arm,scmi"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 589 mbox-names = "tx", "tx_reply", "rx"; 590 mboxes = <&mbox_db_tx 0 0 0>, 591 <&mbox_db_rx 0 0 0>, 592 <&mbox_db_rx 0 0 2>; 593 shmem = <&scmi_shmem_tx &scmi_shmem_rx>; 594 595 scmi_dvfs: protocol@13 { 596 reg = <0x13>; 597 #clock-cells = <1>; 598 }; 599 }; 600 }; 601 602 dsu-pmu-0 { 603 compatible = "arm,dsu-pmu"; 604 cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; 605 interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>; 606 }; 607 608 dsu-pmu-1 { 609 compatible = "arm,dsu-pmu"; 610 cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; 611 interrupts = <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>; 612 }; 613 614 dsu-pmu-2 { 615 compatible = "arm,dsu-pmu"; 616 cpus = <&cpu8 &cpu9 &cpu10 &cpu11>; 617 interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>; 618 }; 619 620 dsu-pmu-3 { 621 compatible = "arm,dsu-pmu"; 622 cpus = <&cpu12 &cpu13 &cpu14 &cpu15>; 623 interrupts = <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>; 624 }; 625 626 psci { 627 compatible = "arm,psci-1.0", "arm,psci-0.2"; 628 method = "smc"; 629 }; 630 631 soc: soc { 632 compatible = "simple-bus"; 633 #address-cells = <2>; 634 #size-cells = <2>; 635 ranges; 636 637 sram: sram@104000 { 638 compatible = "mmio-sram"; 639 reg = <0x0 0x00104000 0x0 0x00001000>; 640 #address-cells = <1>; 641 #size-cells = <1>; 642 ranges = <0 0x0 0x00104000 0x00001000>; 643 644 scmi_shmem_tx: scpshmem-sram-section@0 { 645 compatible = "arm,scmi-shmem"; 646 reg = <0x0 0x100>; 647 }; 648 649 scmi_shmem_rx: scpshmem-sram-section@100 { 650 compatible = "arm,scmi-shmem"; 651 reg = <0x100 0x100>; 652 }; 653 }; 654 655 timer@1a810000 { 656 compatible = "arm,armv7-timer-mem"; 657 reg = <0x0 0x1a810000 0x0 0x10000>; 658 #address-cells = <1>; 659 #size-cells = <1>; 660 661 /* 662 * Map child space [0x0..0x30000) to parent @ 0x1a810000 663 */ 664 ranges = <0x0 0x0 0x1a810000 0x00030000>; 665 666 frame@20000 { 667 reg = <0x20000 0x10000>; 668 frame-number = <0>; 669 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 670 }; 671 }; 672 673 gic: interrupt-controller@20800000 { 674 compatible = "arm,gic-v3"; 675 #interrupt-cells = <3>; 676 #address-cells = <2>; 677 #size-cells = <2>; 678 #redistributor-regions = <16>; 679 interrupt-controller; 680 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 681 ranges; 682 683 /* 684 * With GIC-A720AE multiview enabled, GICR_TYPER.Last is 685 * always reported as 1 on redistributor views other than 686 * view 0. This breaks discovery of a single contiguous 687 * GICR frame region, so each core is described with its own 688 * redistributor region. 689 */ 690 reg = <0x0 0x20800000 0x0 0x10000>, /* GICD */ 691 <0x0 0x20880000 0x0 0x40000>, /* 16 * GICR */ 692 <0x0 0x208c0000 0x0 0x40000>, 693 <0x0 0x20900000 0x0 0x40000>, 694 <0x0 0x20940000 0x0 0x40000>, 695 <0x0 0x20980000 0x0 0x40000>, 696 <0x0 0x209c0000 0x0 0x40000>, 697 <0x0 0x20a00000 0x0 0x40000>, 698 <0x0 0x20a40000 0x0 0x40000>, 699 <0x0 0x20a80000 0x0 0x40000>, 700 <0x0 0x20ac0000 0x0 0x40000>, 701 <0x0 0x20b00000 0x0 0x40000>, 702 <0x0 0x20b40000 0x0 0x40000>, 703 <0x0 0x20b80000 0x0 0x40000>, 704 <0x0 0x20bc0000 0x0 0x40000>, 705 <0x0 0x20c00000 0x0 0x40000>, 706 <0x0 0x20c40000 0x0 0x40000>; 707 708 its: msi-controller@20840000 { 709 compatible = "arm,gic-v3-its"; 710 reg = <0x0 0x20840000 0x0 0x40000>; 711 msi-controller; 712 #msi-cells = <1>; 713 }; 714 }; 715 716 /* 717 * UART is fixed at 24MHz, both UARTCLK and PCLK. 718 */ 719 soc_serial0: serial@1a400000 { 720 compatible = "arm,pl011", "arm,primecell"; 721 reg = <0x0 0x1a400000 0x0 0x10000>; 722 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&soc_clk24mhz>, <&soc_clk24mhz>; 724 clock-names = "uartclk", "apb_pclk"; 725 }; 726 727 watchdog@1a420000 { 728 compatible = "arm,sbsa-gwdt"; 729 reg = <0x0 0x1a420000 0x0 0x10000>, 730 <0x0 0x1a430000 0x0 0x10000>; 731 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 732 }; 733 734 rtc@300d0000 { 735 compatible = "arm,pl031", "arm,primecell"; 736 reg = <0x0 0x300d0000 0x0 0x10000>; 737 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&soc_clk24mhz>; 739 clock-names = "apb_pclk"; 740 }; 741 742 mbox_db_tx: mailbox@40020000 { 743 compatible = "arm,mhuv3"; 744 reg = <0x0 0x40020000 0x0 0x30000>; 745 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 746 interrupt-names = "combined"; 747 clocks = <&soc_clk24mhz>; 748 #mbox-cells = <3>; 749 }; 750 751 mbox_db_rx: mailbox@40060000 { 752 compatible = "arm,mhuv3"; 753 reg = <0x0 0x40060000 0x0 0x30000>; 754 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 755 interrupt-names = "combined"; 756 clocks = <&soc_clk24mhz>; 757 #mbox-cells = <3>; 758 }; 759 }; 760 761 timer { 762 compatible = "arm,armv8-timer"; 763 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 764 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 765 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 766 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 767 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 768 }; 769}; 770