1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (c) 2026, Arm Limited. All rights reserved. 4 * 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 9#include "corstone1000.dtsi" 10 11/ { 12 interrupt-parent = <&gic>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 cpus: cpus { 17 #address-cells = <2>; 18 #size-cells = <0>; 19 20 cpu: cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a320"; 23 reg = <0 0>; 24 enable-method = "psci"; 25 next-level-cache = <&L2_0>; 26 }; 27 28 cpu1: cpu@100 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a320"; 31 reg = <0 0x100>; 32 enable-method = "psci"; 33 next-level-cache = <&L2_0>; 34 }; 35 36 cpu2: cpu@200 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a320"; 39 reg = <0 0x200>; 40 enable-method = "psci"; 41 next-level-cache = <&L2_0>; 42 }; 43 44 cpu3: cpu@300 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a320"; 47 reg = <0 0x300>; 48 enable-method = "psci"; 49 next-level-cache = <&L2_0>; 50 }; 51 }; 52 53 timer { 54 compatible = "arm,armv8-timer"; 55 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 56 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 57 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 58 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 59 }; 60 61 sram: sram@2400000 { 62 compatible = "mmio-sram"; 63 reg = <0x02400000 0x200000>; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 ranges; 67 }; 68 69 gic: interrupt-controller@1c000000 { 70 compatible = "arm,gic-v3"; 71 #interrupt-cells = <3>; 72 #address-cells = <1>; 73 #size-cells = <1>; 74 interrupt-controller; 75 reg = <0x1c000000 0x10000>, 76 <0x1c040000 0x80000>; 77 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 78 }; 79 80 81 soc { 82 npu@1a050000 { 83 compatible = "arm,corstone1000-ethos-u85", "arm,ethos-u85"; 84 reg = <0x1a050000 0x1400>; 85 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 86 clocks = <&refclk100mhz>, <&refclk100mhz>; 87 clock-names = "core", "apb"; 88 sram = <&sram>; 89 }; 90 }; 91}; 92