1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T6032 "M3 Ultra" SoC 4 * 5 * Other names: H15J, "Palma 2C" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/spmi/spmi.h> 16 17#include "multi-die-cpp.h" 18 19#include "t6031-base.dtsi" 20 21/ { 22 compatible = "apple,t6032", "apple,arm-platform"; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu-map { 32 cluster3 { 33 core0 { 34 cpu = <&cpu_e10>; 35 }; 36 core1 { 37 cpu = <&cpu_e11>; 38 }; 39 core2 { 40 cpu = <&cpu_e12>; 41 }; 42 core3 { 43 cpu = <&cpu_e13>; 44 }; 45 }; 46 47 cluster4 { 48 core0 { 49 cpu = <&cpu_p20>; 50 }; 51 core1 { 52 cpu = <&cpu_p21>; 53 }; 54 core2 { 55 cpu = <&cpu_p22>; 56 }; 57 core3 { 58 cpu = <&cpu_p23>; 59 }; 60 core4 { 61 cpu = <&cpu_p24>; 62 }; 63 core5 { 64 cpu = <&cpu_p25>; 65 }; 66 }; 67 68 cluster5 { 69 core0 { 70 cpu = <&cpu_p30>; 71 }; 72 core1 { 73 cpu = <&cpu_p31>; 74 }; 75 core2 { 76 cpu = <&cpu_p32>; 77 }; 78 core3 { 79 cpu = <&cpu_p33>; 80 }; 81 core4 { 82 cpu = <&cpu_p34>; 83 }; 84 core5 { 85 cpu = <&cpu_p35>; 86 }; 87 }; 88 }; 89 90 cpu_e10: cpu@800 { 91 compatible = "apple,sawtooth"; 92 device_type = "cpu"; 93 reg = <0x0 0x800>; 94 enable-method = "spin-table"; 95 cpu-release-addr = <0 0>; /* to be filled by loader */ 96 next-level-cache = <&l2_cache_3>; 97 i-cache-size = <0x20000>; 98 d-cache-size = <0x10000>; 99 }; 100 101 cpu_e11: cpu@801 { 102 compatible = "apple,sawtooth"; 103 device_type = "cpu"; 104 reg = <0x0 0x801>; 105 enable-method = "spin-table"; 106 cpu-release-addr = <0 0>; /* to be filled by loader */ 107 next-level-cache = <&l2_cache_3>; 108 i-cache-size = <0x20000>; 109 d-cache-size = <0x10000>; 110 }; 111 112 cpu_e12: cpu@802 { 113 compatible = "apple,sawtooth"; 114 device_type = "cpu"; 115 reg = <0x0 0x802>; 116 enable-method = "spin-table"; 117 cpu-release-addr = <0 0>; /* to be filled by loader */ 118 next-level-cache = <&l2_cache_3>; 119 i-cache-size = <0x20000>; 120 d-cache-size = <0x10000>; 121 }; 122 123 cpu_e13: cpu@803 { 124 compatible = "apple,sawtooth"; 125 device_type = "cpu"; 126 reg = <0x0 0x803>; 127 enable-method = "spin-table"; 128 cpu-release-addr = <0 0>; /* to be filled by loader */ 129 next-level-cache = <&l2_cache_3>; 130 i-cache-size = <0x20000>; 131 d-cache-size = <0x10000>; 132 }; 133 134 cpu_p20: cpu@10900 { 135 compatible = "apple,everest"; 136 device_type = "cpu"; 137 reg = <0x0 0x10900>; 138 enable-method = "spin-table"; 139 cpu-release-addr = <0 0>; /* To be filled by loader */ 140 next-level-cache = <&l2_cache_4>; 141 i-cache-size = <0x30000>; 142 d-cache-size = <0x20000>; 143 }; 144 145 cpu_p21: cpu@10901 { 146 compatible = "apple,everest"; 147 device_type = "cpu"; 148 reg = <0x0 0x10901>; 149 enable-method = "spin-table"; 150 cpu-release-addr = <0 0>; /* To be filled by loader */ 151 next-level-cache = <&l2_cache_4>; 152 i-cache-size = <0x30000>; 153 d-cache-size = <0x20000>; 154 }; 155 156 cpu_p22: cpu@10902 { 157 compatible = "apple,everest"; 158 device_type = "cpu"; 159 reg = <0x0 0x10902>; 160 enable-method = "spin-table"; 161 cpu-release-addr = <0 0>; /* To be filled by loader */ 162 next-level-cache = <&l2_cache_4>; 163 i-cache-size = <0x30000>; 164 d-cache-size = <0x20000>; 165 }; 166 167 cpu_p23: cpu@10903 { 168 compatible = "apple,everest"; 169 device_type = "cpu"; 170 reg = <0x0 0x10903>; 171 enable-method = "spin-table"; 172 cpu-release-addr = <0 0>; /* To be filled by loader */ 173 next-level-cache = <&l2_cache_4>; 174 i-cache-size = <0x30000>; 175 d-cache-size = <0x20000>; 176 }; 177 178 cpu_p24: cpu@10904 { 179 compatible = "apple,everest"; 180 device_type = "cpu"; 181 reg = <0x0 0x10904>; 182 enable-method = "spin-table"; 183 cpu-release-addr = <0 0>; /* To be filled by loader */ 184 next-level-cache = <&l2_cache_4>; 185 i-cache-size = <0x30000>; 186 d-cache-size = <0x20000>; 187 }; 188 189 cpu_p25: cpu@10905 { 190 compatible = "apple,everest"; 191 device_type = "cpu"; 192 reg = <0x0 0x10905>; 193 enable-method = "spin-table"; 194 cpu-release-addr = <0 0>; /* To be filled by loader */ 195 next-level-cache = <&l2_cache_4>; 196 i-cache-size = <0x30000>; 197 d-cache-size = <0x20000>; 198 }; 199 200 cpu_p30: cpu@10a00 { 201 compatible = "apple,everest"; 202 device_type = "cpu"; 203 reg = <0x0 0x10a00>; 204 enable-method = "spin-table"; 205 cpu-release-addr = <0 0>; /* To be filled by loader */ 206 next-level-cache = <&l2_cache_5>; 207 i-cache-size = <0x30000>; 208 d-cache-size = <0x20000>; 209 }; 210 211 cpu_p31: cpu@10a01 { 212 compatible = "apple,everest"; 213 device_type = "cpu"; 214 reg = <0x0 0x10a01>; 215 enable-method = "spin-table"; 216 cpu-release-addr = <0 0>; /* To be filled by loader */ 217 next-level-cache = <&l2_cache_5>; 218 i-cache-size = <0x30000>; 219 d-cache-size = <0x20000>; 220 }; 221 222 cpu_p32: cpu@10a02 { 223 compatible = "apple,everest"; 224 device_type = "cpu"; 225 reg = <0x0 0x10a02>; 226 enable-method = "spin-table"; 227 cpu-release-addr = <0 0>; /* To be filled by loader */ 228 next-level-cache = <&l2_cache_5>; 229 i-cache-size = <0x30000>; 230 d-cache-size = <0x20000>; 231 }; 232 233 cpu_p33: cpu@10a03 { 234 compatible = "apple,everest"; 235 device_type = "cpu"; 236 reg = <0x0 0x10a03>; 237 enable-method = "spin-table"; 238 cpu-release-addr = <0 0>; /* To be filled by loader */ 239 next-level-cache = <&l2_cache_5>; 240 i-cache-size = <0x30000>; 241 d-cache-size = <0x20000>; 242 }; 243 244 cpu_p34: cpu@10a04 { 245 compatible = "apple,everest"; 246 device_type = "cpu"; 247 reg = <0x0 0x10a04>; 248 enable-method = "spin-table"; 249 cpu-release-addr = <0 0>; /* To be filled by loader */ 250 next-level-cache = <&l2_cache_5>; 251 i-cache-size = <0x30000>; 252 d-cache-size = <0x20000>; 253 }; 254 255 cpu_p35: cpu@10a05 { 256 compatible = "apple,everest"; 257 device_type = "cpu"; 258 reg = <0x0 0x10a05>; 259 enable-method = "spin-table"; 260 cpu-release-addr = <0 0>; /* To be filled by loader */ 261 next-level-cache = <&l2_cache_5>; 262 i-cache-size = <0x30000>; 263 d-cache-size = <0x20000>; 264 }; 265 266 l2_cache_3: l2-cache-3 { 267 compatible = "cache"; 268 cache-level = <2>; 269 cache-unified; 270 cache-size = <0x400000>; 271 }; 272 273 l2_cache_4: l2-cache-4 { 274 compatible = "cache"; 275 cache-level = <2>; 276 cache-unified; 277 cache-size = <0x1000000>; 278 }; 279 280 l2_cache_5: l2-cache-5 { 281 compatible = "cache"; 282 cache-level = <2>; 283 cache-unified; 284 cache-size = <0x1000000>; 285 }; 286 }; 287 288 die0: soc@200000000 { 289 compatible = "simple-bus"; 290 #address-cells = <2>; 291 #size-cells = <2>; 292 ranges = <0x02 0x00000000 0x02 0x00000000 0x4 0x00000000>, 293 <0x05 0x80000000 0x05 0x80000000 0x1 0x80000000>, 294 <0x07 0x00000000 0x07 0x00000000 0xf 0x80000000>, 295 <0x16 0x80000000 0x16 0x80000000 0x5 0x80000000>; 296 nonposted-mmio; 297 /* Required to get >32-bit DMA via DARTs */ 298 dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; 299 300 // filled via templated includes at the end of the file 301 }; 302 303 die1: soc@2200000000 { 304 compatible = "simple-bus"; 305 #address-cells = <2>; 306 #size-cells = <2>; 307 ranges = <0x02 0x00000000 0x22 0x00000000 0x4 0x00000000>, 308 <0x07 0x00000000 0x27 0x00000000 0xf 0x80000000>, 309 <0x16 0x80000000 0x36 0x80000000 0x5 0x80000000>; 310 nonposted-mmio; 311 /* Required to get >32-bit DMA via DARTs */ 312 dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; 313 314 // filled via templated includes at the end of the file 315 }; 316}; 317 318#define DIE 319#define DIE_NO 0 320 321&die0 { 322 #include "t6031-die0.dtsi" 323 #include "t6031-dieX.dtsi" 324}; 325 326#include "t6031-pmgr.dtsi" 327#include "t6031-gpio-pins.dtsi" 328 329#undef DIE 330#undef DIE_NO 331 332#define DIE _die1 333#define DIE_NO 1 334 335&die1 { 336 #include "t6031-dieX.dtsi" 337}; 338 339#include "t6031-pmgr.dtsi" 340 341/delete-node/ &ps_pmp_die1; 342 343#undef DIE 344#undef DIE_NO 345 346/* delete non-present DISP power-states */ 347/delete-node/ &ps_disp_cpu; 348/delete-node/ &ps_disp_cpu_die1; 349/delete-node/ &ps_disp_fe; 350/delete-node/ &ps_disp_fe_die1; 351/delete-node/ &ps_disp_sys; 352/delete-node/ &ps_disp_sys_die1; 353 354/* delete non-present ISP power-states */ 355/delete-node/ &ps_dprx; 356/delete-node/ &ps_dprx_die1; 357/delete-node/ &ps_isp_be; 358/delete-node/ &ps_isp_be_die1; 359/delete-node/ &ps_isp_clr; 360/delete-node/ &ps_isp_clr_die1; 361/delete-node/ &ps_isp_cpu; 362/delete-node/ &ps_isp_cpu_die1; 363/delete-node/ &ps_isp_fe; 364/delete-node/ &ps_isp_fe_die1; 365/delete-node/ &ps_isp_secure; 366/delete-node/ &ps_isp_secure_die1; 367/delete-node/ &ps_isp_sys; 368/delete-node/ &ps_isp_sys_die1; 369 370&ps_afi_d2d_0 { 371 status = "okay"; 372}; 373 374&ps_afi_d2d_0_die1 { 375 status = "okay"; 376}; 377 378&ps_afi_d2d_1 { 379 status = "okay"; 380}; 381 382&ps_afi_d2d_1_die1 { 383 status = "okay"; 384}; 385 386&ps_afc_d2d_0 { 387 status = "okay"; 388}; 389 390&ps_afc_d2d_0_die1{ 391 status = "okay"; 392}; 393 394&ps_afc_d2d_1 { 395 status = "okay"; 396}; 397 398&ps_afc_d2d_1_die1 { 399 status = "okay"; 400}; 401 402&ps_afr_d2d_0 { 403 status = "okay"; 404}; 405 406&ps_afr_d2d_0_die1 { 407 status = "okay"; 408}; 409 410&ps_afr_d2d_1 { 411 status = "okay"; 412}; 413 414&ps_afr_d2d_1_die1 { 415 status = "okay"; 416}; 417