1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T6030 "M3 Pro" SoC 4 * 5 * Other names: H15J, "Lobos" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/interrupt-controller/apple-aic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/pinctrl/apple.h> 13 14/ { 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu_e00>; 26 }; 27 core1 { 28 cpu = <&cpu_e01>; 29 }; 30 core2 { 31 cpu = <&cpu_e02>; 32 }; 33 core3 { 34 cpu = <&cpu_e03>; 35 }; 36 core4 { 37 cpu = <&cpu_e04>; 38 }; 39 core5 { 40 cpu = <&cpu_e05>; 41 }; 42 }; 43 44 cluster1 { 45 core0 { 46 cpu = <&cpu_p00>; 47 }; 48 core1 { 49 cpu = <&cpu_p01>; 50 }; 51 core2 { 52 cpu = <&cpu_p02>; 53 }; 54 core3 { 55 cpu = <&cpu_p03>; 56 }; 57 core4 { 58 cpu = <&cpu_p04>; 59 }; 60 core5 { 61 cpu = <&cpu_p05>; 62 }; 63 }; 64 }; 65 66 cpu_e00: cpu@0 { 67 compatible = "apple,sawtooth"; 68 device_type = "cpu"; 69 reg = <0x0 0x0>; 70 enable-method = "spin-table"; 71 cpu-release-addr = <0 0>; /* to be filled by loader */ 72 next-level-cache = <&l2_cache_0>; 73 i-cache-size = <0x20000>; 74 d-cache-size = <0x10000>; 75 }; 76 77 cpu_e01: cpu@1 { 78 compatible = "apple,sawtooth"; 79 device_type = "cpu"; 80 reg = <0x0 0x1>; 81 enable-method = "spin-table"; 82 cpu-release-addr = <0 0>; /* to be filled by loader */ 83 next-level-cache = <&l2_cache_0>; 84 i-cache-size = <0x20000>; 85 d-cache-size = <0x10000>; 86 }; 87 88 cpu_e02: cpu@2 { 89 compatible = "apple,sawtooth"; 90 device_type = "cpu"; 91 reg = <0x0 0x2>; 92 enable-method = "spin-table"; 93 cpu-release-addr = <0 0>; /* to be filled by loader */ 94 next-level-cache = <&l2_cache_0>; 95 i-cache-size = <0x20000>; 96 d-cache-size = <0x10000>; 97 }; 98 99 cpu_e03: cpu@3 { 100 compatible = "apple,sawtooth"; 101 device_type = "cpu"; 102 reg = <0x0 0x3>; 103 enable-method = "spin-table"; 104 cpu-release-addr = <0 0>; /* to be filled by loader */ 105 next-level-cache = <&l2_cache_0>; 106 i-cache-size = <0x20000>; 107 d-cache-size = <0x10000>; 108 }; 109 110 cpu_e04: cpu@4 { 111 compatible = "apple,sawtooth"; 112 device_type = "cpu"; 113 reg = <0x0 0x4>; 114 enable-method = "spin-table"; 115 cpu-release-addr = <0 0>; /* to be filled by loader */ 116 next-level-cache = <&l2_cache_0>; 117 i-cache-size = <0x20000>; 118 d-cache-size = <0x10000>; 119 }; 120 121 cpu_e05: cpu@5 { 122 compatible = "apple,sawtooth"; 123 device_type = "cpu"; 124 reg = <0x0 0x5>; 125 enable-method = "spin-table"; 126 cpu-release-addr = <0 0>; /* to be filled by loader */ 127 next-level-cache = <&l2_cache_0>; 128 i-cache-size = <0x20000>; 129 d-cache-size = <0x10000>; 130 }; 131 132 cpu_p00: cpu@10100 { 133 compatible = "apple,everest"; 134 device_type = "cpu"; 135 reg = <0x0 0x10100>; 136 enable-method = "spin-table"; 137 cpu-release-addr = <0 0>; /* To be filled by loader */ 138 next-level-cache = <&l2_cache_1>; 139 i-cache-size = <0x30000>; 140 d-cache-size = <0x20000>; 141 }; 142 143 cpu_p01: cpu@10101 { 144 compatible = "apple,everest"; 145 device_type = "cpu"; 146 reg = <0x0 0x10101>; 147 enable-method = "spin-table"; 148 cpu-release-addr = <0 0>; /* To be filled by loader */ 149 next-level-cache = <&l2_cache_1>; 150 i-cache-size = <0x30000>; 151 d-cache-size = <0x20000>; 152 }; 153 154 cpu_p02: cpu@10102 { 155 compatible = "apple,everest"; 156 device_type = "cpu"; 157 reg = <0x0 0x10102>; 158 enable-method = "spin-table"; 159 cpu-release-addr = <0 0>; /* To be filled by loader */ 160 next-level-cache = <&l2_cache_1>; 161 i-cache-size = <0x30000>; 162 d-cache-size = <0x20000>; 163 }; 164 165 cpu_p03: cpu@10103 { 166 compatible = "apple,everest"; 167 device_type = "cpu"; 168 reg = <0x0 0x10103>; 169 enable-method = "spin-table"; 170 cpu-release-addr = <0 0>; /* To be filled by loader */ 171 next-level-cache = <&l2_cache_1>; 172 i-cache-size = <0x30000>; 173 d-cache-size = <0x20000>; 174 }; 175 176 cpu_p04: cpu@10104 { 177 compatible = "apple,everest"; 178 device_type = "cpu"; 179 reg = <0x0 0x10104>; 180 enable-method = "spin-table"; 181 cpu-release-addr = <0 0>; /* To be filled by loader */ 182 next-level-cache = <&l2_cache_1>; 183 i-cache-size = <0x30000>; 184 d-cache-size = <0x20000>; 185 }; 186 187 cpu_p05: cpu@10105 { 188 compatible = "apple,everest"; 189 device_type = "cpu"; 190 reg = <0x0 0x10105>; 191 enable-method = "spin-table"; 192 cpu-release-addr = <0 0>; /* To be filled by loader */ 193 next-level-cache = <&l2_cache_1>; 194 i-cache-size = <0x30000>; 195 d-cache-size = <0x20000>; 196 }; 197 198 l2_cache_0: l2-cache-0 { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 cache-size = <0x400000>; 203 }; 204 205 l2_cache_1: l2-cache-1 { 206 compatible = "cache"; 207 cache-level = <2>; 208 cache-unified; 209 cache-size = <0x1000000>; 210 }; 211 }; 212 213 timer { 214 compatible = "arm,armv8-timer"; 215 interrupt-parent = <&aic>; 216 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 217 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 218 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 219 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 220 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 221 }; 222 223 clkref: clock-ref { 224 compatible = "fixed-clock"; 225 #clock-cells = <0>; 226 clock-frequency = <24000000>; 227 clock-output-names = "clkref"; 228 }; 229 230 reserved-memory { 231 #address-cells = <2>; 232 #size-cells = <2>; 233 ranges; 234 }; 235 236 soc: soc { 237 compatible = "simple-bus"; 238 #address-cells = <2>; 239 #size-cells = <2>; 240 241 ranges; 242 nonposted-mmio; 243 /* Required to get >32-bit DMA via DARTs */ 244 dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; 245 246 i2c1: i2c@289014000 { 247 compatible = "apple,t6030-i2c", "apple,t8103-i2c"; 248 reg = <0x2 0x89014000 0x0 0x4000>; 249 clocks = <&clkref>; 250 interrupt-parent = <&aic>; 251 interrupts = <AIC_IRQ 890 IRQ_TYPE_LEVEL_HIGH>; 252 pinctrl-0 = <&i2c1_pins>; 253 pinctrl-names = "default"; 254 #address-cells = <0x1>; 255 #size-cells = <0x0>; 256 power-domains = <&ps_i2c1>; 257 status = "disabled"; 258 }; 259 260 i2c2: i2c@289018000 { 261 compatible = "apple,t6030-i2c", "apple,t8103-i2c"; 262 reg = <0x2 0x89018000 0x0 0x4000>; 263 clocks = <&clkref>; 264 interrupt-parent = <&aic>; 265 interrupts = <AIC_IRQ 891 IRQ_TYPE_LEVEL_HIGH>; 266 pinctrl-0 = <&i2c2_pins>; 267 pinctrl-names = "default"; 268 #address-cells = <0x1>; 269 #size-cells = <0x0>; 270 power-domains = <&ps_i2c2>; 271 status = "disabled"; 272 }; 273 274 i2c3: i2c@28901c000 { 275 compatible = "apple,t6030-i2c", "apple,t8103-i2c"; 276 reg = <0x2 0x8901c000 0x0 0x4000>; 277 clocks = <&clkref>; 278 interrupt-parent = <&aic>; 279 interrupts = <AIC_IRQ 892 IRQ_TYPE_LEVEL_HIGH>; 280 pinctrl-0 = <&i2c3_pins>; 281 pinctrl-names = "default"; 282 #address-cells = <0x1>; 283 #size-cells = <0x0>; 284 power-domains = <&ps_i2c3>; 285 status = "disabled"; 286 }; 287 288 i2c4: i2c@289020000 { 289 compatible = "apple,t6030-i2c", "apple,t8103-i2c"; 290 reg = <0x2 0x89020000 0x0 0x4000>; 291 clocks = <&clkref>; 292 interrupt-parent = <&aic>; 293 interrupts = <AIC_IRQ 893 IRQ_TYPE_LEVEL_HIGH>; 294 pinctrl-0 = <&i2c4_pins>; 295 pinctrl-names = "default"; 296 #address-cells = <0x1>; 297 #size-cells = <0x0>; 298 power-domains = <&ps_i2c4>; 299 status = "disabled"; 300 }; 301 302 i2c6: i2c@289028000 { 303 compatible = "apple,t6030-i2c", "apple,t8103-i2c"; 304 reg = <0x2 0x89028000 0x0 0x4000>; 305 clocks = <&clkref>; 306 interrupt-parent = <&aic>; 307 interrupts = <AIC_IRQ 895 IRQ_TYPE_LEVEL_HIGH>; 308 pinctrl-0 = <&i2c6_pins>; 309 pinctrl-names = "default"; 310 #address-cells = <0x1>; 311 #size-cells = <0x0>; 312 power-domains = <&ps_i2c6>; 313 status = "disabled"; 314 }; 315 316 i2c8: i2c@289030000 { 317 compatible = "apple,t6030-i2c", "apple,t8103-i2c"; 318 reg = <0x2 0x89030000 0x0 0x4000>; 319 clocks = <&clkref>; 320 interrupt-parent = <&aic>; 321 interrupts = <AIC_IRQ 897 IRQ_TYPE_LEVEL_HIGH>; 322 pinctrl-0 = <&i2c8_pins>; 323 pinctrl-names = "default"; 324 #address-cells = <0x1>; 325 #size-cells = <0x0>; 326 power-domains = <&ps_i2c8>; 327 status = "disabled"; 328 }; 329 330 fpwm0: pwm@289040000 { 331 compatible = "apple,t6030-fpwm", "apple,s5l-fpwm"; 332 reg = <0x2 0x89040000 0x0 0x4000>; 333 power-domains = <&ps_fpwm0>; 334 clocks = <&clkref>; 335 #pwm-cells = <2>; 336 status = "disabled"; 337 }; 338 339 serial0: serial@289200000 { 340 compatible = "apple,s5l-uart"; 341 reg = <0x2 0x89200000 0x0 0x1000>; 342 reg-io-width = <4>; 343 interrupt-parent = <&aic>; 344 interrupts = <AIC_IRQ 866 IRQ_TYPE_LEVEL_HIGH>; 345 /* 346 * TODO: figure out the clocking properly, there may 347 * be a third selectable clock. 348 */ 349 clocks = <&clkref>, <&clkref>; 350 clock-names = "uart", "clk_uart_baud0"; 351 power-domains = <&ps_uart0>; 352 status = "disabled"; 353 }; 354 355 pmgr_gfx: power-management@290e80000 { 356 compatible = "apple,t6030-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; 357 #address-cells = <1>; 358 #size-cells = <1>; 359 360 reg = <0x2 0x90e80000 0 0x4000>; 361 /* child nodes are added in t6030-pmgr.dtsi */ 362 }; 363 364 pinctrl_ap: pinctrl@347100000 { 365 compatible = "apple,t6030-pinctrl", "apple,t8103-pinctrl"; 366 reg = <0x3 0x47100000 0x0 0x4000>; 367 368 interrupt-parent = <&aic>; 369 interrupts = <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, 370 <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>, 371 <AIC_IRQ 275 IRQ_TYPE_LEVEL_HIGH>, 372 <AIC_IRQ 276 IRQ_TYPE_LEVEL_HIGH>, 373 <AIC_IRQ 277 IRQ_TYPE_LEVEL_HIGH>, 374 <AIC_IRQ 278 IRQ_TYPE_LEVEL_HIGH>, 375 <AIC_IRQ 279 IRQ_TYPE_LEVEL_HIGH>; 376 377 power-domains = <&ps_gpio>; 378 379 gpio-controller; 380 #gpio-cells = <2>; 381 gpio-ranges = <&pinctrl_ap 0 0 224>; 382 apple,npins = <224>; 383 384 interrupt-controller; 385 #interrupt-cells = <2>; 386 387 i2c1_pins: i2c1-pins { 388 pinmux = <APPLE_PINMUX(37, 1)>, 389 <APPLE_PINMUX(36, 1)>; 390 }; 391 392 i2c2_pins: i2c2-pins { 393 pinmux = <APPLE_PINMUX(43, 1)>, 394 <APPLE_PINMUX(42, 1)>; 395 }; 396 397 i2c3_pins: i2c3-pins { 398 pinmux = <APPLE_PINMUX(41, 1)>, 399 <APPLE_PINMUX(40, 1)>; 400 }; 401 402 i2c4_pins: i2c4-pins { 403 pinmux = <APPLE_PINMUX(39, 1)>, 404 <APPLE_PINMUX(38, 1)>; 405 }; 406 407 i2c6_pins: i2c6-pins { 408 pinmux = <APPLE_PINMUX(47, 1)>, 409 <APPLE_PINMUX(46, 1)>; 410 }; 411 412 i2c8_pins: i2c8-pins { 413 pinmux = <APPLE_PINMUX(51, 1)>, 414 <APPLE_PINMUX(50, 1)>; 415 }; 416 }; 417 418 pmgr: power-management@350700000 { 419 compatible = "apple,t6030-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; 420 #address-cells = <1>; 421 #size-cells = <1>; 422 423 reg = <0x3 0x50700000 0 0x14000>; 424 /* child nodes are added in t6030-pmgr.dtsi */ 425 }; 426 427 aic: interrupt-controller@351000000 { 428 compatible = "apple,t6030-aic3", "apple,t8122-aic3"; 429 #interrupt-cells = <3>; 430 interrupt-controller; 431 432 reg = <0x3 0x51000000 0x0 0x184000>, 433 <0x3 0x51040000 0x0 0x4000>; 434 reg-names = "core", "event"; 435 power-domains = <&ps_aic>; 436 }; 437 438 pinctrl_nub: pinctrl@3641f0000 { 439 compatible = "apple,t6030-pinctrl", "apple,t8103-pinctrl"; 440 reg = <0x3 0x641f0000 0x0 0x4000>; 441 442 interrupt-parent = <&aic>; 443 interrupts = <AIC_IRQ 472 IRQ_TYPE_LEVEL_HIGH>, 444 <AIC_IRQ 473 IRQ_TYPE_LEVEL_HIGH>, 445 <AIC_IRQ 474 IRQ_TYPE_LEVEL_HIGH>, 446 <AIC_IRQ 475 IRQ_TYPE_LEVEL_HIGH>, 447 <AIC_IRQ 476 IRQ_TYPE_LEVEL_HIGH>, 448 <AIC_IRQ 477 IRQ_TYPE_LEVEL_HIGH>, 449 <AIC_IRQ 478 IRQ_TYPE_LEVEL_HIGH>; 450 451 gpio-controller; 452 #gpio-cells = <2>; 453 gpio-ranges = <&pinctrl_nub 0 0 37>; 454 apple,npins = <37>; 455 456 interrupt-controller; 457 #interrupt-cells = <2>; 458 }; 459 460 pmgr_mini: power-management@364280000 { 461 compatible = "apple,t6030-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; 462 #address-cells = <1>; 463 #size-cells = <1>; 464 465 reg = <0x3 0x64280000 0 0x4000>; 466 /* child nodes are added in t6030-pmgr.dtsi */ 467 }; 468 469 wdt: watchdog@3642b0000 { 470 compatible = "apple,t6030-wdt", "apple,t8103-wdt"; 471 reg = <0x3 0x642b0000 0x0 0x4000>; 472 clocks = <&clkref>; 473 interrupt-parent = <&aic>; 474 interrupts = <AIC_IRQ 480 IRQ_TYPE_LEVEL_HIGH>; 475 }; 476 477 pinctrl_smc: pinctrl@36c820000 { 478 compatible = "apple,t6030-pinctrl", "apple,t8103-pinctrl"; 479 reg = <0x3 0x6c820000 0x0 0x4000>; 480 481 gpio-controller; 482 #gpio-cells = <2>; 483 gpio-ranges = <&pinctrl_smc 0 0 18>; 484 apple,npins = <18>; 485 486 interrupt-controller; 487 #interrupt-cells = <2>; 488 interrupt-parent = <&aic>; 489 interrupts = <AIC_IRQ 545 IRQ_TYPE_LEVEL_HIGH>, 490 <AIC_IRQ 546 IRQ_TYPE_LEVEL_HIGH>, 491 <AIC_IRQ 547 IRQ_TYPE_LEVEL_HIGH>, 492 <AIC_IRQ 548 IRQ_TYPE_LEVEL_HIGH>, 493 <AIC_IRQ 549 IRQ_TYPE_LEVEL_HIGH>, 494 <AIC_IRQ 550 IRQ_TYPE_LEVEL_HIGH>, 495 <AIC_IRQ 551 IRQ_TYPE_LEVEL_HIGH>; 496 }; 497 498 pinctrl_aop: pinctrl@374824000 { 499 compatible = "apple,t6030-pinctrl", "apple,t8103-pinctrl"; 500 reg = <0x3 0x74824000 0x0 0x4000>; 501 502 interrupt-parent = <&aic>; 503 interrupts = <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, 504 <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, 505 <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, 506 <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>, 507 <AIC_IRQ 398 IRQ_TYPE_LEVEL_HIGH>, 508 <AIC_IRQ 399 IRQ_TYPE_LEVEL_HIGH>, 509 <AIC_IRQ 400 IRQ_TYPE_LEVEL_HIGH>; 510 511 clocks = <&clkref>; 512 513 gpio-controller; 514 #gpio-cells = <2>; 515 gpio-ranges = <&pinctrl_aop 0 0 54>; 516 apple,npins = <54>; 517 518 interrupt-controller; 519 #interrupt-cells = <2>; 520 }; 521 }; 522}; 523 524#include "t6030-pmgr.dtsi" 525