1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T6022 "M2 Ultra" SoC 4 * 5 * Other names: H14J, "Rhodes 2C" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/spmi/spmi.h> 16 17#include "multi-die-cpp.h" 18 19#include "t602x-common.dtsi" 20 21/ { 22 compatible = "apple,t6022", "apple,arm-platform"; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 cpus { 28 cpu-map { 29 cluster3 { 30 core0 { 31 cpu = <&cpu_e10>; 32 }; 33 core1 { 34 cpu = <&cpu_e11>; 35 }; 36 core2 { 37 cpu = <&cpu_e12>; 38 }; 39 core3 { 40 cpu = <&cpu_e13>; 41 }; 42 }; 43 44 cluster4 { 45 core0 { 46 cpu = <&cpu_p20>; 47 }; 48 core1 { 49 cpu = <&cpu_p21>; 50 }; 51 core2 { 52 cpu = <&cpu_p22>; 53 }; 54 core3 { 55 cpu = <&cpu_p23>; 56 }; 57 }; 58 59 cluster5 { 60 core0 { 61 cpu = <&cpu_p30>; 62 }; 63 core1 { 64 cpu = <&cpu_p31>; 65 }; 66 core2 { 67 cpu = <&cpu_p32>; 68 }; 69 core3 { 70 cpu = <&cpu_p33>; 71 }; 72 }; 73 }; 74 75 cpu_e10: cpu@800 { 76 compatible = "apple,blizzard"; 77 device_type = "cpu"; 78 reg = <0x0 0x800>; 79 enable-method = "spin-table"; 80 cpu-release-addr = <0 0>; /* to be filled by loader */ 81 next-level-cache = <&l2_cache_3>; 82 i-cache-size = <0x20000>; 83 d-cache-size = <0x10000>; 84 operating-points-v2 = <&blizzard_opp>; 85 capacity-dmips-mhz = <756>; 86 performance-domains = <&cpufreq_e_die1>; 87 }; 88 89 cpu_e11: cpu@801 { 90 compatible = "apple,blizzard"; 91 device_type = "cpu"; 92 reg = <0x0 0x801>; 93 enable-method = "spin-table"; 94 cpu-release-addr = <0 0>; /* to be filled by loader */ 95 next-level-cache = <&l2_cache_3>; 96 i-cache-size = <0x20000>; 97 d-cache-size = <0x10000>; 98 operating-points-v2 = <&blizzard_opp>; 99 capacity-dmips-mhz = <756>; 100 performance-domains = <&cpufreq_e_die1>; 101 }; 102 103 cpu_e12: cpu@802 { 104 compatible = "apple,blizzard"; 105 device_type = "cpu"; 106 reg = <0x0 0x802>; 107 enable-method = "spin-table"; 108 cpu-release-addr = <0 0>; /* to be filled by loader */ 109 next-level-cache = <&l2_cache_3>; 110 i-cache-size = <0x20000>; 111 d-cache-size = <0x10000>; 112 operating-points-v2 = <&blizzard_opp>; 113 capacity-dmips-mhz = <756>; 114 performance-domains = <&cpufreq_e_die1>; 115 }; 116 117 cpu_e13: cpu@803 { 118 compatible = "apple,blizzard"; 119 device_type = "cpu"; 120 reg = <0x0 0x803>; 121 enable-method = "spin-table"; 122 cpu-release-addr = <0 0>; /* to be filled by loader */ 123 next-level-cache = <&l2_cache_3>; 124 i-cache-size = <0x20000>; 125 d-cache-size = <0x10000>; 126 operating-points-v2 = <&blizzard_opp>; 127 capacity-dmips-mhz = <756>; 128 performance-domains = <&cpufreq_e_die1>; 129 }; 130 131 cpu_p20: cpu@10900 { 132 compatible = "apple,avalanche"; 133 device_type = "cpu"; 134 reg = <0x0 0x10900>; 135 enable-method = "spin-table"; 136 cpu-release-addr = <0 0>; /* To be filled by loader */ 137 next-level-cache = <&l2_cache_4>; 138 i-cache-size = <0x30000>; 139 d-cache-size = <0x20000>; 140 operating-points-v2 = <&avalanche_opp>; 141 capacity-dmips-mhz = <1024>; 142 performance-domains = <&cpufreq_p0_die1>; 143 }; 144 145 cpu_p21: cpu@10901 { 146 compatible = "apple,avalanche"; 147 device_type = "cpu"; 148 reg = <0x0 0x10901>; 149 enable-method = "spin-table"; 150 cpu-release-addr = <0 0>; /* To be filled by loader */ 151 next-level-cache = <&l2_cache_4>; 152 i-cache-size = <0x30000>; 153 d-cache-size = <0x20000>; 154 operating-points-v2 = <&avalanche_opp>; 155 capacity-dmips-mhz = <1024>; 156 performance-domains = <&cpufreq_p0_die1>; 157 }; 158 159 cpu_p22: cpu@10902 { 160 compatible = "apple,avalanche"; 161 device_type = "cpu"; 162 reg = <0x0 0x10902>; 163 enable-method = "spin-table"; 164 cpu-release-addr = <0 0>; /* To be filled by loader */ 165 next-level-cache = <&l2_cache_4>; 166 i-cache-size = <0x30000>; 167 d-cache-size = <0x20000>; 168 operating-points-v2 = <&avalanche_opp>; 169 capacity-dmips-mhz = <1024>; 170 performance-domains = <&cpufreq_p0_die1>; 171 }; 172 173 cpu_p23: cpu@10903 { 174 compatible = "apple,avalanche"; 175 device_type = "cpu"; 176 reg = <0x0 0x10903>; 177 enable-method = "spin-table"; 178 cpu-release-addr = <0 0>; /* To be filled by loader */ 179 next-level-cache = <&l2_cache_4>; 180 i-cache-size = <0x30000>; 181 d-cache-size = <0x20000>; 182 operating-points-v2 = <&avalanche_opp>; 183 capacity-dmips-mhz = <1024>; 184 performance-domains = <&cpufreq_p0_die1>; 185 }; 186 187 cpu_p30: cpu@10a00 { 188 compatible = "apple,avalanche"; 189 device_type = "cpu"; 190 reg = <0x0 0x10a00>; 191 enable-method = "spin-table"; 192 cpu-release-addr = <0 0>; /* To be filled by loader */ 193 next-level-cache = <&l2_cache_5>; 194 i-cache-size = <0x30000>; 195 d-cache-size = <0x20000>; 196 operating-points-v2 = <&avalanche_opp>; 197 capacity-dmips-mhz = <1024>; 198 performance-domains = <&cpufreq_p1_die1>; 199 }; 200 201 cpu_p31: cpu@10a01 { 202 compatible = "apple,avalanche"; 203 device_type = "cpu"; 204 reg = <0x0 0x10a01>; 205 enable-method = "spin-table"; 206 cpu-release-addr = <0 0>; /* To be filled by loader */ 207 next-level-cache = <&l2_cache_5>; 208 i-cache-size = <0x30000>; 209 d-cache-size = <0x20000>; 210 operating-points-v2 = <&avalanche_opp>; 211 capacity-dmips-mhz = <1024>; 212 performance-domains = <&cpufreq_p1_die1>; 213 }; 214 215 cpu_p32: cpu@10a02 { 216 compatible = "apple,avalanche"; 217 device_type = "cpu"; 218 reg = <0x0 0x10a02>; 219 enable-method = "spin-table"; 220 cpu-release-addr = <0 0>; /* To be filled by loader */ 221 next-level-cache = <&l2_cache_5>; 222 i-cache-size = <0x30000>; 223 d-cache-size = <0x20000>; 224 operating-points-v2 = <&avalanche_opp>; 225 capacity-dmips-mhz = <1024>; 226 performance-domains = <&cpufreq_p1_die1>; 227 }; 228 229 cpu_p33: cpu@10a03 { 230 compatible = "apple,avalanche"; 231 device_type = "cpu"; 232 reg = <0x0 0x10a03>; 233 enable-method = "spin-table"; 234 cpu-release-addr = <0 0>; /* To be filled by loader */ 235 next-level-cache = <&l2_cache_5>; 236 i-cache-size = <0x30000>; 237 d-cache-size = <0x20000>; 238 operating-points-v2 = <&avalanche_opp>; 239 capacity-dmips-mhz = <1024>; 240 performance-domains = <&cpufreq_p1_die1>; 241 }; 242 243 l2_cache_3: l2-cache-3 { 244 compatible = "cache"; 245 cache-level = <2>; 246 cache-unified; 247 cache-size = <0x400000>; 248 }; 249 250 l2_cache_4: l2-cache-4 { 251 compatible = "cache"; 252 cache-level = <2>; 253 cache-unified; 254 cache-size = <0x1000000>; 255 }; 256 257 l2_cache_5: l2-cache-5 { 258 compatible = "cache"; 259 cache-level = <2>; 260 cache-unified; 261 cache-size = <0x1000000>; 262 }; 263 }; 264 265 die0: soc@200000000 { 266 compatible = "simple-bus"; 267 #address-cells = <2>; 268 #size-cells = <2>; 269 ranges = <0x02 0x00000000 0x02 0x00000000 0x4 0x00000000>, 270 <0x05 0x80000000 0x05 0x80000000 0x1 0x80000000>, 271 <0x07 0x00000000 0x07 0x00000000 0xf 0x80000000>, 272 <0x16 0x80000000 0x16 0x80000000 0x5 0x80000000>; 273 nonposted-mmio; 274 /* Required to get >32-bit DMA via DARTs */ 275 dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; 276 277 // filled via templated includes at the end of the file 278 }; 279 280 die1: soc@2200000000 { 281 compatible = "simple-bus"; 282 #address-cells = <2>; 283 #size-cells = <2>; 284 ranges = <0x02 0x00000000 0x22 0x00000000 0x4 0x00000000>, 285 <0x07 0x00000000 0x27 0x00000000 0xf 0x80000000>, 286 <0x16 0x80000000 0x36 0x80000000 0x5 0x80000000>; 287 nonposted-mmio; 288 /* Required to get >32-bit DMA via DARTs */ 289 dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; 290 291 // filled via templated includes at the end of the file 292 }; 293}; 294 295#define DIE 296#define DIE_NO 0 297 298&die0 { 299 #include "t602x-die0.dtsi" 300 #include "t602x-dieX.dtsi" 301}; 302 303#include "t602x-pmgr.dtsi" 304#include "t602x-gpio-pins.dtsi" 305 306#undef DIE 307#undef DIE_NO 308 309#define DIE _die1 310#define DIE_NO 1 311 312&die1 { 313 #include "t602x-dieX.dtsi" 314 #include "t602x-nvme.dtsi" 315}; 316 317#include "t602x-pmgr.dtsi" 318 319/delete-node/ &ps_pmp_die1; 320 321#undef DIE 322#undef DIE_NO 323 324&aic { 325 affinities { 326 e-core-pmu-affinity { 327 apple,fiq-index = <AIC_CPU_PMU_E>; 328 cpus = <&cpu_e00 &cpu_e01 &cpu_e02 &cpu_e03 329 &cpu_e10 &cpu_e11 &cpu_e12 &cpu_e13>; 330 }; 331 332 p-core-pmu-affinity { 333 apple,fiq-index = <AIC_CPU_PMU_P>; 334 cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03 335 &cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13 336 &cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23 337 &cpu_p30 &cpu_p31 &cpu_p32 &cpu_p33>; 338 }; 339 }; 340}; 341 342&ps_gfx { 343 // On t6022, the die0 GPU power domain needs both AFR power domains 344 power-domains = <&ps_afr>, <&ps_afr_die1>; 345}; 346 347&gpu { 348 compatible = "apple,agx-g14d", "apple,agx-g14s"; 349}; 350