1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/axg-aoclkc.h> 7#include <dt-bindings/clock/axg-audio-clkc.h> 8#include <dt-bindings/clock/axg-clkc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/meson-axg-gpio.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 15#include <dt-bindings/power/meson-axg-power.h> 16 17/ { 18 compatible = "amlogic,meson-axg"; 19 20 interrupt-parent = <&gic>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 tdmif_a: audio-controller-0 { 25 compatible = "amlogic,axg-tdm-iface"; 26 #sound-dai-cells = <0>; 27 sound-name-prefix = "TDM_A"; 28 clocks = <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>, 30 <&clkc_audio AUD_CLKID_MST_A_MCLK>; 31 clock-names = "sclk", "lrclk", "mclk"; 32 status = "disabled"; 33 }; 34 35 tdmif_b: audio-controller-1 { 36 compatible = "amlogic,axg-tdm-iface"; 37 #sound-dai-cells = <0>; 38 sound-name-prefix = "TDM_B"; 39 clocks = <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>, 41 <&clkc_audio AUD_CLKID_MST_B_MCLK>; 42 clock-names = "sclk", "lrclk", "mclk"; 43 status = "disabled"; 44 }; 45 46 tdmif_c: audio-controller-2 { 47 compatible = "amlogic,axg-tdm-iface"; 48 #sound-dai-cells = <0>; 49 sound-name-prefix = "TDM_C"; 50 clocks = <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>, 52 <&clkc_audio AUD_CLKID_MST_C_MCLK>; 53 clock-names = "sclk", "lrclk", "mclk"; 54 status = "disabled"; 55 }; 56 57 arm-pmu { 58 compatible = "arm,cortex-a53-pmu"; 59 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 63 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 64 }; 65 66 cpus { 67 #address-cells = <0x2>; 68 #size-cells = <0x0>; 69 70 cpu0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x0 0x0>; 74 enable-method = "psci"; 75 next-level-cache = <&l2>; 76 clocks = <&scpi_dvfs 0>; 77 dynamic-power-coefficient = <140>; 78 #cooling-cells = <2>; 79 }; 80 81 cpu1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x1>; 85 enable-method = "psci"; 86 d-cache-line-size = <32>; 87 d-cache-size = <0x8000>; 88 d-cache-sets = <32>; 89 i-cache-line-size = <32>; 90 i-cache-size = <0x8000>; 91 i-cache-sets = <32>; 92 next-level-cache = <&l2>; 93 clocks = <&scpi_dvfs 0>; 94 dynamic-power-coefficient = <140>; 95 #cooling-cells = <2>; 96 }; 97 98 cpu2: cpu@2 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a53"; 101 reg = <0x0 0x2>; 102 enable-method = "psci"; 103 d-cache-line-size = <32>; 104 d-cache-size = <0x8000>; 105 d-cache-sets = <32>; 106 i-cache-line-size = <32>; 107 i-cache-size = <0x8000>; 108 i-cache-sets = <32>; 109 next-level-cache = <&l2>; 110 clocks = <&scpi_dvfs 0>; 111 dynamic-power-coefficient = <140>; 112 #cooling-cells = <2>; 113 }; 114 115 cpu3: cpu@3 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a53"; 118 reg = <0x0 0x3>; 119 enable-method = "psci"; 120 d-cache-line-size = <32>; 121 d-cache-size = <0x8000>; 122 d-cache-sets = <32>; 123 i-cache-line-size = <32>; 124 i-cache-size = <0x8000>; 125 i-cache-sets = <32>; 126 next-level-cache = <&l2>; 127 clocks = <&scpi_dvfs 0>; 128 dynamic-power-coefficient = <140>; 129 #cooling-cells = <2>; 130 }; 131 132 l2: l2-cache0 { 133 compatible = "cache"; 134 cache-level = <2>; 135 cache-unified; 136 cache-size = <0x80000>; /* L2. 512 KB */ 137 cache-line-size = <64>; 138 cache-sets = <512>; 139 }; 140 }; 141 142 sm: secure-monitor { 143 compatible = "amlogic,meson-gxbb-sm"; 144 }; 145 146 efuse: efuse { 147 compatible = "amlogic,meson-gxbb-efuse"; 148 clocks = <&clkc CLKID_EFUSE>; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 read-only; 152 secure-monitor = <&sm>; 153 }; 154 155 psci { 156 compatible = "arm,psci-1.0"; 157 method = "smc"; 158 }; 159 160 reserved-memory { 161 #address-cells = <2>; 162 #size-cells = <2>; 163 ranges; 164 165 /* 16 MiB reserved for Hardware ROM Firmware */ 166 hwrom_reserved: hwrom@0 { 167 reg = <0x0 0x0 0x0 0x1000000>; 168 no-map; 169 }; 170 171 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 172 secmon_reserved: secmon@5000000 { 173 reg = <0x0 0x05000000 0x0 0x300000>; 174 no-map; 175 }; 176 }; 177 178 scpi { 179 compatible = "arm,scpi-pre-1.0"; 180 mboxes = <&mailbox 1 &mailbox 2>; 181 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 182 183 scpi_clocks: clocks { 184 compatible = "arm,scpi-clocks"; 185 186 scpi_dvfs: clocks-0 { 187 compatible = "arm,scpi-dvfs-clocks"; 188 #clock-cells = <1>; 189 clock-indices = <0>; 190 clock-output-names = "vcpu"; 191 }; 192 }; 193 194 scpi_sensors: sensors { 195 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; 196 #thermal-sensor-cells = <1>; 197 }; 198 }; 199 200 soc { 201 compatible = "simple-bus"; 202 #address-cells = <2>; 203 #size-cells = <2>; 204 ranges; 205 206 pcieA: pcie@f9800000 { 207 compatible = "amlogic,axg-pcie", "snps,dw-pcie"; 208 reg = <0x0 0xf9800000 0x0 0x400000>, 209 <0x0 0xff646000 0x0 0x2000>, 210 <0x0 0xf9f00000 0x0 0x100000>; 211 reg-names = "elbi", "cfg", "config"; 212 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; 213 #interrupt-cells = <1>; 214 interrupt-map-mask = <0 0 0 0>; 215 interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 216 bus-range = <0x0 0xff>; 217 #address-cells = <3>; 218 #size-cells = <2>; 219 device_type = "pci"; 220 ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>; 221 222 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>; 223 clock-names = "general", "pclk", "port"; 224 resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>; 225 reset-names = "port", "apb"; 226 num-lanes = <1>; 227 phys = <&pcie_phy>; 228 phy-names = "pcie"; 229 status = "disabled"; 230 }; 231 232 pcieB: pcie@fa000000 { 233 compatible = "amlogic,axg-pcie", "snps,dw-pcie"; 234 reg = <0x0 0xfa000000 0x0 0x400000>, 235 <0x0 0xff648000 0x0 0x2000>, 236 <0x0 0xfa400000 0x0 0x100000>; 237 reg-names = "elbi", "cfg", "config"; 238 interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>; 239 #interrupt-cells = <1>; 240 interrupt-map-mask = <0 0 0 0>; 241 interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; 242 bus-range = <0x0 0xff>; 243 #address-cells = <3>; 244 #size-cells = <2>; 245 device_type = "pci"; 246 ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>; 247 248 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>; 249 clock-names = "general", "pclk", "port"; 250 resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>; 251 reset-names = "port", "apb"; 252 num-lanes = <1>; 253 phys = <&pcie_phy>; 254 phy-names = "pcie"; 255 status = "disabled"; 256 }; 257 258 usb: usb@ffe09080 { 259 compatible = "amlogic,meson-axg-usb-ctrl"; 260 reg = <0x0 0xffe09080 0x0 0x20>; 261 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 262 #address-cells = <2>; 263 #size-cells = <2>; 264 ranges; 265 266 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; 267 clock-names = "usb_ctrl", "ddr"; 268 resets = <&reset RESET_USB_OTG>; 269 270 dr_mode = "otg"; 271 272 phys = <&usb2_phy1>; 273 phy-names = "usb2-phy1"; 274 275 dwc2: usb@ff400000 { 276 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 277 reg = <0x0 0xff400000 0x0 0x40000>; 278 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&clkc CLKID_USB1>; 280 clock-names = "otg"; 281 phys = <&usb2_phy1>; 282 dr_mode = "peripheral"; 283 g-rx-fifo-size = <192>; 284 g-np-tx-fifo-size = <128>; 285 g-tx-fifo-size = <128 128 16 16 16>; 286 }; 287 288 dwc3: usb@ff500000 { 289 compatible = "snps,dwc3"; 290 reg = <0x0 0xff500000 0x0 0x100000>; 291 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 292 dr_mode = "host"; 293 maximum-speed = "high-speed"; 294 snps,dis_u2_susphy_quirk; 295 }; 296 }; 297 298 ethmac: ethernet@ff3f0000 { 299 compatible = "amlogic,meson-axg-dwmac", 300 "snps,dwmac-3.70a", 301 "snps,dwmac"; 302 reg = <0x0 0xff3f0000 0x0 0x10000>, 303 <0x0 0xff634540 0x0 0x8>; 304 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 305 interrupt-names = "macirq"; 306 clocks = <&clkc CLKID_ETH>, 307 <&clkc CLKID_FCLK_DIV2>, 308 <&clkc CLKID_MPLL2>, 309 <&clkc CLKID_FCLK_DIV2>; 310 clock-names = "stmmaceth", "clkin0", "clkin1", 311 "timing-adjustment"; 312 rx-fifo-depth = <4096>; 313 tx-fifo-depth = <2048>; 314 power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>; 315 status = "disabled"; 316 }; 317 318 pcie_phy: phy@ff644000 { 319 compatible = "amlogic,axg-pcie-phy"; 320 reg = <0x0 0xff644000 0x0 0x1c>; 321 resets = <&reset RESET_PCIE_PHY>; 322 phys = <&mipi_pcie_analog_dphy>; 323 phy-names = "analog"; 324 #phy-cells = <0>; 325 }; 326 327 pdm: audio-controller@ff632000 { 328 compatible = "amlogic,axg-pdm"; 329 reg = <0x0 0xff632000 0x0 0x34>; 330 #sound-dai-cells = <0>; 331 sound-name-prefix = "PDM"; 332 clocks = <&clkc_audio AUD_CLKID_PDM>, 333 <&clkc_audio AUD_CLKID_PDM_DCLK>, 334 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 335 clock-names = "pclk", "dclk", "sysclk"; 336 status = "disabled"; 337 }; 338 339 periphs: bus@ff634000 { 340 compatible = "simple-bus"; 341 reg = <0x0 0xff634000 0x0 0x2000>; 342 #address-cells = <2>; 343 #size-cells = <2>; 344 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 345 346 hwrng: rng@18 { 347 compatible = "amlogic,meson-rng"; 348 reg = <0x0 0x18 0x0 0x4>; 349 clocks = <&clkc CLKID_RNG0>; 350 clock-names = "core"; 351 }; 352 353 pinctrl_periphs: pinctrl@480 { 354 compatible = "amlogic,meson-axg-periphs-pinctrl"; 355 #address-cells = <2>; 356 #size-cells = <2>; 357 ranges; 358 359 gpio: bank@480 { 360 reg = <0x0 0x00480 0x0 0x40>, 361 <0x0 0x004e8 0x0 0x14>, 362 <0x0 0x00520 0x0 0x14>, 363 <0x0 0x00430 0x0 0x3c>; 364 reg-names = "mux", "pull", "pull-enable", "gpio"; 365 gpio-controller; 366 #gpio-cells = <2>; 367 gpio-ranges = <&pinctrl_periphs 0 0 86>; 368 }; 369 370 i2c0_pins: i2c0 { 371 mux { 372 groups = "i2c0_sck", 373 "i2c0_sda"; 374 function = "i2c0"; 375 bias-disable; 376 }; 377 }; 378 379 i2c1_x_pins: i2c1_x { 380 mux { 381 groups = "i2c1_sck_x", 382 "i2c1_sda_x"; 383 function = "i2c1"; 384 bias-disable; 385 }; 386 }; 387 388 i2c1_z_pins: i2c1_z { 389 mux { 390 groups = "i2c1_sck_z", 391 "i2c1_sda_z"; 392 function = "i2c1"; 393 bias-disable; 394 }; 395 }; 396 397 i2c2_a_pins: i2c2_a { 398 mux { 399 groups = "i2c2_sck_a", 400 "i2c2_sda_a"; 401 function = "i2c2"; 402 bias-disable; 403 }; 404 }; 405 406 i2c2_x_pins: i2c2_x { 407 mux { 408 groups = "i2c2_sck_x", 409 "i2c2_sda_x"; 410 function = "i2c2"; 411 bias-disable; 412 }; 413 }; 414 415 i2c3_a6_pins: i2c3_a6 { 416 mux { 417 groups = "i2c3_sda_a6", 418 "i2c3_sck_a7"; 419 function = "i2c3"; 420 bias-disable; 421 }; 422 }; 423 424 i2c3_a12_pins: i2c3_a12 { 425 mux { 426 groups = "i2c3_sda_a12", 427 "i2c3_sck_a13"; 428 function = "i2c3"; 429 bias-disable; 430 }; 431 }; 432 433 i2c3_a19_pins: i2c3_a19 { 434 mux { 435 groups = "i2c3_sda_a19", 436 "i2c3_sck_a20"; 437 function = "i2c3"; 438 bias-disable; 439 }; 440 }; 441 442 emmc_pins: emmc { 443 mux-0 { 444 groups = "emmc_nand_d0", 445 "emmc_nand_d1", 446 "emmc_nand_d2", 447 "emmc_nand_d3", 448 "emmc_nand_d4", 449 "emmc_nand_d5", 450 "emmc_nand_d6", 451 "emmc_nand_d7", 452 "emmc_cmd"; 453 function = "emmc"; 454 bias-pull-up; 455 }; 456 457 mux-1 { 458 groups = "emmc_clk"; 459 function = "emmc"; 460 bias-disable; 461 }; 462 }; 463 464 nand_all_pins: nand-all-pins { 465 mux { 466 groups = "emmc_nand_d0", 467 "emmc_nand_d1", 468 "emmc_nand_d2", 469 "emmc_nand_d3", 470 "emmc_nand_d4", 471 "emmc_nand_d5", 472 "emmc_nand_d6", 473 "emmc_nand_d7", 474 "nand_ce0", 475 "nand_ale", 476 "nand_cle", 477 "nand_wen_clk", 478 "nand_ren_wr"; 479 function = "nand"; 480 input-enable; 481 bias-pull-up; 482 }; 483 }; 484 485 emmc_ds_pins: emmc_ds { 486 mux { 487 groups = "emmc_ds"; 488 function = "emmc"; 489 bias-pull-down; 490 }; 491 }; 492 493 emmc_clk_gate_pins: emmc_clk_gate { 494 mux { 495 groups = "BOOT_8"; 496 function = "gpio_periphs"; 497 bias-pull-down; 498 }; 499 }; 500 501 eth_rgmii_x_pins: eth-x-rgmii { 502 mux { 503 groups = "eth_mdio_x", 504 "eth_mdc_x", 505 "eth_rgmii_rx_clk_x", 506 "eth_rx_dv_x", 507 "eth_rxd0_x", 508 "eth_rxd1_x", 509 "eth_rxd2_rgmii", 510 "eth_rxd3_rgmii", 511 "eth_rgmii_tx_clk", 512 "eth_txen_x", 513 "eth_txd0_x", 514 "eth_txd1_x", 515 "eth_txd2_rgmii", 516 "eth_txd3_rgmii"; 517 function = "eth"; 518 bias-disable; 519 }; 520 }; 521 522 eth_rgmii_y_pins: eth-y-rgmii { 523 mux { 524 groups = "eth_mdio_y", 525 "eth_mdc_y", 526 "eth_rgmii_rx_clk_y", 527 "eth_rx_dv_y", 528 "eth_rxd0_y", 529 "eth_rxd1_y", 530 "eth_rxd2_rgmii", 531 "eth_rxd3_rgmii", 532 "eth_rgmii_tx_clk", 533 "eth_txen_y", 534 "eth_txd0_y", 535 "eth_txd1_y", 536 "eth_txd2_rgmii", 537 "eth_txd3_rgmii"; 538 function = "eth"; 539 bias-disable; 540 }; 541 }; 542 543 eth_rmii_x_pins: eth-x-rmii { 544 mux { 545 groups = "eth_mdio_x", 546 "eth_mdc_x", 547 "eth_rgmii_rx_clk_x", 548 "eth_rx_dv_x", 549 "eth_rxd0_x", 550 "eth_rxd1_x", 551 "eth_txen_x", 552 "eth_txd0_x", 553 "eth_txd1_x"; 554 function = "eth"; 555 bias-disable; 556 }; 557 }; 558 559 eth_rmii_y_pins: eth-y-rmii { 560 mux { 561 groups = "eth_mdio_y", 562 "eth_mdc_y", 563 "eth_rgmii_rx_clk_y", 564 "eth_rx_dv_y", 565 "eth_rxd0_y", 566 "eth_rxd1_y", 567 "eth_txen_y", 568 "eth_txd0_y", 569 "eth_txd1_y"; 570 function = "eth"; 571 bias-disable; 572 }; 573 }; 574 575 mclk_b_pins: mclk_b { 576 mux { 577 groups = "mclk_b"; 578 function = "mclk_b"; 579 bias-disable; 580 }; 581 }; 582 583 mclk_c_pins: mclk_c { 584 mux { 585 groups = "mclk_c"; 586 function = "mclk_c"; 587 bias-disable; 588 }; 589 }; 590 591 pdm_dclk_a14_pins: pdm_dclk_a14 { 592 mux { 593 groups = "pdm_dclk_a14"; 594 function = "pdm"; 595 bias-disable; 596 }; 597 }; 598 599 pdm_dclk_a19_pins: pdm_dclk_a19 { 600 mux { 601 groups = "pdm_dclk_a19"; 602 function = "pdm"; 603 bias-disable; 604 }; 605 }; 606 607 pdm_din0_pins: pdm_din0 { 608 mux { 609 groups = "pdm_din0"; 610 function = "pdm"; 611 bias-disable; 612 }; 613 }; 614 615 pdm_din1_pins: pdm_din1 { 616 mux { 617 groups = "pdm_din1"; 618 function = "pdm"; 619 bias-disable; 620 }; 621 }; 622 623 pdm_din2_pins: pdm_din2 { 624 mux { 625 groups = "pdm_din2"; 626 function = "pdm"; 627 bias-disable; 628 }; 629 }; 630 631 pdm_din3_pins: pdm_din3 { 632 mux { 633 groups = "pdm_din3"; 634 function = "pdm"; 635 bias-disable; 636 }; 637 }; 638 639 pwm_a_a_pins: pwm_a_a { 640 mux { 641 groups = "pwm_a_a"; 642 function = "pwm_a"; 643 bias-disable; 644 }; 645 }; 646 647 pwm_a_x18_pins: pwm_a_x18 { 648 mux { 649 groups = "pwm_a_x18"; 650 function = "pwm_a"; 651 bias-disable; 652 }; 653 }; 654 655 pwm_a_x20_pins: pwm_a_x20 { 656 mux { 657 groups = "pwm_a_x20"; 658 function = "pwm_a"; 659 bias-disable; 660 }; 661 }; 662 663 pwm_a_z_pins: pwm_a_z { 664 mux { 665 groups = "pwm_a_z"; 666 function = "pwm_a"; 667 bias-disable; 668 }; 669 }; 670 671 pwm_b_a_pins: pwm_b_a { 672 mux { 673 groups = "pwm_b_a"; 674 function = "pwm_b"; 675 bias-disable; 676 }; 677 }; 678 679 pwm_b_x_pins: pwm_b_x { 680 mux { 681 groups = "pwm_b_x"; 682 function = "pwm_b"; 683 bias-disable; 684 }; 685 }; 686 687 pwm_b_z_pins: pwm_b_z { 688 mux { 689 groups = "pwm_b_z"; 690 function = "pwm_b"; 691 bias-disable; 692 }; 693 }; 694 695 pwm_c_a_pins: pwm_c_a { 696 mux { 697 groups = "pwm_c_a"; 698 function = "pwm_c"; 699 bias-disable; 700 }; 701 }; 702 703 pwm_c_x10_pins: pwm_c_x10 { 704 mux { 705 groups = "pwm_c_x10"; 706 function = "pwm_c"; 707 bias-disable; 708 }; 709 }; 710 711 pwm_c_x17_pins: pwm_c_x17 { 712 mux { 713 groups = "pwm_c_x17"; 714 function = "pwm_c"; 715 bias-disable; 716 }; 717 }; 718 719 pwm_d_x11_pins: pwm_d_x11 { 720 mux { 721 groups = "pwm_d_x11"; 722 function = "pwm_d"; 723 bias-disable; 724 }; 725 }; 726 727 pwm_d_x16_pins: pwm_d_x16 { 728 mux { 729 groups = "pwm_d_x16"; 730 function = "pwm_d"; 731 bias-disable; 732 }; 733 }; 734 735 sdio_pins: sdio { 736 mux-0 { 737 groups = "sdio_d0", 738 "sdio_d1", 739 "sdio_d2", 740 "sdio_d3", 741 "sdio_cmd"; 742 function = "sdio"; 743 bias-pull-up; 744 }; 745 746 mux-1 { 747 groups = "sdio_clk"; 748 function = "sdio"; 749 bias-disable; 750 }; 751 }; 752 753 sdio_clk_gate_pins: sdio_clk_gate { 754 mux { 755 groups = "GPIOX_4"; 756 function = "gpio_periphs"; 757 bias-pull-down; 758 }; 759 }; 760 761 spdif_in_z_pins: spdif_in_z { 762 mux { 763 groups = "spdif_in_z"; 764 function = "spdif_in"; 765 bias-disable; 766 }; 767 }; 768 769 spdif_in_a1_pins: spdif_in_a1 { 770 mux { 771 groups = "spdif_in_a1"; 772 function = "spdif_in"; 773 bias-disable; 774 }; 775 }; 776 777 spdif_in_a7_pins: spdif_in_a7 { 778 mux { 779 groups = "spdif_in_a7"; 780 function = "spdif_in"; 781 bias-disable; 782 }; 783 }; 784 785 spdif_in_a19_pins: spdif_in_a19 { 786 mux { 787 groups = "spdif_in_a19"; 788 function = "spdif_in"; 789 bias-disable; 790 }; 791 }; 792 793 spdif_in_a20_pins: spdif_in_a20 { 794 mux { 795 groups = "spdif_in_a20"; 796 function = "spdif_in"; 797 bias-disable; 798 }; 799 }; 800 801 spdif_out_a1_pins: spdif_out_a1 { 802 mux { 803 groups = "spdif_out_a1"; 804 function = "spdif_out"; 805 bias-disable; 806 }; 807 }; 808 809 spdif_out_a11_pins: spdif_out_a11 { 810 mux { 811 groups = "spdif_out_a11"; 812 function = "spdif_out"; 813 bias-disable; 814 }; 815 }; 816 817 spdif_out_a19_pins: spdif_out_a19 { 818 mux { 819 groups = "spdif_out_a19"; 820 function = "spdif_out"; 821 bias-disable; 822 }; 823 }; 824 825 spdif_out_a20_pins: spdif_out_a20 { 826 mux { 827 groups = "spdif_out_a20"; 828 function = "spdif_out"; 829 bias-disable; 830 }; 831 }; 832 833 spdif_out_z_pins: spdif_out_z { 834 mux { 835 groups = "spdif_out_z"; 836 function = "spdif_out"; 837 bias-disable; 838 }; 839 }; 840 841 spi0_pins: spi0 { 842 mux { 843 groups = "spi0_miso", 844 "spi0_mosi", 845 "spi0_clk"; 846 function = "spi0"; 847 bias-disable; 848 }; 849 }; 850 851 spi0_ss0_pins: spi0_ss0 { 852 mux { 853 groups = "spi0_ss0"; 854 function = "spi0"; 855 bias-disable; 856 }; 857 }; 858 859 spi0_ss1_pins: spi0_ss1 { 860 mux { 861 groups = "spi0_ss1"; 862 function = "spi0"; 863 bias-disable; 864 }; 865 }; 866 867 spi0_ss2_pins: spi0_ss2 { 868 mux { 869 groups = "spi0_ss2"; 870 function = "spi0"; 871 bias-disable; 872 }; 873 }; 874 875 spi1_a_pins: spi1_a { 876 mux { 877 groups = "spi1_miso_a", 878 "spi1_mosi_a", 879 "spi1_clk_a"; 880 function = "spi1"; 881 bias-disable; 882 }; 883 }; 884 885 spi1_ss0_a_pins: spi1_ss0_a { 886 mux { 887 groups = "spi1_ss0_a"; 888 function = "spi1"; 889 bias-disable; 890 }; 891 }; 892 893 spi1_ss1_pins: spi1_ss1 { 894 mux { 895 groups = "spi1_ss1"; 896 function = "spi1"; 897 bias-disable; 898 }; 899 }; 900 901 spi1_x_pins: spi1_x { 902 mux { 903 groups = "spi1_miso_x", 904 "spi1_mosi_x", 905 "spi1_clk_x"; 906 function = "spi1"; 907 bias-disable; 908 }; 909 }; 910 911 spi1_ss0_x_pins: spi1_ss0_x { 912 mux { 913 groups = "spi1_ss0_x"; 914 function = "spi1"; 915 bias-disable; 916 }; 917 }; 918 919 tdma_din0_pins: tdma_din0 { 920 mux { 921 groups = "tdma_din0"; 922 function = "tdma"; 923 bias-disable; 924 }; 925 }; 926 927 tdma_dout0_x14_pins: tdma_dout0_x14 { 928 mux { 929 groups = "tdma_dout0_x14"; 930 function = "tdma"; 931 bias-disable; 932 }; 933 }; 934 935 tdma_dout0_x15_pins: tdma_dout0_x15 { 936 mux { 937 groups = "tdma_dout0_x15"; 938 function = "tdma"; 939 bias-disable; 940 }; 941 }; 942 943 tdma_dout1_pins: tdma_dout1 { 944 mux { 945 groups = "tdma_dout1"; 946 function = "tdma"; 947 bias-disable; 948 }; 949 }; 950 951 tdma_din1_pins: tdma_din1 { 952 mux { 953 groups = "tdma_din1"; 954 function = "tdma"; 955 bias-disable; 956 }; 957 }; 958 959 tdma_fs_pins: tdma_fs { 960 mux { 961 groups = "tdma_fs"; 962 function = "tdma"; 963 bias-disable; 964 }; 965 }; 966 967 tdma_fs_slv_pins: tdma_fs_slv { 968 mux { 969 groups = "tdma_fs_slv"; 970 function = "tdma"; 971 bias-disable; 972 }; 973 }; 974 975 tdma_sclk_pins: tdma_sclk { 976 mux { 977 groups = "tdma_sclk"; 978 function = "tdma"; 979 bias-disable; 980 }; 981 }; 982 983 tdma_sclk_slv_pins: tdma_sclk_slv { 984 mux { 985 groups = "tdma_sclk_slv"; 986 function = "tdma"; 987 bias-disable; 988 }; 989 }; 990 991 tdmb_din0_pins: tdmb_din0 { 992 mux { 993 groups = "tdmb_din0"; 994 function = "tdmb"; 995 bias-disable; 996 }; 997 }; 998 999 tdmb_din1_pins: tdmb_din1 { 1000 mux { 1001 groups = "tdmb_din1"; 1002 function = "tdmb"; 1003 bias-disable; 1004 }; 1005 }; 1006 1007 tdmb_din2_pins: tdmb_din2 { 1008 mux { 1009 groups = "tdmb_din2"; 1010 function = "tdmb"; 1011 bias-disable; 1012 }; 1013 }; 1014 1015 tdmb_din3_pins: tdmb_din3 { 1016 mux { 1017 groups = "tdmb_din3"; 1018 function = "tdmb"; 1019 bias-disable; 1020 }; 1021 }; 1022 1023 tdmb_dout0_pins: tdmb_dout0 { 1024 mux { 1025 groups = "tdmb_dout0"; 1026 function = "tdmb"; 1027 bias-disable; 1028 }; 1029 }; 1030 1031 tdmb_dout1_pins: tdmb_dout1 { 1032 mux { 1033 groups = "tdmb_dout1"; 1034 function = "tdmb"; 1035 bias-disable; 1036 }; 1037 }; 1038 1039 tdmb_dout2_pins: tdmb_dout2 { 1040 mux { 1041 groups = "tdmb_dout2"; 1042 function = "tdmb"; 1043 bias-disable; 1044 }; 1045 }; 1046 1047 tdmb_dout3_pins: tdmb_dout3 { 1048 mux { 1049 groups = "tdmb_dout3"; 1050 function = "tdmb"; 1051 bias-disable; 1052 }; 1053 }; 1054 1055 tdmb_fs_pins: tdmb_fs { 1056 mux { 1057 groups = "tdmb_fs"; 1058 function = "tdmb"; 1059 bias-disable; 1060 }; 1061 }; 1062 1063 tdmb_fs_slv_pins: tdmb_fs_slv { 1064 mux { 1065 groups = "tdmb_fs_slv"; 1066 function = "tdmb"; 1067 bias-disable; 1068 }; 1069 }; 1070 1071 tdmb_sclk_pins: tdmb_sclk { 1072 mux { 1073 groups = "tdmb_sclk"; 1074 function = "tdmb"; 1075 bias-disable; 1076 }; 1077 }; 1078 1079 tdmb_sclk_slv_pins: tdmb_sclk_slv { 1080 mux { 1081 groups = "tdmb_sclk_slv"; 1082 function = "tdmb"; 1083 bias-disable; 1084 }; 1085 }; 1086 1087 tdmc_fs_pins: tdmc_fs { 1088 mux { 1089 groups = "tdmc_fs"; 1090 function = "tdmc"; 1091 bias-disable; 1092 }; 1093 }; 1094 1095 tdmc_fs_slv_pins: tdmc_fs_slv { 1096 mux { 1097 groups = "tdmc_fs_slv"; 1098 function = "tdmc"; 1099 bias-disable; 1100 }; 1101 }; 1102 1103 tdmc_sclk_pins: tdmc_sclk { 1104 mux { 1105 groups = "tdmc_sclk"; 1106 function = "tdmc"; 1107 bias-disable; 1108 }; 1109 }; 1110 1111 tdmc_sclk_slv_pins: tdmc_sclk_slv { 1112 mux { 1113 groups = "tdmc_sclk_slv"; 1114 function = "tdmc"; 1115 bias-disable; 1116 }; 1117 }; 1118 1119 tdmc_din0_pins: tdmc_din0 { 1120 mux { 1121 groups = "tdmc_din0"; 1122 function = "tdmc"; 1123 bias-disable; 1124 }; 1125 }; 1126 1127 tdmc_din1_pins: tdmc_din1 { 1128 mux { 1129 groups = "tdmc_din1"; 1130 function = "tdmc"; 1131 bias-disable; 1132 }; 1133 }; 1134 1135 tdmc_din2_pins: tdmc_din2 { 1136 mux { 1137 groups = "tdmc_din2"; 1138 function = "tdmc"; 1139 bias-disable; 1140 }; 1141 }; 1142 1143 tdmc_din3_pins: tdmc_din3 { 1144 mux { 1145 groups = "tdmc_din3"; 1146 function = "tdmc"; 1147 bias-disable; 1148 }; 1149 }; 1150 1151 tdmc_dout0_pins: tdmc_dout0 { 1152 mux { 1153 groups = "tdmc_dout0"; 1154 function = "tdmc"; 1155 bias-disable; 1156 }; 1157 }; 1158 1159 tdmc_dout1_pins: tdmc_dout1 { 1160 mux { 1161 groups = "tdmc_dout1"; 1162 function = "tdmc"; 1163 bias-disable; 1164 }; 1165 }; 1166 1167 tdmc_dout2_pins: tdmc_dout2 { 1168 mux { 1169 groups = "tdmc_dout2"; 1170 function = "tdmc"; 1171 bias-disable; 1172 }; 1173 }; 1174 1175 tdmc_dout3_pins: tdmc_dout3 { 1176 mux { 1177 groups = "tdmc_dout3"; 1178 function = "tdmc"; 1179 bias-disable; 1180 }; 1181 }; 1182 1183 uart_a_pins: uart_a { 1184 mux { 1185 groups = "uart_tx_a", 1186 "uart_rx_a"; 1187 function = "uart_a"; 1188 bias-pull-up; 1189 }; 1190 }; 1191 1192 uart_a_cts_rts_pins: uart_a_cts_rts { 1193 mux { 1194 groups = "uart_cts_a", 1195 "uart_rts_a"; 1196 function = "uart_a"; 1197 bias-disable; 1198 }; 1199 }; 1200 1201 uart_b_x_pins: uart_b_x { 1202 mux { 1203 groups = "uart_tx_b_x", 1204 "uart_rx_b_x"; 1205 function = "uart_b"; 1206 bias-pull-up; 1207 }; 1208 }; 1209 1210 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 1211 mux { 1212 groups = "uart_cts_b_x", 1213 "uart_rts_b_x"; 1214 function = "uart_b"; 1215 bias-disable; 1216 }; 1217 }; 1218 1219 uart_b_z_pins: uart_b_z { 1220 mux { 1221 groups = "uart_tx_b_z", 1222 "uart_rx_b_z"; 1223 function = "uart_b"; 1224 bias-pull-up; 1225 }; 1226 }; 1227 1228 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 1229 mux { 1230 groups = "uart_cts_b_z", 1231 "uart_rts_b_z"; 1232 function = "uart_b"; 1233 bias-disable; 1234 }; 1235 }; 1236 1237 uart_ao_b_z_pins: uart_ao_b_z { 1238 mux { 1239 groups = "uart_ao_tx_b_z", 1240 "uart_ao_rx_b_z"; 1241 function = "uart_ao_b_z"; 1242 bias-pull-up; 1243 }; 1244 }; 1245 1246 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 1247 mux { 1248 groups = "uart_ao_cts_b_z", 1249 "uart_ao_rts_b_z"; 1250 function = "uart_ao_b_z"; 1251 bias-disable; 1252 }; 1253 }; 1254 }; 1255 }; 1256 1257 hiubus: bus@ff63c000 { 1258 compatible = "simple-bus"; 1259 reg = <0x0 0xff63c000 0x0 0x1c00>; 1260 #address-cells = <2>; 1261 #size-cells = <2>; 1262 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 1263 1264 sysctrl: system-controller@0 { 1265 compatible = "amlogic,meson-axg-hhi-sysctrl", 1266 "simple-mfd", "syscon"; 1267 reg = <0 0 0 0x400>; 1268 1269 clkc: clock-controller { 1270 compatible = "amlogic,axg-clkc"; 1271 #clock-cells = <1>; 1272 clocks = <&xtal>; 1273 clock-names = "xtal"; 1274 }; 1275 1276 pwrc: power-controller { 1277 compatible = "amlogic,meson-axg-pwrc"; 1278 #power-domain-cells = <1>; 1279 amlogic,ao-sysctrl = <&sysctrl_AO>; 1280 resets = <&reset RESET_VIU>, 1281 <&reset RESET_VENC>, 1282 <&reset RESET_VCBUS>, 1283 <&reset RESET_VENCL>, 1284 <&reset RESET_VID_LOCK>; 1285 reset-names = "viu", "venc", "vcbus", 1286 "vencl", "vid_lock"; 1287 clocks = <&clkc CLKID_VPU>, 1288 <&clkc CLKID_VAPB>; 1289 clock-names = "vpu", "vapb"; 1290 /* 1291 * VPU clocking is provided by two identical clock paths 1292 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1293 * free mux to safely change frequency while running. 1294 * Same for VAPB but with a final gate after the glitch free mux. 1295 */ 1296 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1297 <&clkc CLKID_VPU_0>, 1298 <&clkc CLKID_VPU>, /* Glitch free mux */ 1299 <&clkc CLKID_VAPB_0_SEL>, 1300 <&clkc CLKID_VAPB_0>, 1301 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1302 assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>, 1303 <0>, /* Do Nothing */ 1304 <&clkc CLKID_VPU_0>, 1305 <&clkc CLKID_FCLK_DIV4>, 1306 <0>, /* Do Nothing */ 1307 <&clkc CLKID_VAPB_0>; 1308 assigned-clock-rates = <0>, /* Do Nothing */ 1309 <250000000>, 1310 <0>, /* Do Nothing */ 1311 <0>, /* Do Nothing */ 1312 <250000000>, 1313 <0>; /* Do Nothing */ 1314 }; 1315 1316 mipi_pcie_analog_dphy: phy { 1317 compatible = "amlogic,axg-mipi-pcie-analog-phy"; 1318 #phy-cells = <0>; 1319 status = "disabled"; 1320 }; 1321 }; 1322 }; 1323 1324 mailbox: mailbox@ff63c404 { 1325 compatible = "amlogic,meson-gxbb-mhu"; 1326 reg = <0 0xff63c404 0 0x4c>; 1327 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 1328 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 1329 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 1330 #mbox-cells = <1>; 1331 }; 1332 1333 mipi_dphy: phy@ff640000 { 1334 compatible = "amlogic,axg-mipi-dphy"; 1335 reg = <0x0 0xff640000 0x0 0x100>; 1336 clocks = <&clkc CLKID_MIPI_DSI_PHY>; 1337 clock-names = "pclk"; 1338 resets = <&reset RESET_MIPI_PHY>; 1339 reset-names = "phy"; 1340 phys = <&mipi_pcie_analog_dphy>; 1341 phy-names = "analog"; 1342 #phy-cells = <0>; 1343 status = "disabled"; 1344 }; 1345 1346 audio: bus@ff642000 { 1347 compatible = "simple-bus"; 1348 reg = <0x0 0xff642000 0x0 0x2000>; 1349 #address-cells = <2>; 1350 #size-cells = <2>; 1351 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 1352 1353 clkc_audio: clock-controller@0 { 1354 compatible = "amlogic,axg-audio-clkc"; 1355 reg = <0x0 0x0 0x0 0xb4>; 1356 #clock-cells = <1>; 1357 1358 clocks = <&clkc CLKID_AUDIO>, 1359 <&clkc CLKID_MPLL0>, 1360 <&clkc CLKID_MPLL1>, 1361 <&clkc CLKID_MPLL2>, 1362 <&clkc CLKID_MPLL3>, 1363 <&clkc CLKID_HIFI_PLL>, 1364 <&clkc CLKID_FCLK_DIV3>, 1365 <&clkc CLKID_FCLK_DIV4>, 1366 <&clkc CLKID_GP0_PLL>; 1367 clock-names = "pclk", 1368 "mst_in0", 1369 "mst_in1", 1370 "mst_in2", 1371 "mst_in3", 1372 "mst_in4", 1373 "mst_in5", 1374 "mst_in6", 1375 "mst_in7"; 1376 1377 resets = <&reset RESET_AUDIO>; 1378 }; 1379 1380 toddr_a: audio-controller@100 { 1381 compatible = "amlogic,axg-toddr"; 1382 reg = <0x0 0x100 0x0 0x2c>; 1383 #sound-dai-cells = <0>; 1384 sound-name-prefix = "TODDR_A"; 1385 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 1386 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1387 resets = <&arb AXG_ARB_TODDR_A>; 1388 amlogic,fifo-depth = <512>; 1389 status = "disabled"; 1390 }; 1391 1392 toddr_b: audio-controller@140 { 1393 compatible = "amlogic,axg-toddr"; 1394 reg = <0x0 0x140 0x0 0x2c>; 1395 #sound-dai-cells = <0>; 1396 sound-name-prefix = "TODDR_B"; 1397 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1398 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1399 resets = <&arb AXG_ARB_TODDR_B>; 1400 amlogic,fifo-depth = <256>; 1401 status = "disabled"; 1402 }; 1403 1404 toddr_c: audio-controller@180 { 1405 compatible = "amlogic,axg-toddr"; 1406 reg = <0x0 0x180 0x0 0x2c>; 1407 #sound-dai-cells = <0>; 1408 sound-name-prefix = "TODDR_C"; 1409 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; 1410 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1411 resets = <&arb AXG_ARB_TODDR_C>; 1412 amlogic,fifo-depth = <256>; 1413 status = "disabled"; 1414 }; 1415 1416 frddr_a: audio-controller@1c0 { 1417 compatible = "amlogic,axg-frddr"; 1418 reg = <0x0 0x1c0 0x0 0x2c>; 1419 #sound-dai-cells = <0>; 1420 sound-name-prefix = "FRDDR_A"; 1421 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 1422 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1423 resets = <&arb AXG_ARB_FRDDR_A>; 1424 amlogic,fifo-depth = <512>; 1425 status = "disabled"; 1426 }; 1427 1428 frddr_b: audio-controller@200 { 1429 compatible = "amlogic,axg-frddr"; 1430 reg = <0x0 0x200 0x0 0x2c>; 1431 #sound-dai-cells = <0>; 1432 sound-name-prefix = "FRDDR_B"; 1433 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 1434 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1435 resets = <&arb AXG_ARB_FRDDR_B>; 1436 amlogic,fifo-depth = <256>; 1437 status = "disabled"; 1438 }; 1439 1440 frddr_c: audio-controller@240 { 1441 compatible = "amlogic,axg-frddr"; 1442 reg = <0x0 0x240 0x0 0x2c>; 1443 #sound-dai-cells = <0>; 1444 sound-name-prefix = "FRDDR_C"; 1445 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 1446 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1447 resets = <&arb AXG_ARB_FRDDR_C>; 1448 amlogic,fifo-depth = <256>; 1449 status = "disabled"; 1450 }; 1451 1452 arb: reset-controller@280 { 1453 compatible = "amlogic,meson-axg-audio-arb"; 1454 reg = <0x0 0x280 0x0 0x4>; 1455 #reset-cells = <1>; 1456 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1457 }; 1458 1459 tdmin_a: audio-controller@300 { 1460 compatible = "amlogic,axg-tdmin"; 1461 reg = <0x0 0x300 0x0 0x40>; 1462 sound-name-prefix = "TDMIN_A"; 1463 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1464 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1465 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1466 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1467 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1468 clock-names = "pclk", "sclk", "sclk_sel", 1469 "lrclk", "lrclk_sel"; 1470 status = "disabled"; 1471 }; 1472 1473 tdmin_b: audio-controller@340 { 1474 compatible = "amlogic,axg-tdmin"; 1475 reg = <0x0 0x340 0x0 0x40>; 1476 sound-name-prefix = "TDMIN_B"; 1477 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1478 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1479 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1480 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1481 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1482 clock-names = "pclk", "sclk", "sclk_sel", 1483 "lrclk", "lrclk_sel"; 1484 status = "disabled"; 1485 }; 1486 1487 tdmin_c: audio-controller@380 { 1488 compatible = "amlogic,axg-tdmin"; 1489 reg = <0x0 0x380 0x0 0x40>; 1490 sound-name-prefix = "TDMIN_C"; 1491 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1492 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1493 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1494 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1495 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1496 clock-names = "pclk", "sclk", "sclk_sel", 1497 "lrclk", "lrclk_sel"; 1498 status = "disabled"; 1499 }; 1500 1501 tdmin_lb: audio-controller@3c0 { 1502 compatible = "amlogic,axg-tdmin"; 1503 reg = <0x0 0x3c0 0x0 0x40>; 1504 sound-name-prefix = "TDMIN_LB"; 1505 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1506 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1507 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1508 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1509 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1510 clock-names = "pclk", "sclk", "sclk_sel", 1511 "lrclk", "lrclk_sel"; 1512 status = "disabled"; 1513 }; 1514 1515 spdifin: audio-controller@400 { 1516 compatible = "amlogic,axg-spdifin"; 1517 reg = <0x0 0x400 0x0 0x30>; 1518 #sound-dai-cells = <0>; 1519 sound-name-prefix = "SPDIFIN"; 1520 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; 1521 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1522 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1523 clock-names = "pclk", "refclk"; 1524 status = "disabled"; 1525 }; 1526 1527 spdifout: audio-controller@480 { 1528 compatible = "amlogic,axg-spdifout"; 1529 reg = <0x0 0x480 0x0 0x50>; 1530 #sound-dai-cells = <0>; 1531 sound-name-prefix = "SPDIFOUT"; 1532 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1533 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1534 clock-names = "pclk", "mclk"; 1535 status = "disabled"; 1536 }; 1537 1538 tdmout_a: audio-controller@500 { 1539 compatible = "amlogic,axg-tdmout"; 1540 reg = <0x0 0x500 0x0 0x40>; 1541 sound-name-prefix = "TDMOUT_A"; 1542 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1543 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1544 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1545 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1546 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1547 clock-names = "pclk", "sclk", "sclk_sel", 1548 "lrclk", "lrclk_sel"; 1549 status = "disabled"; 1550 }; 1551 1552 tdmout_b: audio-controller@540 { 1553 compatible = "amlogic,axg-tdmout"; 1554 reg = <0x0 0x540 0x0 0x40>; 1555 sound-name-prefix = "TDMOUT_B"; 1556 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1557 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1558 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1559 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1560 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1561 clock-names = "pclk", "sclk", "sclk_sel", 1562 "lrclk", "lrclk_sel"; 1563 status = "disabled"; 1564 }; 1565 1566 tdmout_c: audio-controller@580 { 1567 compatible = "amlogic,axg-tdmout"; 1568 reg = <0x0 0x580 0x0 0x40>; 1569 sound-name-prefix = "TDMOUT_C"; 1570 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1571 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1572 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1573 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1574 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1575 clock-names = "pclk", "sclk", "sclk_sel", 1576 "lrclk", "lrclk_sel"; 1577 status = "disabled"; 1578 }; 1579 }; 1580 1581 aobus: bus@ff800000 { 1582 compatible = "simple-bus"; 1583 reg = <0x0 0xff800000 0x0 0x100000>; 1584 #address-cells = <2>; 1585 #size-cells = <2>; 1586 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1587 1588 sysctrl_AO: sys-ctrl@0 { 1589 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; 1590 reg = <0x0 0x0 0x0 0x100>; 1591 1592 clkc_AO: clock-controller { 1593 compatible = "amlogic,meson-axg-aoclkc"; 1594 #clock-cells = <1>; 1595 #reset-cells = <1>; 1596 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1597 clock-names = "xtal", "mpeg-clk"; 1598 }; 1599 }; 1600 1601 pinctrl_aobus: pinctrl@14 { 1602 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1603 #address-cells = <2>; 1604 #size-cells = <2>; 1605 ranges; 1606 1607 gpio_ao: bank@14 { 1608 reg = <0x0 0x00014 0x0 0x8>, 1609 <0x0 0x0002c 0x0 0x4>, 1610 <0x0 0x00024 0x0 0x8>; 1611 reg-names = "mux", "pull", "gpio"; 1612 gpio-controller; 1613 #gpio-cells = <2>; 1614 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1615 }; 1616 1617 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1618 mux { 1619 groups = "i2c_ao_sck_4"; 1620 function = "i2c_ao"; 1621 bias-disable; 1622 }; 1623 }; 1624 1625 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1626 mux { 1627 groups = "i2c_ao_sck_8"; 1628 function = "i2c_ao"; 1629 bias-disable; 1630 }; 1631 }; 1632 1633 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1634 mux { 1635 groups = "i2c_ao_sck_10"; 1636 function = "i2c_ao"; 1637 bias-disable; 1638 }; 1639 }; 1640 1641 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1642 mux { 1643 groups = "i2c_ao_sda_5"; 1644 function = "i2c_ao"; 1645 bias-disable; 1646 }; 1647 }; 1648 1649 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1650 mux { 1651 groups = "i2c_ao_sda_9"; 1652 function = "i2c_ao"; 1653 bias-disable; 1654 }; 1655 }; 1656 1657 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1658 mux { 1659 groups = "i2c_ao_sda_11"; 1660 function = "i2c_ao"; 1661 bias-disable; 1662 }; 1663 }; 1664 1665 remote_input_ao_pins: remote_input_ao { 1666 mux { 1667 groups = "remote_input_ao"; 1668 function = "remote_input_ao"; 1669 bias-disable; 1670 }; 1671 }; 1672 1673 uart_ao_a_pins: uart_ao_a { 1674 mux { 1675 groups = "uart_ao_tx_a", 1676 "uart_ao_rx_a"; 1677 function = "uart_ao_a"; 1678 bias-pull-up; 1679 }; 1680 }; 1681 1682 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1683 mux { 1684 groups = "uart_ao_cts_a", 1685 "uart_ao_rts_a"; 1686 function = "uart_ao_a"; 1687 bias-disable; 1688 }; 1689 }; 1690 1691 uart_ao_b_pins: uart_ao_b { 1692 mux { 1693 groups = "uart_ao_tx_b", 1694 "uart_ao_rx_b"; 1695 function = "uart_ao_b"; 1696 bias-pull-up; 1697 }; 1698 }; 1699 1700 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1701 mux { 1702 groups = "uart_ao_cts_b", 1703 "uart_ao_rts_b"; 1704 function = "uart_ao_b"; 1705 bias-disable; 1706 }; 1707 }; 1708 }; 1709 1710 sec_AO: ao-secure@140 { 1711 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1712 reg = <0x0 0x140 0x0 0x140>; 1713 amlogic,has-chip-id; 1714 }; 1715 1716 pwm_AO_cd: pwm@2000 { 1717 compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; 1718 reg = <0x0 0x02000 0x0 0x20>; 1719 clocks = <&xtal>, 1720 <&clkc_AO CLKID_AO_CLK81>, 1721 <&clkc CLKID_FCLK_DIV4>, 1722 <&clkc CLKID_FCLK_DIV5>; 1723 #pwm-cells = <3>; 1724 status = "disabled"; 1725 }; 1726 1727 uart_AO: serial@3000 { 1728 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1729 reg = <0x0 0x3000 0x0 0x18>; 1730 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1731 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1732 clock-names = "xtal", "pclk", "baud"; 1733 status = "disabled"; 1734 }; 1735 1736 uart_AO_B: serial@4000 { 1737 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1738 reg = <0x0 0x4000 0x0 0x18>; 1739 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1740 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1741 clock-names = "xtal", "pclk", "baud"; 1742 status = "disabled"; 1743 }; 1744 1745 i2c_AO: i2c@5000 { 1746 compatible = "amlogic,meson-axg-i2c"; 1747 reg = <0x0 0x05000 0x0 0x20>; 1748 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1749 clocks = <&clkc CLKID_AO_I2C>; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 status = "disabled"; 1753 }; 1754 1755 pwm_AO_ab: pwm@7000 { 1756 compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; 1757 reg = <0x0 0x07000 0x0 0x20>; 1758 clocks = <&xtal>, 1759 <&clkc_AO CLKID_AO_CLK81>, 1760 <&clkc CLKID_FCLK_DIV4>, 1761 <&clkc CLKID_FCLK_DIV5>; 1762 #pwm-cells = <3>; 1763 status = "disabled"; 1764 }; 1765 1766 ir: ir@8000 { 1767 compatible = "amlogic,meson-gxbb-ir"; 1768 reg = <0x0 0x8000 0x0 0x20>; 1769 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1770 status = "disabled"; 1771 }; 1772 1773 saradc: adc@9000 { 1774 compatible = "amlogic,meson-axg-saradc", 1775 "amlogic,meson-saradc"; 1776 reg = <0x0 0x9000 0x0 0x38>; 1777 #io-channel-cells = <1>; 1778 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1779 clocks = <&xtal>, 1780 <&clkc_AO CLKID_AO_SAR_ADC>, 1781 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1782 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1783 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1784 status = "disabled"; 1785 }; 1786 }; 1787 1788 ge2d: ge2d@ff940000 { 1789 compatible = "amlogic,axg-ge2d"; 1790 reg = <0x0 0xff940000 0x0 0x10000>; 1791 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1792 clocks = <&clkc CLKID_VAPB>; 1793 resets = <&reset RESET_GE2D>; 1794 }; 1795 1796 gic: interrupt-controller@ffc01000 { 1797 compatible = "arm,gic-400"; 1798 reg = <0x0 0xffc01000 0 0x1000>, 1799 <0x0 0xffc02000 0 0x2000>, 1800 <0x0 0xffc04000 0 0x2000>, 1801 <0x0 0xffc06000 0 0x2000>; 1802 interrupt-controller; 1803 interrupts = <GIC_PPI 9 1804 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1805 #interrupt-cells = <3>; 1806 #address-cells = <0>; 1807 }; 1808 1809 cbus: bus@ffd00000 { 1810 compatible = "simple-bus"; 1811 reg = <0x0 0xffd00000 0x0 0x25000>; 1812 #address-cells = <2>; 1813 #size-cells = <2>; 1814 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 1815 1816 reset: reset-controller@1004 { 1817 compatible = "amlogic,meson-axg-reset"; 1818 reg = <0x0 0x01004 0x0 0x9c>; 1819 #reset-cells = <1>; 1820 }; 1821 1822 gpio_intc: interrupt-controller@f080 { 1823 compatible = "amlogic,meson-axg-gpio-intc", 1824 "amlogic,meson-gpio-intc"; 1825 reg = <0x0 0xf080 0x0 0x10>; 1826 interrupt-controller; 1827 #interrupt-cells = <2>; 1828 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 1829 }; 1830 1831 watchdog@f0d0 { 1832 compatible = "amlogic,meson-gxbb-wdt"; 1833 reg = <0x0 0xf0d0 0x0 0x10>; 1834 clocks = <&xtal>; 1835 }; 1836 1837 pwm_ab: pwm@1b000 { 1838 compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; 1839 reg = <0x0 0x1b000 0x0 0x20>; 1840 clocks = <&xtal>, 1841 <&clkc CLKID_FCLK_DIV5>, 1842 <&clkc CLKID_FCLK_DIV4>, 1843 <&clkc CLKID_FCLK_DIV3>; 1844 #pwm-cells = <3>; 1845 status = "disabled"; 1846 }; 1847 1848 pwm_cd: pwm@1a000 { 1849 compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; 1850 reg = <0x0 0x1a000 0x0 0x20>; 1851 clocks = <&xtal>, 1852 <&clkc CLKID_FCLK_DIV5>, 1853 <&clkc CLKID_FCLK_DIV4>, 1854 <&clkc CLKID_FCLK_DIV3>; 1855 #pwm-cells = <3>; 1856 status = "disabled"; 1857 }; 1858 1859 spicc0: spi@13000 { 1860 compatible = "amlogic,meson-axg-spicc"; 1861 reg = <0x0 0x13000 0x0 0x3c>; 1862 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1863 clocks = <&clkc CLKID_SPICC0>; 1864 clock-names = "core"; 1865 #address-cells = <1>; 1866 #size-cells = <0>; 1867 status = "disabled"; 1868 }; 1869 1870 spicc1: spi@15000 { 1871 compatible = "amlogic,meson-axg-spicc"; 1872 reg = <0x0 0x15000 0x0 0x3c>; 1873 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1874 clocks = <&clkc CLKID_SPICC1>; 1875 clock-names = "core"; 1876 #address-cells = <1>; 1877 #size-cells = <0>; 1878 status = "disabled"; 1879 }; 1880 1881 clk_msr: clock-measure@18000 { 1882 compatible = "amlogic,meson-axg-clk-measure"; 1883 reg = <0x0 0x18000 0x0 0x10>; 1884 }; 1885 1886 i2c3: i2c@1c000 { 1887 compatible = "amlogic,meson-axg-i2c"; 1888 reg = <0x0 0x1c000 0x0 0x20>; 1889 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1890 clocks = <&clkc CLKID_I2C>; 1891 #address-cells = <1>; 1892 #size-cells = <0>; 1893 status = "disabled"; 1894 }; 1895 1896 i2c2: i2c@1d000 { 1897 compatible = "amlogic,meson-axg-i2c"; 1898 reg = <0x0 0x1d000 0x0 0x20>; 1899 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1900 clocks = <&clkc CLKID_I2C>; 1901 #address-cells = <1>; 1902 #size-cells = <0>; 1903 status = "disabled"; 1904 }; 1905 1906 i2c1: i2c@1e000 { 1907 compatible = "amlogic,meson-axg-i2c"; 1908 reg = <0x0 0x1e000 0x0 0x20>; 1909 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1910 clocks = <&clkc CLKID_I2C>; 1911 #address-cells = <1>; 1912 #size-cells = <0>; 1913 status = "disabled"; 1914 }; 1915 1916 i2c0: i2c@1f000 { 1917 compatible = "amlogic,meson-axg-i2c"; 1918 reg = <0x0 0x1f000 0x0 0x20>; 1919 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1920 clocks = <&clkc CLKID_I2C>; 1921 #address-cells = <1>; 1922 #size-cells = <0>; 1923 status = "disabled"; 1924 }; 1925 1926 uart_B: serial@23000 { 1927 compatible = "amlogic,meson-gx-uart"; 1928 reg = <0x0 0x23000 0x0 0x18>; 1929 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1930 status = "disabled"; 1931 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1932 clock-names = "xtal", "pclk", "baud"; 1933 }; 1934 1935 uart_A: serial@24000 { 1936 compatible = "amlogic,meson-gx-uart"; 1937 reg = <0x0 0x24000 0x0 0x18>; 1938 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1939 status = "disabled"; 1940 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1941 clock-names = "xtal", "pclk", "baud"; 1942 fifo-size = <128>; 1943 }; 1944 }; 1945 1946 apb: bus@ffe00000 { 1947 compatible = "simple-bus"; 1948 reg = <0x0 0xffe00000 0x0 0x200000>; 1949 #address-cells = <2>; 1950 #size-cells = <2>; 1951 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 1952 1953 sd_emmc_b: mmc@5000 { 1954 compatible = "amlogic,meson-axg-mmc"; 1955 reg = <0x0 0x5000 0x0 0x800>; 1956 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 1957 status = "disabled"; 1958 clocks = <&clkc CLKID_SD_EMMC_B>, 1959 <&clkc CLKID_SD_EMMC_B_CLK0>, 1960 <&clkc CLKID_FCLK_DIV2>; 1961 clock-names = "core", "clkin0", "clkin1"; 1962 resets = <&reset RESET_SD_EMMC_B>; 1963 }; 1964 1965 sd_emmc_c: mmc@7000 { 1966 compatible = "amlogic,meson-axg-mmc"; 1967 reg = <0x0 0x7000 0x0 0x800>; 1968 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 1969 status = "disabled"; 1970 clocks = <&clkc CLKID_SD_EMMC_C>, 1971 <&clkc CLKID_SD_EMMC_C_CLK0>, 1972 <&clkc CLKID_FCLK_DIV2>; 1973 clock-names = "core", "clkin0", "clkin1"; 1974 resets = <&reset RESET_SD_EMMC_C>; 1975 }; 1976 1977 nfc: nand-controller@7800 { 1978 compatible = "amlogic,meson-axg-nfc"; 1979 reg = <0x0 0x7800 0x0 0x100>, 1980 <0x0 0x7000 0x0 0x800>; 1981 reg-names = "nfc", "emmc"; 1982 pinctrl-0 = <&nand_all_pins>; 1983 pinctrl-names = "default"; 1984 #address-cells = <1>; 1985 #size-cells = <0>; 1986 interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; 1987 clocks = <&clkc CLKID_SD_EMMC_C>, 1988 <&clkc CLKID_FCLK_DIV2>; 1989 clock-names = "core", "device"; 1990 }; 1991 1992 usb2_phy1: phy@9020 { 1993 compatible = "amlogic,meson-gxl-usb2-phy"; 1994 #phy-cells = <0>; 1995 reg = <0x0 0x9020 0x0 0x20>; 1996 clocks = <&clkc CLKID_USB>; 1997 clock-names = "phy"; 1998 resets = <&reset RESET_USB_OTG>; 1999 reset-names = "phy"; 2000 }; 2001 }; 2002 2003 sram: sram@fffc0000 { 2004 compatible = "mmio-sram"; 2005 reg = <0x0 0xfffc0000 0x0 0x20000>; 2006 #address-cells = <1>; 2007 #size-cells = <1>; 2008 ranges = <0 0x0 0xfffc0000 0x20000>; 2009 2010 cpu_scp_lpri: scp-sram@13000 { 2011 compatible = "amlogic,meson-axg-scp-shmem"; 2012 reg = <0x13000 0x400>; 2013 }; 2014 2015 cpu_scp_hpri: scp-sram@13400 { 2016 compatible = "amlogic,meson-axg-scp-shmem"; 2017 reg = <0x13400 0x400>; 2018 }; 2019 }; 2020 }; 2021 2022 timer { 2023 compatible = "arm,armv8-timer"; 2024 interrupts = <GIC_PPI 13 2025 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2026 <GIC_PPI 14 2027 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2028 <GIC_PPI 11 2029 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2030 <GIC_PPI 10 2031 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2032 }; 2033 2034 xtal: xtal-clk { 2035 compatible = "fixed-clock"; 2036 clock-frequency = <24000000>; 2037 clock-output-names = "xtal"; 2038 #clock-cells = <0>; 2039 }; 2040}; 2041