1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2025 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/amlogic,pinctrl.h> 10 11/ { 12 cpus { 13 #address-cells = <2>; 14 #size-cells = <0>; 15 16 cpu0: cpu@0 { 17 device_type = "cpu"; 18 compatible = "arm,cortex-a55"; 19 reg = <0x0 0x0>; 20 enable-method = "psci"; 21 d-cache-line-size = <32>; 22 d-cache-size = <0x8000>; 23 d-cache-sets = <32>; 24 i-cache-line-size = <32>; 25 i-cache-size = <0x8000>; 26 i-cache-sets = <32>; 27 next-level-cache = <&l2>; 28 }; 29 30 cpu1: cpu@100 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a55"; 33 reg = <0x0 0x100>; 34 enable-method = "psci"; 35 d-cache-line-size = <32>; 36 d-cache-size = <0x8000>; 37 d-cache-sets = <32>; 38 i-cache-line-size = <32>; 39 i-cache-size = <0x8000>; 40 i-cache-sets = <32>; 41 next-level-cache = <&l2>; 42 }; 43 44 cpu2: cpu@200 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a55"; 47 reg = <0x0 0x200>; 48 enable-method = "psci"; 49 d-cache-line-size = <32>; 50 d-cache-size = <0x8000>; 51 d-cache-sets = <32>; 52 i-cache-line-size = <32>; 53 i-cache-size = <0x8000>; 54 i-cache-sets = <32>; 55 next-level-cache = <&l2>; 56 }; 57 58 cpu3: cpu@300 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a55"; 61 reg = <0x0 0x300>; 62 enable-method = "psci"; 63 d-cache-line-size = <32>; 64 d-cache-size = <0x8000>; 65 d-cache-sets = <32>; 66 i-cache-line-size = <32>; 67 i-cache-size = <0x8000>; 68 i-cache-sets = <32>; 69 next-level-cache = <&l2>; 70 }; 71 72 l2: l2-cache0 { 73 compatible = "cache"; 74 cache-level = <2>; 75 cache-unified; 76 cache-size = <0x40000>; /* L2. 256 KB */ 77 cache-line-size = <64>; 78 cache-sets = <512>; 79 }; 80 }; 81 82 timer { 83 compatible = "arm,armv8-timer"; 84 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 85 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 86 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 87 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 88 }; 89 90 psci { 91 compatible = "arm,psci-1.0"; 92 method = "smc"; 93 }; 94 95 xtal: xtal-clk { 96 compatible = "fixed-clock"; 97 clock-frequency = <24000000>; 98 clock-output-names = "xtal"; 99 #clock-cells = <0>; 100 }; 101 102 soc { 103 compatible = "simple-bus"; 104 #address-cells = <2>; 105 #size-cells = <2>; 106 ranges; 107 108 gic: interrupt-controller@fff01000 { 109 compatible = "arm,gic-400"; 110 #interrupt-cells = <3>; 111 #address-cells = <0>; 112 interrupt-controller; 113 reg = <0x0 0xfff01000 0 0x1000>, 114 <0x0 0xfff02000 0 0x0100>; 115 interrupts = <GIC_PPI 9 0xf04>; 116 }; 117 118 apb: bus@fe000000 { 119 compatible = "simple-bus"; 120 reg = <0x0 0xfe000000 0x0 0x480000>; 121 #address-cells = <2>; 122 #size-cells = <2>; 123 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 124 125 uart_b: serial@7a000 { 126 compatible = "amlogic,s7-uart", 127 "amlogic,meson-s4-uart"; 128 reg = <0x0 0x7a000 0x0 0x18>; 129 interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; 130 clocks = <&xtal>, <&xtal>, <&xtal>; 131 clock-names = "xtal", "pclk", "baud"; 132 status = "disabled"; 133 }; 134 135 periphs_pinctrl: pinctrl@4000 { 136 compatible = "amlogic,pinctrl-s7"; 137 #address-cells = <2>; 138 #size-cells = <2>; 139 ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>; 140 141 gpioz: gpio@c0 { 142 reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>; 143 reg-names = "gpio", "mux"; 144 gpio-controller; 145 #gpio-cells = <2>; 146 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>; 147 }; 148 149 gpiox: gpio@100 { 150 reg = <0 0x100 0 0x30>, <0 0xc 0 0x8>; 151 reg-names = "gpio", "mux"; 152 gpio-controller; 153 #gpio-cells = <2>; 154 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; 155 }; 156 157 gpioh: gpio@140 { 158 reg = <0 0x140 0 0x20>, <0 0x2c 0 0x8>; 159 reg-names = "gpio", "mux"; 160 gpio-controller; 161 #gpio-cells = <2>; 162 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>; 163 }; 164 165 gpiod: gpio@180 { 166 reg = <0 0x180 0 0x20>, <0 0x40 0 0x8>; 167 reg-names = "gpio", "mux"; 168 gpio-controller; 169 #gpio-cells = <2>; 170 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 12>; 171 }; 172 173 gpioe: gpio@1c0 { 174 reg = <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; 175 reg-names = "gpio", "mux"; 176 gpio-controller; 177 #gpio-cells = <2>; 178 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>; 179 }; 180 181 gpioc: gpio@200 { 182 reg = <0 0x200 0 0x20>, <0 0x24 0 0x4>; 183 reg-names = "gpio", "mux"; 184 gpio-controller; 185 #gpio-cells = <2>; 186 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; 187 }; 188 189 gpiob: gpio@240 { 190 reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>; 191 reg-names = "gpio", "mux"; 192 gpio-controller; 193 #gpio-cells = <2>; 194 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; 195 }; 196 197 test_n: gpio@2c0 { 198 reg = <0 0x2c0 0 0x20>; 199 reg-names = "gpio"; 200 gpio-controller; 201 #gpio-cells = <2>; 202 gpio-ranges = 203 <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; 204 }; 205 206 gpiocc: gpio@300 { 207 reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>; 208 reg-names = "gpio", "mux"; 209 gpio-controller; 210 #gpio-cells = <2>; 211 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; 212 }; 213 }; 214 }; 215 }; 216}; 217