1*ab5eadfeSXianwei Zhao// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*ab5eadfeSXianwei Zhao/* 3*ab5eadfeSXianwei Zhao * Copyright (c) 2026 Amlogic, Inc. All rights reserved. 4*ab5eadfeSXianwei Zhao */ 5*ab5eadfeSXianwei Zhao 6*ab5eadfeSXianwei Zhao#include <dt-bindings/interrupt-controller/irq.h> 7*ab5eadfeSXianwei Zhao#include <dt-bindings/interrupt-controller/arm-gic.h> 8*ab5eadfeSXianwei Zhao#include <dt-bindings/gpio/gpio.h> 9*ab5eadfeSXianwei Zhao 10*ab5eadfeSXianwei Zhao/ { 11*ab5eadfeSXianwei Zhao interrupt-parent = <&gic>; 12*ab5eadfeSXianwei Zhao 13*ab5eadfeSXianwei Zhao cpus { 14*ab5eadfeSXianwei Zhao #address-cells = <2>; 15*ab5eadfeSXianwei Zhao #size-cells = <0>; 16*ab5eadfeSXianwei Zhao 17*ab5eadfeSXianwei Zhao cpu0: cpu@0 { 18*ab5eadfeSXianwei Zhao device_type = "cpu"; 19*ab5eadfeSXianwei Zhao compatible = "arm,cortex-a55"; 20*ab5eadfeSXianwei Zhao reg = <0x0 0x0>; 21*ab5eadfeSXianwei Zhao enable-method = "psci"; 22*ab5eadfeSXianwei Zhao }; 23*ab5eadfeSXianwei Zhao 24*ab5eadfeSXianwei Zhao cpu1: cpu@100 { 25*ab5eadfeSXianwei Zhao device_type = "cpu"; 26*ab5eadfeSXianwei Zhao compatible = "arm,cortex-a55"; 27*ab5eadfeSXianwei Zhao reg = <0x0 0x100>; 28*ab5eadfeSXianwei Zhao enable-method = "psci"; 29*ab5eadfeSXianwei Zhao }; 30*ab5eadfeSXianwei Zhao 31*ab5eadfeSXianwei Zhao cpu2: cpu@200 { 32*ab5eadfeSXianwei Zhao device_type = "cpu"; 33*ab5eadfeSXianwei Zhao compatible = "arm,cortex-a55"; 34*ab5eadfeSXianwei Zhao reg = <0x0 0x200>; 35*ab5eadfeSXianwei Zhao enable-method = "psci"; 36*ab5eadfeSXianwei Zhao }; 37*ab5eadfeSXianwei Zhao 38*ab5eadfeSXianwei Zhao cpu3: cpu@300 { 39*ab5eadfeSXianwei Zhao device_type = "cpu"; 40*ab5eadfeSXianwei Zhao compatible = "arm,cortex-a55"; 41*ab5eadfeSXianwei Zhao reg = <0x0 0x300>; 42*ab5eadfeSXianwei Zhao enable-method = "psci"; 43*ab5eadfeSXianwei Zhao }; 44*ab5eadfeSXianwei Zhao 45*ab5eadfeSXianwei Zhao cpu4: cpu@400 { 46*ab5eadfeSXianwei Zhao device_type = "cpu"; 47*ab5eadfeSXianwei Zhao compatible = "arm,cortex-a55"; 48*ab5eadfeSXianwei Zhao reg = <0x0 0x400>; 49*ab5eadfeSXianwei Zhao enable-method = "psci"; 50*ab5eadfeSXianwei Zhao }; 51*ab5eadfeSXianwei Zhao 52*ab5eadfeSXianwei Zhao cpu5: cpu@500 { 53*ab5eadfeSXianwei Zhao device_type = "cpu"; 54*ab5eadfeSXianwei Zhao compatible = "arm,cortex-a55"; 55*ab5eadfeSXianwei Zhao reg = <0x0 0x500>; 56*ab5eadfeSXianwei Zhao enable-method = "psci"; 57*ab5eadfeSXianwei Zhao }; 58*ab5eadfeSXianwei Zhao 59*ab5eadfeSXianwei Zhao cpu6: cpu@600 { 60*ab5eadfeSXianwei Zhao device_type = "cpu"; 61*ab5eadfeSXianwei Zhao compatible = "arm,cortex-a78"; 62*ab5eadfeSXianwei Zhao reg = <0x0 0x600>; 63*ab5eadfeSXianwei Zhao enable-method = "psci"; 64*ab5eadfeSXianwei Zhao }; 65*ab5eadfeSXianwei Zhao 66*ab5eadfeSXianwei Zhao cpu7: cpu@700 { 67*ab5eadfeSXianwei Zhao device_type = "cpu"; 68*ab5eadfeSXianwei Zhao compatible = "arm,cortex-a78"; 69*ab5eadfeSXianwei Zhao reg = <0x0 0x700>; 70*ab5eadfeSXianwei Zhao enable-method = "psci"; 71*ab5eadfeSXianwei Zhao }; 72*ab5eadfeSXianwei Zhao }; 73*ab5eadfeSXianwei Zhao 74*ab5eadfeSXianwei Zhao timer { 75*ab5eadfeSXianwei Zhao compatible = "arm,armv8-timer"; 76*ab5eadfeSXianwei Zhao interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 77*ab5eadfeSXianwei Zhao <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 78*ab5eadfeSXianwei Zhao <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 79*ab5eadfeSXianwei Zhao <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 80*ab5eadfeSXianwei Zhao }; 81*ab5eadfeSXianwei Zhao 82*ab5eadfeSXianwei Zhao psci { 83*ab5eadfeSXianwei Zhao compatible = "arm,psci-1.0"; 84*ab5eadfeSXianwei Zhao method = "smc"; 85*ab5eadfeSXianwei Zhao }; 86*ab5eadfeSXianwei Zhao 87*ab5eadfeSXianwei Zhao xtal: xtal-clk { 88*ab5eadfeSXianwei Zhao compatible = "fixed-clock"; 89*ab5eadfeSXianwei Zhao clock-frequency = <24000000>; 90*ab5eadfeSXianwei Zhao clock-output-names = "xtal"; 91*ab5eadfeSXianwei Zhao #clock-cells = <0>; 92*ab5eadfeSXianwei Zhao }; 93*ab5eadfeSXianwei Zhao 94*ab5eadfeSXianwei Zhao soc { 95*ab5eadfeSXianwei Zhao compatible = "simple-bus"; 96*ab5eadfeSXianwei Zhao #address-cells = <2>; 97*ab5eadfeSXianwei Zhao #size-cells = <2>; 98*ab5eadfeSXianwei Zhao ranges; 99*ab5eadfeSXianwei Zhao 100*ab5eadfeSXianwei Zhao gic: interrupt-controller@ff800000 { 101*ab5eadfeSXianwei Zhao compatible = "arm,gic-v3"; 102*ab5eadfeSXianwei Zhao #interrupt-cells = <3>; 103*ab5eadfeSXianwei Zhao #address-cells = <0>; 104*ab5eadfeSXianwei Zhao interrupt-controller; 105*ab5eadfeSXianwei Zhao reg = <0x0 0xff800000 0 0x10000>, 106*ab5eadfeSXianwei Zhao <0x0 0xff840000 0 0x100000>; 107*ab5eadfeSXianwei Zhao interrupts = <GIC_PPI 9 0xf04>; 108*ab5eadfeSXianwei Zhao }; 109*ab5eadfeSXianwei Zhao 110*ab5eadfeSXianwei Zhao aobus: bus@ffa00000 { 111*ab5eadfeSXianwei Zhao compatible = "simple-bus"; 112*ab5eadfeSXianwei Zhao reg = <0x0 0xffa00000 0x0 0x100000>; 113*ab5eadfeSXianwei Zhao #address-cells = <2>; 114*ab5eadfeSXianwei Zhao #size-cells = <2>; 115*ab5eadfeSXianwei Zhao ranges = <0x0 0x0 0x0 0xffa00000 0x0 0x100000>; 116*ab5eadfeSXianwei Zhao 117*ab5eadfeSXianwei Zhao uart_b: serial@1e000 { 118*ab5eadfeSXianwei Zhao compatible = "amlogic,a9-uart", 119*ab5eadfeSXianwei Zhao "amlogic,meson-s4-uart"; 120*ab5eadfeSXianwei Zhao reg = <0x0 0x1e000 0x0 0x18>; 121*ab5eadfeSXianwei Zhao interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>; 122*ab5eadfeSXianwei Zhao clocks = <&xtal>, <&xtal>, <&xtal>; 123*ab5eadfeSXianwei Zhao clock-names = "xtal", "pclk", "baud"; 124*ab5eadfeSXianwei Zhao status = "disabled"; 125*ab5eadfeSXianwei Zhao }; 126*ab5eadfeSXianwei Zhao }; 127*ab5eadfeSXianwei Zhao }; 128*ab5eadfeSXianwei Zhao}; 129