1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2// Copyright (C) 2023-2024 Arm Ltd. 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun6i-rtc.h> 6#include <dt-bindings/clock/sun55i-a523-ccu.h> 7#include <dt-bindings/clock/sun55i-a523-r-ccu.h> 8#include <dt-bindings/reset/sun55i-a523-ccu.h> 9#include <dt-bindings/reset/sun55i-a523-r-ccu.h> 10#include <dt-bindings/power/allwinner,sun55i-a523-ppu.h> 11#include <dt-bindings/power/allwinner,sun55i-a523-pck-600.h> 12 13/ { 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 compatible = "arm,cortex-a55"; 24 device_type = "cpu"; 25 reg = <0x000>; 26 enable-method = "psci"; 27 }; 28 29 cpu1: cpu@100 { 30 compatible = "arm,cortex-a55"; 31 device_type = "cpu"; 32 reg = <0x100>; 33 enable-method = "psci"; 34 }; 35 36 cpu2: cpu@200 { 37 compatible = "arm,cortex-a55"; 38 device_type = "cpu"; 39 reg = <0x200>; 40 enable-method = "psci"; 41 }; 42 43 cpu3: cpu@300 { 44 compatible = "arm,cortex-a55"; 45 device_type = "cpu"; 46 reg = <0x300>; 47 enable-method = "psci"; 48 }; 49 50 cpu4: cpu@400 { 51 compatible = "arm,cortex-a55"; 52 device_type = "cpu"; 53 reg = <0x400>; 54 enable-method = "psci"; 55 }; 56 57 cpu5: cpu@500 { 58 compatible = "arm,cortex-a55"; 59 device_type = "cpu"; 60 reg = <0x500>; 61 enable-method = "psci"; 62 }; 63 64 cpu6: cpu@600 { 65 compatible = "arm,cortex-a55"; 66 device_type = "cpu"; 67 reg = <0x600>; 68 enable-method = "psci"; 69 }; 70 71 cpu7: cpu@700 { 72 compatible = "arm,cortex-a55"; 73 device_type = "cpu"; 74 reg = <0x700>; 75 enable-method = "psci"; 76 }; 77 }; 78 79 osc24M: osc24M-clk { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <24000000>; 83 clock-output-names = "osc24M"; 84 }; 85 86 pmu { 87 compatible = "arm,cortex-a55-pmu"; 88 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 89 }; 90 91 psci { 92 compatible = "arm,psci-0.2"; 93 method = "smc"; 94 }; 95 96 timer { 97 compatible = "arm,armv8-timer"; 98 arm,no-tick-in-suspend; 99 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 103 }; 104 105 soc { 106 compatible = "simple-bus"; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges = <0x0 0x0 0x0 0x40000000>; 110 111 gpu: gpu@1800000 { 112 compatible = "allwinner,sun55i-a523-mali", 113 "arm,mali-valhall-jm"; 114 reg = <0x1800000 0x10000>; 115 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 118 interrupt-names = "job", "mmu", "gpu"; 119 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 120 clock-names = "core", "bus"; 121 power-domains = <&pck600 PD_GPU>; 122 resets = <&ccu RST_BUS_GPU>; 123 status = "disabled"; 124 }; 125 126 pio: pinctrl@2000000 { 127 compatible = "allwinner,sun55i-a523-pinctrl"; 128 reg = <0x2000000 0x800>; 129 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 139 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; 140 clock-names = "apb", "hosc", "losc"; 141 gpio-controller; 142 #gpio-cells = <3>; 143 interrupt-controller; 144 #interrupt-cells = <3>; 145 146 mmc0_pins: mmc0-pins { 147 pins = "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; 148 allwinner,pinmux = <2>; 149 function = "mmc0"; 150 drive-strength = <30>; 151 bias-pull-up; 152 }; 153 154 /omit-if-no-ref/ 155 mmc1_pins: mmc1-pins { 156 pins = "PG0" ,"PG1", "PG2", "PG3", "PG4", "PG5"; 157 allwinner,pinmux = <2>; 158 function = "mmc1"; 159 drive-strength = <30>; 160 bias-pull-up; 161 }; 162 163 mmc2_pins: mmc2-pins { 164 pins = "PC0", "PC1" ,"PC5", "PC6", "PC8", 165 "PC9", "PC10", "PC11", "PC13", "PC14", 166 "PC15", "PC16"; 167 allwinner,pinmux = <3>; 168 function = "mmc2"; 169 drive-strength = <30>; 170 bias-pull-up; 171 }; 172 173 rgmii0_pins: rgmii0-pins { 174 pins = "PH0", "PH1", "PH2", "PH3", "PH4", 175 "PH5", "PH6", "PH7", "PH9", "PH10", 176 "PH14", "PH15", "PH16", "PH17", "PH18"; 177 allwinner,pinmux = <5>; 178 function = "gmac0"; 179 drive-strength = <40>; 180 bias-disable; 181 }; 182 183 uart0_pb_pins: uart0-pb-pins { 184 pins = "PB9", "PB10"; 185 allwinner,pinmux = <2>; 186 function = "uart0"; 187 }; 188 189 /omit-if-no-ref/ 190 uart1_pins: uart1-pins { 191 pins = "PG6", "PG7"; 192 function = "uart1"; 193 allwinner,pinmux = <2>; 194 }; 195 196 /omit-if-no-ref/ 197 uart1_rts_cts_pins: uart1-rts-cts-pins { 198 pins = "PG8", "PG9"; 199 function = "uart1"; 200 allwinner,pinmux = <2>; 201 }; 202 }; 203 204 ccu: clock-controller@2001000 { 205 compatible = "allwinner,sun55i-a523-ccu"; 206 reg = <0x02001000 0x1000>; 207 clocks = <&osc24M>, <&rtc CLK_OSC32K>, 208 <&rtc CLK_IOSC>, <&rtc CLK_OSC32K_FANOUT>; 209 clock-names = "hosc", "losc", 210 "iosc", "losc-fanout"; 211 #clock-cells = <1>; 212 #reset-cells = <1>; 213 }; 214 215 wdt: watchdog@2050000 { 216 compatible = "allwinner,sun55i-a523-wdt"; 217 reg = <0x2050000 0x20>; 218 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&osc24M>, <&rtc CLK_OSC32K>; 220 clock-names = "hosc", "losc"; 221 status = "okay"; 222 }; 223 224 uart0: serial@2500000 { 225 compatible = "snps,dw-apb-uart"; 226 reg = <0x02500000 0x400>; 227 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 228 reg-shift = <2>; 229 reg-io-width = <4>; 230 clocks = <&ccu CLK_BUS_UART0>; 231 resets = <&ccu RST_BUS_UART0>; 232 status = "disabled"; 233 }; 234 235 uart1: serial@2500400 { 236 compatible = "snps,dw-apb-uart"; 237 reg = <0x02500400 0x400>; 238 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 239 reg-shift = <2>; 240 reg-io-width = <4>; 241 clocks = <&ccu CLK_BUS_UART1>; 242 resets = <&ccu RST_BUS_UART1>; 243 status = "disabled"; 244 }; 245 246 uart2: serial@2500800 { 247 compatible = "snps,dw-apb-uart"; 248 reg = <0x02500800 0x400>; 249 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 250 reg-shift = <2>; 251 reg-io-width = <4>; 252 clocks = <&ccu CLK_BUS_UART2>; 253 resets = <&ccu RST_BUS_UART2>; 254 status = "disabled"; 255 }; 256 257 uart3: serial@2500c00 { 258 compatible = "snps,dw-apb-uart"; 259 reg = <0x02500c00 0x400>; 260 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 261 reg-shift = <2>; 262 reg-io-width = <4>; 263 clocks = <&ccu CLK_BUS_UART3>; 264 resets = <&ccu RST_BUS_UART3>; 265 status = "disabled"; 266 }; 267 268 uart4: serial@2501000 { 269 compatible = "snps,dw-apb-uart"; 270 reg = <0x02501000 0x400>; 271 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 272 reg-shift = <2>; 273 reg-io-width = <4>; 274 clocks = <&ccu CLK_BUS_UART4>; 275 resets = <&ccu RST_BUS_UART4>; 276 status = "disabled"; 277 }; 278 279 uart5: serial@2501400 { 280 compatible = "snps,dw-apb-uart"; 281 reg = <0x02501400 0x400>; 282 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 283 reg-shift = <2>; 284 reg-io-width = <4>; 285 clocks = <&ccu CLK_BUS_UART5>; 286 resets = <&ccu RST_BUS_UART5>; 287 status = "disabled"; 288 }; 289 290 uart6: serial@2501800 { 291 compatible = "snps,dw-apb-uart"; 292 reg = <0x02501800 0x400>; 293 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 294 reg-shift = <2>; 295 reg-io-width = <4>; 296 clocks = <&ccu CLK_BUS_UART6>; 297 resets = <&ccu RST_BUS_UART6>; 298 status = "disabled"; 299 }; 300 301 uart7: serial@2501c00 { 302 compatible = "snps,dw-apb-uart"; 303 reg = <0x02501c00 0x400>; 304 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 305 reg-shift = <2>; 306 reg-io-width = <4>; 307 clocks = <&ccu CLK_BUS_UART7>; 308 resets = <&ccu RST_BUS_UART7>; 309 status = "disabled"; 310 }; 311 312 i2c0: i2c@2502000 { 313 compatible = "allwinner,sun55i-a523-i2c", 314 "allwinner,sun8i-v536-i2c", 315 "allwinner,sun6i-a31-i2c"; 316 reg = <0x2502000 0x400>; 317 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&ccu CLK_BUS_I2C0>; 319 resets = <&ccu RST_BUS_I2C0>; 320 status = "disabled"; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 }; 324 325 i2c1: i2c@2502400 { 326 compatible = "allwinner,sun55i-a523-i2c", 327 "allwinner,sun8i-v536-i2c", 328 "allwinner,sun6i-a31-i2c"; 329 reg = <0x2502400 0x400>; 330 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&ccu CLK_BUS_I2C1>; 332 resets = <&ccu RST_BUS_I2C1>; 333 status = "disabled"; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 }; 337 338 i2c2: i2c@2502800 { 339 compatible = "allwinner,sun55i-a523-i2c", 340 "allwinner,sun8i-v536-i2c", 341 "allwinner,sun6i-a31-i2c"; 342 reg = <0x2502800 0x400>; 343 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&ccu CLK_BUS_I2C2>; 345 resets = <&ccu RST_BUS_I2C2>; 346 status = "disabled"; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 }; 350 351 i2c3: i2c@2502c00 { 352 compatible = "allwinner,sun55i-a523-i2c", 353 "allwinner,sun8i-v536-i2c", 354 "allwinner,sun6i-a31-i2c"; 355 reg = <0x2502c00 0x400>; 356 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&ccu CLK_BUS_I2C3>; 358 resets = <&ccu RST_BUS_I2C3>; 359 status = "disabled"; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 }; 363 364 i2c4: i2c@2503000 { 365 compatible = "allwinner,sun55i-a523-i2c", 366 "allwinner,sun8i-v536-i2c", 367 "allwinner,sun6i-a31-i2c"; 368 reg = <0x2503000 0x400>; 369 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&ccu CLK_BUS_I2C4>; 371 resets = <&ccu RST_BUS_I2C4>; 372 status = "disabled"; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 }; 376 377 i2c5: i2c@2503400 { 378 compatible = "allwinner,sun55i-a523-i2c", 379 "allwinner,sun8i-v536-i2c", 380 "allwinner,sun6i-a31-i2c"; 381 reg = <0x2503400 0x400>; 382 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&ccu CLK_BUS_I2C5>; 384 resets = <&ccu RST_BUS_I2C5>; 385 status = "disabled"; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 }; 389 390 syscon: syscon@3000000 { 391 compatible = "allwinner,sun55i-a523-system-control", 392 "allwinner,sun50i-a64-system-control"; 393 reg = <0x03000000 0x1000>; 394 #address-cells = <1>; 395 #size-cells = <1>; 396 ranges; 397 }; 398 399 sid: efuse@3006000 { 400 compatible = "allwinner,sun55i-a523-sid", 401 "allwinner,sun50i-a64-sid"; 402 reg = <0x03006000 0x1000>; 403 #address-cells = <1>; 404 #size-cells = <1>; 405 }; 406 407 gic: interrupt-controller@3400000 { 408 compatible = "arm,gic-v3"; 409 #address-cells = <1>; 410 #interrupt-cells = <3>; 411 #size-cells = <1>; 412 ranges; 413 interrupt-controller; 414 reg = <0x3400000 0x10000>, 415 <0x3460000 0x100000>; 416 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 417 dma-noncoherent; 418 419 its: msi-controller@3440000 { 420 compatible = "arm,gic-v3-its"; 421 reg = <0x3440000 0x20000>; 422 msi-controller; 423 #msi-cells = <1>; 424 dma-noncoherent; 425 }; 426 }; 427 428 mmc0: mmc@4020000 { 429 compatible = "allwinner,sun55i-a523-mmc", 430 "allwinner,sun20i-d1-mmc"; 431 reg = <0x04020000 0x1000>; 432 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 433 clock-names = "ahb", "mmc"; 434 resets = <&ccu RST_BUS_MMC0>; 435 reset-names = "ahb"; 436 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 437 pinctrl-names = "default"; 438 pinctrl-0 = <&mmc0_pins>; 439 status = "disabled"; 440 441 max-frequency = <150000000>; 442 cap-sd-highspeed; 443 cap-mmc-highspeed; 444 cap-sdio-irq; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 }; 448 449 mmc1: mmc@4021000 { 450 compatible = "allwinner,sun55i-a523-mmc", 451 "allwinner,sun20i-d1-mmc"; 452 reg = <0x04021000 0x1000>; 453 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 454 clock-names = "ahb", "mmc"; 455 resets = <&ccu RST_BUS_MMC1>; 456 reset-names = "ahb"; 457 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&mmc1_pins>; 460 status = "disabled"; 461 462 max-frequency = <150000000>; 463 cap-sd-highspeed; 464 cap-mmc-highspeed; 465 cap-sdio-irq; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 }; 469 470 mmc2: mmc@4022000 { 471 compatible = "allwinner,sun55i-a523-mmc", 472 "allwinner,sun20i-d1-mmc"; 473 reg = <0x04022000 0x1000>; 474 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 475 clock-names = "ahb", "mmc"; 476 resets = <&ccu RST_BUS_MMC2>; 477 reset-names = "ahb"; 478 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&mmc2_pins>; 481 status = "disabled"; 482 483 max-frequency = <150000000>; 484 cap-sd-highspeed; 485 cap-mmc-highspeed; 486 cap-sdio-irq; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 }; 490 491 usb_otg: usb@4100000 { 492 compatible = "allwinner,sun55i-a523-musb", 493 "allwinner,sun8i-a33-musb"; 494 reg = <0x4100000 0x400>; 495 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 496 interrupt-names = "mc"; 497 clocks = <&ccu CLK_BUS_OTG>; 498 resets = <&ccu RST_BUS_OTG>; 499 extcon = <&usbphy 0>; 500 phys = <&usbphy 0>; 501 phy-names = "usb"; 502 status = "disabled"; 503 }; 504 505 usbphy: phy@4100400 { 506 compatible = "allwinner,sun55i-a523-usb-phy", 507 "allwinner,sun20i-d1-usb-phy"; 508 reg = <0x4100400 0x100>, 509 <0x4101800 0x100>, 510 <0x4200800 0x100>; 511 reg-names = "phy_ctrl", 512 "pmu0", 513 "pmu1"; 514 clocks = <&osc24M>, 515 <&osc24M>; 516 clock-names = "usb0_phy", 517 "usb1_phy"; 518 resets = <&ccu RST_USB_PHY0>, 519 <&ccu RST_USB_PHY1>; 520 reset-names = "usb0_reset", 521 "usb1_reset"; 522 status = "disabled"; 523 #phy-cells = <1>; 524 }; 525 526 ehci0: usb@4101000 { 527 compatible = "allwinner,sun55i-a523-ehci", 528 "generic-ehci"; 529 reg = <0x4101000 0x100>; 530 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&ccu CLK_BUS_OHCI0>, 532 <&ccu CLK_BUS_EHCI0>, 533 <&ccu CLK_USB_OHCI0>; 534 resets = <&ccu RST_BUS_OHCI0>, 535 <&ccu RST_BUS_EHCI0>; 536 phys = <&usbphy 0>; 537 phy-names = "usb"; 538 status = "disabled"; 539 }; 540 541 ohci0: usb@4101400 { 542 compatible = "allwinner,sun55i-a523-ohci", 543 "generic-ohci"; 544 reg = <0x4101400 0x100>; 545 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&ccu CLK_BUS_OHCI0>, 547 <&ccu CLK_USB_OHCI0>; 548 resets = <&ccu RST_BUS_OHCI0>; 549 phys = <&usbphy 0>; 550 phy-names = "usb"; 551 status = "disabled"; 552 }; 553 554 ehci1: usb@4200000 { 555 compatible = "allwinner,sun55i-a523-ehci", 556 "generic-ehci"; 557 reg = <0x4200000 0x100>; 558 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&ccu CLK_BUS_OHCI1>, 560 <&ccu CLK_BUS_EHCI1>, 561 <&ccu CLK_USB_OHCI1>; 562 resets = <&ccu RST_BUS_OHCI1>, 563 <&ccu RST_BUS_EHCI1>; 564 phys = <&usbphy 1>; 565 phy-names = "usb"; 566 status = "disabled"; 567 }; 568 569 ohci1: usb@4200400 { 570 compatible = "allwinner,sun55i-a523-ohci", 571 "generic-ohci"; 572 reg = <0x4200400 0x100>; 573 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&ccu CLK_BUS_OHCI1>, 575 <&ccu CLK_USB_OHCI1>; 576 resets = <&ccu RST_BUS_OHCI1>; 577 phys = <&usbphy 1>; 578 phy-names = "usb"; 579 status = "disabled"; 580 }; 581 582 gmac0: ethernet@4500000 { 583 compatible = "allwinner,sun55i-a523-gmac0", 584 "allwinner,sun50i-a64-emac"; 585 reg = <0x04500000 0x10000>; 586 clocks = <&ccu CLK_BUS_EMAC0>; 587 clock-names = "stmmaceth"; 588 resets = <&ccu RST_BUS_EMAC0>; 589 reset-names = "stmmaceth"; 590 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 591 interrupt-names = "macirq"; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&rgmii0_pins>; 594 syscon = <&syscon>; 595 status = "disabled"; 596 597 mdio0: mdio { 598 compatible = "snps,dwmac-mdio"; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 }; 602 }; 603 604 ppu: power-controller@7001400 { 605 compatible = "allwinner,sun55i-a523-ppu"; 606 reg = <0x07001400 0x400>; 607 clocks = <&r_ccu CLK_BUS_R_PPU1>; 608 resets = <&r_ccu RST_BUS_R_PPU1>; 609 #power-domain-cells = <1>; 610 }; 611 612 r_ccu: clock-controller@7010000 { 613 compatible = "allwinner,sun55i-a523-r-ccu"; 614 reg = <0x7010000 0x250>; 615 clocks = <&osc24M>, 616 <&rtc CLK_OSC32K>, 617 <&rtc CLK_IOSC>, 618 <&ccu CLK_PLL_PERIPH0_200M>, 619 <&ccu CLK_PLL_AUDIO0_4X>; 620 clock-names = "hosc", 621 "losc", 622 "iosc", 623 "pll-periph", 624 "pll-audio"; 625 #clock-cells = <1>; 626 #reset-cells = <1>; 627 }; 628 629 nmi_intc: interrupt-controller@7010320 { 630 compatible = "allwinner,sun55i-a523-nmi"; 631 reg = <0x07010320 0xc>; 632 interrupt-controller; 633 #interrupt-cells = <2>; 634 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 635 }; 636 637 r_pio: pinctrl@7022000 { 638 compatible = "allwinner,sun55i-a523-r-pinctrl"; 639 reg = <0x7022000 0x800>; 640 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&r_ccu CLK_R_APB0>, 643 <&osc24M>, 644 <&rtc CLK_OSC32K>; 645 clock-names = "apb", "hosc", "losc"; 646 gpio-controller; 647 #gpio-cells = <3>; 648 interrupt-controller; 649 #interrupt-cells = <3>; 650 651 r_i2c_pins: r-i2c-pins { 652 pins = "PL0" ,"PL1"; 653 allwinner,pinmux = <2>; 654 function = "r_i2c0"; 655 }; 656 }; 657 658 pck600: power-controller@7060000 { 659 compatible = "allwinner,sun55i-a523-pck-600"; 660 reg = <0x07060000 0x8000>; 661 clocks = <&r_ccu CLK_BUS_R_PPU0>; 662 resets = <&r_ccu RST_BUS_R_PPU0>; 663 #power-domain-cells = <1>; 664 }; 665 666 r_i2c0: i2c@7081400 { 667 compatible = "allwinner,sun55i-a523-i2c", 668 "allwinner,sun8i-v536-i2c", 669 "allwinner,sun6i-a31-i2c"; 670 reg = <0x07081400 0x400>; 671 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&r_ccu CLK_BUS_R_I2C0>; 673 resets = <&r_ccu RST_BUS_R_I2C0>; 674 pinctrl-names = "default"; 675 pinctrl-0 = <&r_i2c_pins>; 676 status = "disabled"; 677 678 #address-cells = <1>; 679 #size-cells = <0>; 680 }; 681 682 rtc: rtc@7090000 { 683 compatible = "allwinner,sun55i-a523-rtc", 684 "allwinner,sun50i-r329-rtc"; 685 reg = <0x7090000 0x400>; 686 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&r_ccu CLK_BUS_R_RTC>, 688 <&osc24M>, 689 <&r_ccu CLK_R_AHB>; 690 clock-names = "bus", "hosc", "ahb"; 691 #clock-cells = <1>; 692 }; 693 }; 694}; 695